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1. 发明授权

US08571513B2 Integrated circuit passive signal distribution 有权
标题翻译：集成电路无源信号分配
公开(公告)号：US08571513B2
公开(公告)日：2013-10-29
申请号：US13540500
申请日：2012-07-02
申请人： Frank O'Mahony , Bryan Casper , James Jaussi , Matthew B. Haycock , Joseph Kennedy , Mozhgan Mansuri , Stephen R. Mooney
发明人： Frank O'Mahony , Bryan Casper , James Jaussi , Matthew B. Haycock , Joseph Kennedy , Mozhgan Mansuri , Stephen R. Mooney
IPC分类号： H04B1/28
CPC分类号： H04L25/0278 , H03K5/15013 , H04L25/0292 , H04L25/0298
摘要： For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.
摘要翻译：对于一个公开的实施例，集成电路可以包括集成电路的一个或多个层中的内部传输线。内部传输线可以被耦合以在内部传输线的第一端处接收来自外部传输线的信号，而不使用终端电路。内部传输线路可以将信号被动地发送到内部传输线路的第二端。集成电路还可以包括第一电路，其具有在内部传输线的第一位置处耦合到内部传输线的输入以接收信号，并且第二电路具有在内部传输的第二位置处耦合到内部传输线的输入线接收信号。第二位置可以不同于第一位置。还公开了其他实施例。

2. 发明授权

US07222208B1 Simultaneous bidirectional port with synchronization circuit to synchronize the port with another port 失效
标题翻译：具有同步电路的双向口同步端口与另一端口同步
公开(公告)号：US07222208B1
公开(公告)日：2007-05-22
申请号：US09644463
申请日：2000-08-23
申请人： Matthew B. Haycock , Amaresh Pangal
发明人： Matthew B. Haycock , Amaresh Pangal
IPC分类号： G06F1/00 , H03K19/175
CPC分类号： G06F13/4077
摘要： A simultaneous bidirectional port coupled to a bus includes a synchronization circuit that synchronizes the port with another simultaneous data port coupled to the same bus. The synchronization circuit includes an output driver having an imbalanced output impedance, and includes a receiver with input hysteresis. The input hysteresis of the receiver is not satisfied unless both drivers with imbalanced output impedance coupled to the bus assert an output signal. Each driver asserts a signal on the bus when initialization of the corresponding simultaneous bidirectional port is complete. When both simultaneous bidirectional ports are initialized, the hysteresis of the receivers is satisfied, and each port is notified that both have been initialized.
摘要翻译：耦合到总线的同时双向端口包括同步电路，该同步电路使端口与耦合到同一总线的另一同时数据端口同步。同步电路包括具有不平衡输出阻抗的输出驱动器，并且包括具有输入滞后的接收器。接收器的输入滞后不能满足，除非与总线耦合的不平衡输出阻抗的驱动器都断言输出信号。当对应的同时双向端口的初始化完成时，每个驱动器在总线上断言信号。当两个同时双向端口被初始化时，接收器的滞后被满足，并且通知两个端口都被初始化。

3. 发明授权

US06847617B2 Systems for interchip communication 有权
标题翻译：芯片间通信系统
公开(公告)号：US06847617B2
公开(公告)日：2005-01-25
申请号：US09817659
申请日：2001-03-26
申请人： Shekhar Y Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
发明人： Shekhar Y Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
IPC分类号： G06F13/00 , G06F13/38 , G06F13/40 , H04L12/28
CPC分类号： G06F13/4086
摘要： In some embodiments, the invention involves a system having a first group of integrated circuits connected in a truncated ring fashion, wherein the truncated ring includes a truncated region to allow for additional integrated circuits to be added to the ring. In some embodiments, the invention involves a system having a group of integrated circuits connected in a pseudo ring fashion, wherein the pseudo ring is created by data flow of bi-directional signaling between the integrated circuits. In some embodiments, the invention involves a system having a group of integrated circuits connected in a pseudo differential arrangement in which multiple conductors carrying signals share a common reference signal conductor.
摘要翻译：在一些实施例中，本发明涉及具有以截头环方式连接的第一组集成电路的系统，其中所述截头环包括截取的区域，以允许将额外的集成电路添加到所述环中。在一些实施例中，本发明涉及具有以伪环方式连接的一组集成电路的系统，其中通过集成电路之间的双向信令的数据流创建伪环。在一些实施例中，本发明涉及一种具有以伪差分布置连接的一组集成电路的系统，其中携带多个导体的信号共用公共参考信号导体。

4. 发明授权

US06791356B2 Bidirectional port with clock channel used for synchronization 有权
标题翻译：具有时钟通道的双向端口用于同步
公开(公告)号：US06791356B2
公开(公告)日：2004-09-14
申请号：US09894865
申请日：2001-06-28
申请人： Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin
发明人： Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin
IPC分类号： H03K190175
CPC分类号： G06F13/4077
摘要： A simultaneous bidirectional port coupled to a bus combines a synchronization circuit and a clock circuit. The synchronization and clock circuit synchronizes the port with another simultaneous data port coupled to the same bus. A clock driver circuit is provided that is capable of being turned on and off. Prior to synchronization, the clock driver is off, and after synchronization, the clock driver is on. A clock receiver circuit includes a clock detection circuit to detect the presence of an input clock signal. When an integrated circuit is ready to communicate, the output clock driver is turned on and the clock detection circuit is monitored to determine when an input clock signal is received. When both the output clock driver is turned on, and an input clock signal is being received, the simultaneous bidirectional port is synchronized, and communication between integrated circuits can take place.
摘要翻译：耦合到总线的同时双向端口组合同步电路和时钟电路。同步和时钟电路将端口与耦合到同一总线的另一个同时的数据端口同步。提供能够打开和关闭的时钟驱动器电路。在同步之前，时钟驱动程序关闭，并且在同步之后，时钟驱动程序处于打开状态。时钟接收器电路包括用于检测输入时钟信号的存在的时钟检测电路。当集成电路准备好通信时，输出时钟驱动器导通，监视时钟检测电路，以确定何时接收输入时钟信号。当输出时钟驱动器都打开并且正在接收输入时钟信号时，同时双向端口被同步，并且可以发生集成电路之间的通信。

5. 发明授权

US06747474B2 Integrated circuit stubs in a point-to-point system 有权
标题翻译：集成电路存根在点对点系统中
公开(公告)号：US06747474B2
公开(公告)日：2004-06-08
申请号：US09797480
申请日：2001-02-28
申请人： Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
发明人： Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
IPC分类号： H03K1716
CPC分类号： H04L5/14 , H03K19/01759 , H04L25/0278 , H04L25/24
摘要： In some embodiments, the invention involves multiple integrated circuit stubs coupled in series. At least one of the integrated circuit stubs including first conductors to receive signals from a first adjacent one of the integrated circuit stubs, second conductors to provide signals to a second adjacent one of the integrated circuit stubs, and third conductors to provide signals to an integrated circuit chip. The integrated circuit stubs include first drivers and second drivers coupled to the first, second, and third conductors, wherein the first drivers receive the external signals from the first conductors and drive them onto the second conductors and the second drivers receive signals from the first conductors and drive them onto the third conductors.
摘要翻译：在一些实施例中，本发明涉及串联耦合的多个集成电路短截线。所述集成电路短截线中的至少一个包括用于接收来自所述集成电路短截线中的第一相邻一个的信号的第一导体，用于向所述集成电路短截线中的第二相邻组件提供信号的第二导体以及向集成电路短截线提供信号的第三导体电路芯片。集成电路短截线包括耦合到第一，第二和第三导体的第一驱动器和第二驱动器，其中第一驱动器接收来自第一导体的外部信号并将它们驱动到第二导体上，并且第二驱动器从第一导体接收信号并将它们驱动到第三导体上。

6. 发明授权

US06741107B2 Synchronous clock generator for integrated circuits 有权
标题翻译：用于集成电路的同步时钟发生器
公开(公告)号：US06741107B2
公开(公告)日：2004-05-25
申请号：US09802584
申请日：2001-03-08
申请人： Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
发明人： Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
IPC分类号： H03L700
CPC分类号： H03L7/0805 , H03L7/0812
摘要： A synchronous clock generator for an integrated circuit is described in which a delay lock loop circuit may be used to delay a first input signal. A delay circuit is coupled to the delay lock loop circuit and receives a control voltage from the delay lock loop circuit, which is used to delay a second input signal. The first and second input signal may be complimentary.
摘要翻译：描述了用于集成电路的同步时钟发生器，其中可以使用延迟锁定环路来延迟第一输入信号。延迟电路耦合到延迟锁定环电路并且从延迟锁定环路电路接收用于延迟第二输入信号的控制电压。第一和第二输入信号可以是互补的。

7. 发明授权

US06536025B2 Receiver deskewing of multiple source synchronous bits from a parallel bus 失效
公开(公告)号：US06536025B2
公开(公告)日：2003-03-18
申请号：US09858346
申请日：2001-05-14
申请人： Joseph T. Kennedy , Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin
发明人： Joseph T. Kennedy , Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin
IPC分类号： G06F1750
CPC分类号： G06F13/4217
摘要： A receiver integrated circuit (IC) die or functional unit has deskew circuitry to reduce bit-to-bit timing variation that is no more than one bit time interval in a number of bits that are received, before validating the capture of the bits using a transition in a received strobe signal. The data bits and the strobe signal are driven in a parallel bus section that may be part of a shared multi-drop bus or a point-to-point bus. The system applications include interfacing to a processor or memory bus of a computer system.

8. 发明授权

US07177288B2 Simultaneous transmission and reception of signals in different frequency bands over a bus line 有权
标题翻译：在总线上同时发送和接收不同频段的信号
公开(公告)号：US07177288B2
公开(公告)日：2007-02-13
申请号：US09998008
申请日：2001-11-28
申请人： Stephen R. Mooney , Aaron K. Martin , Matthew B. Haycock , Bryan K. Casper , Shekhar Y. Borkar , Joseph T. Kennedy , James E. Jaussi
发明人： Stephen R. Mooney , Aaron K. Martin , Matthew B. Haycock , Bryan K. Casper , Shekhar Y. Borkar , Joseph T. Kennedy , James E. Jaussi
IPC分类号： H04L5/14
CPC分类号： H04L5/1423
摘要： A device includes a bus, a first transmitter connected to the bus and configured to transmit a first signal over the bus in a first frequency band, a second transmitter connected to the bus and configured to transmit a second signal over the bus in a second frequency band at the same time that the first transmitter is transmitting the first signal, a first receiver connected to the bus and configured to receive the first signal transmitted over the bus in the first frequency band, and a second receiver connected to the bus and configured to receive the second signal transmitted over the bus in the second frequency band. The first frequency band and the second frequency band occupy different portions of the frequency spectrum.
摘要翻译：一种设备包括总线，连接到总线的第一发射机，并且被配置为在第一频带中通过总线传输第一信号，第二发射器连接到总线并且被配置为以第二频率通过总线发送第二信号与第一发射机正在发送第一信号的同时，连接到总线并被配置为接收通过总线在第一频带中发送的第一信号的第一接收机和连接到总线的第二接收机，并且被配置为接收在第二频带中通过总线发送的第二信号。第一频带和第二频带占据频谱的不同部分。

9. 发明授权

US06901526B1 Digital bus synchronizer for generating read reset signal 失效
公开(公告)号：US06901526B1
公开(公告)日：2005-05-31
申请号：US09709001
申请日：2000-11-08
申请人： Matthew B. Haycock , Amaresh Pangal
发明人： Matthew B. Haycock , Amaresh Pangal
IPC分类号： G06F1/04 , G06F1/12 , H03K19/00
CPC分类号： G06F1/12
摘要： A digital bus includes a transmitter unit, a receiver unit, and a transmission medium to couple the transmitter unit to the receiver unit and to provide a path for exchanging information between the transmitter unit and the receiver unit. The receiver unit includes a first-in-first-out (FIFO) unit and a synchronizer unit for receiving information from the transmitter unit. The synchronizer unit receives a plurality of write clock signals and a reset signal and generates a read reset signal positioned with respect to the plurality write clock signals and a sample clock signal. The read reset signal has a latency with respect to each of the plurality of write reset signals of between 0 and 1 clock cycles.

10. 发明授权

US06718416B1 Method and apparatus for removing and installing a computer system bus agent without powering down the computer system 有权
标题翻译：用于移除和安装计算机系统总线代理而不关闭计算机系统的方法和装置
公开(公告)号：US06718416B1
公开(公告)日：2004-04-06
申请号：US09643379
申请日：2000-08-21
申请人： Keith M. Self , Matthew B. Haycock
发明人： Keith M. Self , Matthew B. Haycock
IPC分类号： G06F1300
CPC分类号： G06F13/4081
摘要： An example embodiment of a computer system that includes a removable agent that can be removed or installed without powering down the system includes a fixed bus agent and the replaceable bus agent. The fixed bus agent and the replaceable bus agent are electrically coupled together by a presence detect signal, a synchronization signal, and a data bus. A deassertion of the presence detect signal indicates to the fixed bus agent that the removable bus agent has been disconnected and is no longer electrically coupled to the fixed bus agent. The fixed bus agent then tri-states its outputs and also prevents potentially invalid data from being delivered to the core circuitry of the fixed bus agent. An assertion of the presence detect signal indicates to the fixed bus agent that the replaceable bus agent is electrically connected to the fixed bus agent. In response to the assertion of the presence detect signal, the fixed bus agent and the replaceable bus agent enter reset periods. Following the reset periods and when each bus agent is ready to communicate to the other agent, the fixed bus agent and the replaceable bus agent signal to each other over the synchronization signal that each is ready to begin communication over the data bus.
摘要翻译：包括可以在不关闭系统的情况下被移除或安装的可移除代理的计算机系统的示例性实施例包括固定总线代理和可更换总线代理。固定总线代理和可更换总线代理通过存在检测信号，同步信号和数据总线电耦合在一起。存在检测信号的取消表示向固定总线代理指示可移除总线代理已经断开并且不再电耦合到固定总线代理。然后，固定总线代理器对其输出进行三态，并且还防止潜在的无效数据被传递到固定总线代理的核心电路。存在检测信号的断言向固定总线代理指示可更换总线代理电连接到固定总线代理。响应于存在检测信号的确认，固定总线代理和可更换总线代理进入复位周期。在复位周期之后，当每个总线代理准备好与其他代理通信时，固定总线代理和可更换总线代理器通过同步信号相互信号，每个同步信号准备好通过数据总线开始通信。

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