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1. 发明授权

US6151257A Apparatus for receiving/transmitting signals in an input/output pad buffer cell 失效
标题翻译：用于在输入/输出缓冲单元中接收/发送信号的装置
公开(公告)号：US6151257A
公开(公告)日：2000-11-21
申请号：US13482
申请日：1998-01-26
申请人： Smith E. Jeffrey , Timothy W. Kelly , Stephen W. Kiss , Keith M. Self
发明人： Smith E. Jeffrey , Timothy W. Kelly , Stephen W. Kiss , Keith M. Self
IPC分类号： G11C7/10 , H03K19/003 , G11C7/00
CPC分类号： G11C7/1093 , G11C7/1051 , G11C7/1078 , G11C7/1087 , H03K19/00323
摘要： An electronic circuit die is presented including a plurality of first and second input/output (I/O) pad buffer cells. The first I/O pad buffer cells include at least a latch for latching data signals received at a pad in the cell. Adjacent ones of these first I/O pad buffer cells are conductively coupled together using conductive trace pins. The second I/O pad buffer cells include a pad that receives clocking signal which are supplied to the latches of the first I/O pad buffer cells. Accordingly, data signals received at the pads of the die are latched in the pad as opposed to the core logic of the die. One benefit of providing the latching of data signals in the pad is that conductive traces between the latches and the core logic need not be precisely matched, thus reducing cost. Also, the first I/O pad buffer cells can be similarly constructed, thus reducing the complexity and cost of manufacture for the die.
摘要翻译：呈现包括多个第一和第二输入/输出（I / O）缓冲区单元的电子电路管芯。第一I / O缓冲单元至少包括用于锁存在单元中的垫处接收的数据信号的锁存器。这些第一I / O焊盘缓冲单元中的相邻的一个使用导电迹线引脚导电耦合在一起。第二I / O焊盘缓冲单元包括接收提供给第一I / O缓冲单元的锁存器的时钟信号的焊盘。因此，与芯片的核心逻辑相反，在芯片的焊盘处接收的数据信号被锁存在焊盘中。在焊盘中提供数据信号锁存的一个好处是锁存器和核心逻辑之间的导电迹线不需要精确匹配，从而降低了成本。此外，可以类似地构造第一I / O缓冲电池，从而降低了芯片制造的复杂性和成本。

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