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1. 发明申请

US20080127485A1 VENTS WITH SIGNAL IMAGE FOR SIGNAL RETURN PATH 审中-公开
标题翻译：具有信号返回路径的信号图像的信息
公开(公告)号：US20080127485A1
公开(公告)日：2008-06-05
申请号：US11968695
申请日：2008-01-03
申请人： Timothy W. Budell , Thomas P. Camino , Todd W. Davies , Ross W. Keesler , Steven G. Rosser , David B. Stone
发明人： Timothy W. Budell , Thomas P. Camino , Todd W. Davies , Ross W. Keesler , Steven G. Rosser , David B. Stone
IPC分类号： H05K3/20 , H05K3/07
CPC分类号： H05K1/0224 , H05K1/0253 , H05K2201/0715 , H05K2201/093 , H05K2201/09672 , H05K2201/09681 , H05K2201/0969 , H05K2203/1178 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156
摘要： A method for forming an electrical structure. A dielectric substrate having a metal signal line therein is provided. A first metal voltage plane is laminated to a first surface of the dielectric substrate. An opening in the first metal voltage plane is formed such that a first electrically conductive strip across the opening includes an image of a first portion of the metal signal line, wherein the image of the first portion of the metal signal line projects across the opening in the first metal voltage plane. A signal current is flowed through the metal signal line, wherein the signal current is an alternating current. A return current is flowed through the first electrically conductive strip, wherein the return current includes a portion of the signal current.
摘要翻译：一种形成电结构的方法。提供其中具有金属信号线的电介质基片。将第一金属电压平面层叠到电介质基板的第一表面上。第一金属电压平面中的开口形成为使得穿过开口的第一导电条包括金属信号线的第一部分的图像，其中金属信号线的第一部分的图像跨越开口突出第一个金属电压平面。信号电流流过金属信号线，其中信号电流是交流电流。返回电流流过第一导电条，其中返回电流包括信号电流的一部分。

2. 发明授权

US07351917B2 Vents with signal image for signal return path 有权
标题翻译：具有信号图像的通风口用于信号返回路径
公开(公告)号：US07351917B2
公开(公告)日：2008-04-01
申请号：US11251745
申请日：2005-10-17
申请人： Timothy W. Budell , Thomas P. Comino , Todd W. Davies , Ross W. Keesler , Steven G. Rosser , David B. Stone
发明人： Timothy W. Budell , Thomas P. Comino , Todd W. Davies , Ross W. Keesler , Steven G. Rosser , David B. Stone
IPC分类号： H01R12/04 , H05K1/11
CPC分类号： H05K1/0224 , H05K1/0253 , H05K2201/0715 , H05K2201/093 , H05K2201/09672 , H05K2201/09681 , H05K2201/0969 , H05K2203/1178 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156
摘要： A method, structure, and method of design relating an electrical structure that includes a metal voltage plane laminated to a dielectric substrate. A determination is made as to where to place an opening for venting gases generated during fabrication of the dielectric laminate. An identification is made of a problematic opening in the metal voltage plane that is above or below a corresponding metal signal line within the dielectric laminate, such that an image of a portion of the corresponding metal signal line projects across the problematic opening. An electrically conductive strip is positioned across the problematic opening, such that the strip includes the image. In fabrication, the dielectric substrate having the metal signal line therein is provided. The metal voltage plane is laminated to the dielectric substrate. The opening in the metal voltage plane is formed such that the strip is across the opening and includes the image.
摘要翻译：一种设计的方法，结构和方法，涉及包括层叠在电介质基板上的金属电压平面的电结构。确定在电介质层压板的制造过程中产生的排出气体的位置在何处放置。识别金属电压平面中的有问题的开口，其高于或低于介电层压板内的对应金属信号线，使得相应的金属信号线的一部分的图像跨越有问题的开口突出。导电条被放置在有问题的开口处，使得条带包括图像。在制造中，提供其中具有金属信号线的电介质基片。金属电压平面层压到电介质基片上。金属电压平面中的开口形成为使得条带穿过开口并且包括图像。

3. 发明授权

US06977345B2 Vents with signal image for signal return path 失效
标题翻译：具有信号图像的通风口用于信号返回路径
公开(公告)号：US06977345B2
公开(公告)日：2005-12-20
申请号：US10042031
申请日：2002-01-08
申请人： Timothy W. Budell , Thomas P. Comino , Todd W. Davies , Ross W. Keesler , Steven G. Rosser , David B. Stone
发明人： Timothy W. Budell , Thomas P. Comino , Todd W. Davies , Ross W. Keesler , Steven G. Rosser , David B. Stone
IPC分类号： H05K1/02 , H05K1/00
CPC分类号： H05K1/0224 , H05K1/0253 , H05K2201/0715 , H05K2201/093 , H05K2201/09672 , H05K2201/09681 , H05K2201/0969 , H05K2203/1178 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156
摘要： A method, structure, and method of design relating an electrical structure that includes a metal voltage plane laminated to a dielectric substrate. A determination is made as to where to place an opening for venting gases generated during fabrication of the dielectric laminate. An identification is made of a problematic opening in the metal voltage plane that is above or below a corresponding metal signal line within the dielectric laminate, such that an image of a portion of the corresponding metal signal line projects across the problematic opening. An electrically conductive strip is positioned across the problematic opening, such that the strip includes the image. In fabrication, the dielectric substrate having the metal signal line therein is provided. The metal voltage plane is laminated to the dielectric substrate. The opening in the metal voltage plane is formed such that the strip is across the opening and includes the image.
摘要翻译：一种设计的方法，结构和方法，涉及包括层叠在电介质基板上的金属电压平面的电结构。确定在电介质层压板的制造过程中产生的排出气体的位置在何处放置。识别金属电压平面中的有问题的开口，其高于或低于介电层压板内的对应金属信号线，使得相应的金属信号线的一部分的图像跨越有问题的开口突出。导电条被放置在有问题的开口处，使得条带包括图像。在制造中，提供其中具有金属信号线的电介质基片。金属电压平面层压到电介质基片上。金属电压平面中的开口形成为使得条带穿过开口并且包括图像。

4. 发明授权

US07196908B2 Dual pitch contact pad footprint for flip-chip chips and modules 失效
标题翻译：用于倒装芯片和模块的双音高接触焊盘尺寸
公开(公告)号：US07196908B2
公开(公告)日：2007-03-27
申请号：US10455982
申请日：2003-06-05
申请人： Timothy W. Budell , David B. Stone , Jerzy M. Zalesinski
发明人： Timothy W. Budell , David B. Stone , Jerzy M. Zalesinski
IPC分类号： H05K7/10
CPC分类号： H01L23/49838 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16235 , H01L2924/00014 , H01L2924/15174 , H01L2924/15312 , H05K1/111 , H05K2201/09227 , H05K2201/10674 , Y02P70/611 , H01L2224/05599
摘要： An electronic device, including: a plurality of contacts pads on a surface of a substrate; the contacts pads spaced apart a first predetermined distance in a first direction; and the contact pads spaced apart a second predetermined distance in a second direction, the first predetermined distance different from the second predetermined distance, the first direction perpendicular to the second direction.
摘要翻译：一种电子设备，包括：在基板的表面上的多个接触焊盘; 所述接触垫在第一方向上间隔开第一预定距离; 并且所述接触垫在第二方向上间隔开第二预定距离，所述第一预定距离不同于所述第二预定距离，所述第一方向垂直于所述第二方向。

5. 发明授权

US06793500B1 Radial contact pad footprint and wiring for electrical components 失效
标题翻译：径向接触焊盘尺寸和电气元件接线
公开(公告)号：US06793500B1
公开(公告)日：2004-09-21
申请号：US10666607
申请日：2003-09-18
申请人： Timothy W. Budell , Esmaeil Rahmati , David B. Stone , Jerzy M. Zalesinski
发明人： Timothy W. Budell , Esmaeil Rahmati , David B. Stone , Jerzy M. Zalesinski
IPC分类号： H01R1200
CPC分类号： H01L23/50 , H01L23/49838 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/15312 , H05K1/0224 , H05K1/111 , H05K2201/09227 , H05K2201/093 , H05K2201/09418 , H05K2201/09681 , Y02P70/611 , H01L2224/05599
摘要： A structure and associated method comprising contact pads on a surface of a substrate for coupling signal, power, and ground connections for an electrical device to a plurality of conductive wires on the substrate. The contact pads are formed in single lines along radial edges of sectors on the substrate. Each of the sectors comprise a predetermined angle between the radial edges of each of the sectors. The plurality of sectors collectively form a circular area. The contact pads comprise signal, power, and ground connections located at predetermined positions on the single lines along the radial edges of each of the sectors on the substrate.
摘要翻译：一种结构和相关方法，包括在衬底的表面上的接触焊盘，用于将用于电气设备的信号，功率和接地连接耦合到衬底上的多个导电线。接触焊盘沿着衬底上的扇区的沿边缘沿单条线形成。每个扇区在每个扇区的径向边缘之间包括预定角度。多个扇区共同形成圆形区域。接触焊盘包括沿着衬底上每个扇区的径向边缘位于单个线上的预定位置处的信号，功率和接地连接。

6. 发明授权

US06978214B2 Validation of electrical performance of an electronic package prior to fabrication 失效
公开(公告)号：US06978214B2
公开(公告)日：2005-12-20
申请号：US10721966
申请日：2003-11-25
申请人： Timothy W. Budell , Patrick H. Buffet , Craig P. Lussier
发明人： Timothy W. Budell , Patrick H. Buffet , Craig P. Lussier
IPC分类号： G01R31/04 , G01R31/28 , G06F3/06 , G06F11/00 , G06F11/14 , G06F11/20 , G06F12/00 , G06F12/08 , G06F13/00 , G06F19/00
CPC分类号： G01R31/2853 , G01R31/2896 , G06F3/0622 , G06F3/0637 , G06F3/065 , G06F3/067 , G06F11/2069
摘要： An electrical resistance determination method. Input to the method includes a description of at least one electrical network within a substrate. The description includes specification of a plurality of first ports on a first side of the substrate, and a plurality of second ports on a second side of the substrate, for each electrical network. All of the first ports are electrically isolated from one another. All of the second ports are electrically connected to a common voltage. A computer readable program code, which is executed by a processor of a computer system computes for a first electrical network of the at least one electrical network an electrical resistance between each first port and a port of the second ports. The computer code may also display a perspective plot of the computed electrical resistances as a bar oriented about normal to each first port.

7. 发明授权

US08312404B2 Multi-segments modeling bond wire interconnects with 2D simulations in high speed, high density wire bond packages 有权
标题翻译：多段建模粘合线与高速，高密度线焊包装中的2D模拟互连
公开(公告)号：US08312404B2
公开(公告)日：2012-11-13
申请号：US12492198
申请日：2009-06-26
申请人： Haitian Hu , Timothy W. Budell , Charles S. Chiu , Eric Tremble
发明人： Haitian Hu , Timothy W. Budell , Charles S. Chiu , Eric Tremble
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , H01L23/552 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/4809 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/484 , H01L2224/49171 , H01L2224/49173 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01055 , H01L2924/01076 , H01L2924/09701 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A method for modeling bond wires in an IC package for predicting noise effects generated by electromagnetic coupling in complex bond wire configurations. A look-up table of equivalent LC circuit models for the bond wires is generated that accurately predicts the effects of the bond wire circuitry of a signal transmission system. Switch and mirror techniques are applied to reduce the bond wire configurations necessary to simulate. The method includes: setting parameters related to the IC package layout of groups of bond wires; sub-dividing each group of bond wires into regions, each including a portion of the bond wire or its corresponding pad, and generating dissection planes for the regions consisting of the bond wires; performing a 3D simulation on the regions consisting of the corresponding pads, and a 2D simulation for each dissection plane; constructing equivalent circuit models for groups of bond wires and corresponding pads based on the 3D and 2D simulations results; inputting the equivalent circuit models into a circuit simulator to measure the noise effects; and modifying the layout geometry to meet noise targets.
摘要翻译：一种用于在IC封装中建模接合线的方法，用于预测复杂接合线配置中由电磁耦合产生的噪声影响。产生用于接合线的等效LC电路模型的查找表，其精确地预测信号传输系统的接合线电路的影响。应用开关和镜像技术来减少模拟所需的接合线配置。该方法包括：设置与电线组IC封装布局有关的参数; 将每组接合线分割成区域，每个区域包括接合线的一部分或其对应的衬垫，并为由接合线组成的区域产生解剖平面; 在由相应的垫组成的区域上进行3D模拟，以及对每个解剖平面进行2D模拟; 基于3D和2D模拟结果构建了用于焊接线组和相应焊盘组的等效电路模型; 将等效电路模型输入到电路模拟器中以测量噪声影响; 并修改布局几何以满足噪声目标。

8. 发明授权

US07882469B2 Automatic verification of adequate conductive return-current paths 有权
标题翻译：自动验证足够的导通回路路径
公开(公告)号：US07882469B2
公开(公告)日：2011-02-01
申请号：US11945754
申请日：2007-11-27
申请人： Timothy W. Budell , David C. Reynolds , Eric W. Tremble
发明人： Timothy W. Budell , David C. Reynolds , Eric W. Tremble
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5081
摘要： After finding the shortest conductive signal return-current path for each signal, the invention assesses whether each conductive return-current path is adequate. The method analyzes each shortest conductive signal return-current path and determines if a significant portion of the signal return current flows as displacement current rather than following the conductive current path. A significant displacement current flows when the length of the conductive return-current path that diverges from a signal net is more than a previously defined limit based on the signal transition time. Further, a significant displacement current flows when the overall length of the signal differs from the overall length of the conductive return-current path by more than a previously defined limit based on the signal transition time.
摘要翻译：在找到每个信号的最短导通信号返回电流路径之后，本发明评估每个导通回路路径是否足够。该方法分析每个最短导通信号返回电流路径，并确定信号返回电流的有效部分是否以位移电流流动，而不是跟随导电电流路径。当从信号网发散的导电返回电流路径的长度大于基于信号转换时间的先前定义的极限时，显着的位移电流流动。此外，当信号的总长度与导电返回电流路径的总长度不同于基于信号转换时间的预先限定的极限时，显着的位移电流流动。

9. 发明授权

US07275229B2 Auto connection assignment system and method 失效
标题翻译：自动连接分配系统和方法
公开(公告)号：US07275229B2
公开(公告)日：2007-09-25
申请号：US11159915
申请日：2005-06-23
申请人： Adam Matthew Bittner , Timothy W. Budell , Robert C. Cusimano , Richard Dauphin , Matthew Thomas Guzowski , Craig Paul Lussier , David Brian Stone , Patrick G. Wilder
发明人： Adam Matthew Bittner , Timothy W. Budell , Robert C. Cusimano , Richard Dauphin , Matthew Thomas Guzowski , Craig Paul Lussier , David Brian Stone , Patrick G. Wilder
IPC分类号： G06F17/50
CPC分类号： H01L23/50 , G06F17/5077 , H01L2224/16225 , H01L2924/15174 , H01L2924/15311 , H01L2924/3011
摘要： A system and method for generating simulated wiring connections between first I/O terminals of a semiconductor device and second I/O terminals of a carrier. The method comprises identifying a plurality of first factors and instances of each first factor relating to a semiconductor device and identifying a plurality of second factors and instances of each second factor relating to a carrier. The first and second factors are associated with each other on a one-to-one basis. The instances of each first factor are correlated to the instances of each associated second factor on a one-to-one basis. A simulated wiring connection automatically is generated between each first I/O terminal and a matching second I/O terminal, subject to an identified instance of each first factor of each first I/O terminal being correlated to an identified instance of the associated second factor of the matching second I/O terminal.
摘要翻译：一种用于在半导体器件的第一I / O端子与载体的第二I / O端子之间产生模拟布线连接的系统和方法。该方法包括识别与半导体器件相关的每个第一因素的多个第一因素和实例，并且识别与载波相关的每个第二因素的多个第二因素和实例。第一和第二因素在一对一的基础上相互关联。每个第一因子的实例与每个相关联的第二因子的实例在一对一的基础上相关。在每个第一I / O终端和匹配的第二I / O终端之间自动生成模拟接线连接，受到每个第一I / O端子的每个第一因子的识别实例与相关联的第二因素的识别实例相关联的匹配第二个I / O端子。

10. 发明授权

US07197446B2 Hierarchical method of power supply noise and signal integrity analysis 失效
标题翻译：电源噪声和信号完整性分析的分层方法
公开(公告)号：US07197446B2
公开(公告)日：2007-03-27
申请号：US10711168
申请日：2004-08-30
申请人： Erik Breiland , Timothy W. Budell , Charles S. Chiu , Paul L. Clouser , Charles K. Erdelyi , Brian P. Welch
发明人： Erik Breiland , Timothy W. Budell , Charles S. Chiu , Paul L. Clouser , Charles K. Erdelyi , Brian P. Welch
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/78
摘要： The invention relates generally to a method of power supply noise and signal integrity analysis for creating frequency-dependent electrical models particularly related to microelectronic packages. The method discloses creation of equivalent circuits for geometries encountered in a typical chip package, including how to partition the geometry into cells which are less then 1/20 the minimum wavelength (λ) in size, and how to handle signal and power supply vias, signal wires, and power planes. The method also instructs how to assign values to each of the inductors, capacitors, resistors, and transmission lines in each equivalent circuit. The method further provides modeling of only those interactions which occur between adjacent cells.
摘要翻译：本发明一般涉及一种用于产生与微电子封装特别相关的频率相关的电气模型的电源噪声和信号完整性分析方法。该方法公开了在典型芯片封装中遇到的几何形状的等效电路的创建，包括如何将几何划分成小于小于最小波长（λ）的1/20的单元，以及如何处理信号和电源通孔，信号线和电源平面。该方法还指示如何为每个等效电路中的每个电感器，电容器，电阻器和传输线分配值。该方法还提供仅在相邻小区之间发生的那些相互作用的建模。

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