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1. 发明申请

US20090085155A1 METHOD AND APPARATUS FOR PACKAGE-TO-BOARD IMPEDANCE MATCHING FOR HIGH SPEED INTEGRATED CIRCUITS 审中-公开
标题翻译：用于高速集成电路的封装对板阻抗匹配的方法和装置
公开(公告)号：US20090085155A1
公开(公告)日：2009-04-02
申请号：US11864247
申请日：2007-09-28
申请人： Mark J. Bailey , Todd A. Cannon , Haitian Hu , Nanju Na , Katsuyuki Yonehara , Deborah E. Zwitter
发明人： Mark J. Bailey , Todd A. Cannon , Haitian Hu , Nanju Na , Katsuyuki Yonehara , Deborah E. Zwitter
IPC分类号： H01L29/00 , G06F17/50
CPC分类号： G06F17/5036 , G06F2217/40 , H01L23/645 , H01L23/66 , H01L24/48 , H01L2223/6611 , H01L2224/48091 , H01L2924/00014 , H01L2924/14 , H01L2924/15174 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of package-to-board impedance matching for high speed integrated circuits (ICs). Multiple solder balls are attached to an IC package. The IC package includes multiple conductive interconnect layers, where one of the conductive interconnect layers is coupled to one or more of the multiple solder balls. Multiple vias are coupled between different conductive interconnect layers. An inductive element is coupled between an interconnect lead and a via land in the conductive interconnect layer within the IC package. The physical layout dimensions of the inductive element are configured such that the inductive element provides an inductance value that is sufficient to offset a parasitic capacitance provided by the conductive interconnect layers and the solder balls. The inductive element may be a bond wire, an inductive interconnect, or a spiral interconnect.
摘要翻译：一种用于高速集成电路（IC）的封装对板阻抗匹配的方法。多个焊球连接到IC封装。 IC封装包括多个导电互连层，其中一个导电互连层耦合到多个焊球中的一个或多个。多个通孔耦合在不同的导电互连层之间。电感元件耦合在IC封装内的导电互连层中的互连引线和通孔焊盘之间。电感元件的物理布局尺寸被配置为使得感应元件提供足以抵消由导电互连层和焊球提供的寄生电容的电感值。电感元件可以是接合线，电感互连或螺旋互连。

2. 发明申请

US20140007034A1 ROUTING OF LOCAL CLOCK INTERCONNECTS 失效
标题翻译：当地时钟互连路由
公开(公告)号：US20140007034A1
公开(公告)日：2014-01-02
申请号：US13538593
申请日：2012-06-29
申请人： HAITIAN HU , Chin Ngai Sze
发明人： HAITIAN HU , Chin Ngai Sze
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： In an improved routing of local clock interconnects, an endpoint including a representation of a pin is selected. An original delay is calculated in a route segment that supplies a clock signal to the pin. When the original delay exceeds a delay threshold, a cross-link is added in the route such that the cross-link completes a non-tree sub-network including the segment. The non-tree sub-network is a part of a non-tree network of interconnects carrying the clock signal. A revised delay is calculated in the segment without using delay information corresponding to another non-tree sub-network. The non-tree sub-network is virtually manipulated such that the revised delay can be computed in the manner of computing delay of a tree network. The route is modified using the revised delay in the segment such that a clock skew at the pin is reduced.
摘要翻译：在本地时钟互连的改进路由中，选择包括引脚的表示的端点。在向引脚提供时钟信号的路由段中计算原始延迟。当原始延迟超过延迟阈值时，在路由中添加交叉链路，使得交叉链路完成包括该段的非树状子网络。非树子网络是携带时钟信号的互连非树网络的一部分。在段中计算修改的延迟，而不使用与另一非树子网相对应的延迟信息。虚拟地操作非树子网络，使得可以以树网络的计算延迟的方式计算修改的延迟。使用段中修改的延迟修改路由，使得引脚处的时钟偏移减小。

3. 发明授权

US08788994B2 Routing of local clock interconnects 失效
标题翻译：本地时钟互连的路由
公开(公告)号：US08788994B2
公开(公告)日：2014-07-22
申请号：US13538593
申请日：2012-06-29
申请人： Haitian Hu , Chin Ngai Sze
发明人： Haitian Hu , Chin Ngai Sze
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： In an improved routing of local clock interconnects, an endpoint including a representation of a pin is selected. An original delay is calculated in a route segment that supplies a clock signal to the pin. When the original delay exceeds a delay threshold, a cross-link is added in the route such that the cross-link completes a non-tree sub-network including the segment. The non-tree sub-network is a part of a non-tree network of interconnects carrying the clock signal. A revised delay is calculated in the segment without using delay information corresponding to another non-tree sub-network. The non-tree sub-network is virtually manipulated such that the revised delay can be computed in the manner of computing delay of a tree network. The route is modified using the revised delay in the segment such that a clock skew at the pin is reduced.
摘要翻译：在本地时钟互连的改进路由中，选择包括引脚的表示的端点。在向引脚提供时钟信号的路由段中计算原始延迟。当原始延迟超过延迟阈值时，在路由中添加交叉链路，使得交叉链路完成包括该段的非树状子网络。非树子网络是携带时钟信号的互连非树网络的一部分。在段中计算修改的延迟，而不使用与另一非树子网相对应的延迟信息。虚拟地操作非树子网络，使得可以以树网络的计算延迟的方式计算修改的延迟。使用段中修改的延迟修改路由，使得引脚处的时钟偏移减小。

4. 发明授权

US08312404B2 Multi-segments modeling bond wire interconnects with 2D simulations in high speed, high density wire bond packages 有权
标题翻译：多段建模粘合线与高速，高密度线焊包装中的2D模拟互连
公开(公告)号：US08312404B2
公开(公告)日：2012-11-13
申请号：US12492198
申请日：2009-06-26
申请人： Haitian Hu , Timothy W. Budell , Charles S. Chiu , Eric Tremble
发明人： Haitian Hu , Timothy W. Budell , Charles S. Chiu , Eric Tremble
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , H01L23/552 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/4809 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/484 , H01L2224/49171 , H01L2224/49173 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01055 , H01L2924/01076 , H01L2924/09701 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A method for modeling bond wires in an IC package for predicting noise effects generated by electromagnetic coupling in complex bond wire configurations. A look-up table of equivalent LC circuit models for the bond wires is generated that accurately predicts the effects of the bond wire circuitry of a signal transmission system. Switch and mirror techniques are applied to reduce the bond wire configurations necessary to simulate. The method includes: setting parameters related to the IC package layout of groups of bond wires; sub-dividing each group of bond wires into regions, each including a portion of the bond wire or its corresponding pad, and generating dissection planes for the regions consisting of the bond wires; performing a 3D simulation on the regions consisting of the corresponding pads, and a 2D simulation for each dissection plane; constructing equivalent circuit models for groups of bond wires and corresponding pads based on the 3D and 2D simulations results; inputting the equivalent circuit models into a circuit simulator to measure the noise effects; and modifying the layout geometry to meet noise targets.
摘要翻译：一种用于在IC封装中建模接合线的方法，用于预测复杂接合线配置中由电磁耦合产生的噪声影响。产生用于接合线的等效LC电路模型的查找表，其精确地预测信号传输系统的接合线电路的影响。应用开关和镜像技术来减少模拟所需的接合线配置。该方法包括：设置与电线组IC封装布局有关的参数; 将每组接合线分割成区域，每个区域包括接合线的一部分或其对应的衬垫，并为由接合线组成的区域产生解剖平面; 在由相应的垫组成的区域上进行3D模拟，以及对每个解剖平面进行2D模拟; 基于3D和2D模拟结果构建了用于焊接线组和相应焊盘组的等效电路模型; 将等效电路模型输入到电路模拟器中以测量噪声影响; 并修改布局几何以满足噪声目标。

5. 发明申请

US20100332193A1 Method of Multi-segments Modeling Bond Wire Interconnects with 2D Simulations in High Speed, High Density Wire Bond Packages 有权
标题翻译：多段建模与高速，高密度线框封装中的二维模拟的连接线互连的方法
公开(公告)号：US20100332193A1
公开(公告)日：2010-12-30
申请号：US12492198
申请日：2009-06-26
申请人： Haitian Hu , Timothy W. Budell , Charles S. Chiu , Eric Tremble
发明人： Haitian Hu , Timothy W. Budell , Charles S. Chiu , Eric Tremble
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , H01L23/552 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/4809 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/484 , H01L2224/49171 , H01L2224/49173 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01055 , H01L2924/01076 , H01L2924/09701 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A method for modeling bond wires in an IC package for predicting noise effects generated by electromagnetic coupling in complex bond wire configurations. A look-up table of equivalent LC circuit models for the bond wires is generated that accurately predicts the effects of the bond wire circuitry of a signal transmission system. Switch and mirror techniques are applied to reduce the bond wire configurations necessary to simulate. The method includes: setting parameters related to the IC package layout of groups of bond wires; sub-dividing each group of bond wires into regions, each including a portion of the bond wire or its corresponding pad, and generating dissection planes for the regions consisting of the bond wires; performing a 3D simulation on the regions consisting of the corresponding pads, and a 2D simulation for each dissection plane; constructing equivalent circuit models for groups of bond wires and corresponding pads based on the 3D and 2D simulations results; inputting the equivalent circuit models into a circuit simulator to measure the noise effects; and modifying the layout geometry to meet noise targets.
摘要翻译：一种用于在IC封装中建模接合线的方法，用于预测复杂接合线配置中由电磁耦合产生的噪声影响。产生用于接合线的等效LC电路模型的查找表，其精确地预测信号传输系统的接合线电路的影响。应用开关和镜像技术来减少模拟所需的接合线配置。该方法包括：设置与电线组IC封装布局有关的参数; 将每组接合线分割成区域，每个区域包括接合线的一部分或其对应的衬垫，并为由接合线组成的区域产生解剖平面; 在由相应的垫组成的区域上进行3D模拟，以及对每个解剖平面进行2D模拟; 基于3D和2D模拟结果构建了用于焊接线组和相应焊盘组的等效电路模型; 将等效电路模型输入到电路模拟器中以测量噪声影响; 并修改布局几何以满足噪声目标。

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