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1. 发明授权

US08510697B2 System and method for modeling I/O simultaneous switching noise 失效
标题翻译： I / O同时开关噪声建模的系统和方法
公开(公告)号：US08510697B2
公开(公告)日：2013-08-13
申请号：US13448925
申请日：2012-04-17
申请人： Erik Breiland , Charles S. Chiu , Prince George
发明人： Erik Breiland , Charles S. Chiu , Prince George
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The invention generally relates to systems and methods for modeling I/O simultaneous switching noise, and, more particularly, to systems and methods for modeling I/O simultaneous switching noise in a selected chip window area while accounting for the effect of current sharing among neighbors. A method includes determining a current sharing factor of areas of an integrated circuit (IC) chip package, and determining an offload scaling factor of the IC chip package based upon the current sharing factor and numbers of I/O devices in neighboring areas of the IC chip package.
摘要翻译：本发明一般涉及用于对I / O同时开关噪声进行建模的系统和方法，更具体地说，涉及用于在选择的芯片窗口区域中建模I / O同时开关噪声的系统和方法，同时考虑到邻居之间的电流共享的影响。一种方法包括确定集成电路（IC）芯片封装的区域的电流共享因子，以及基于IC的相邻区域中的I / O设备的当前共享因数和数量来确定IC芯片封装的卸载缩放因子芯片封装。

2. 发明申请

US20120204137A1 SYSTEM AND METHOD FOR MODELING I/O SIMULTANEOUS SWITCHING NOISE 失效
标题翻译：用于建模I / O同时切换噪声的系统和方法
公开(公告)号：US20120204137A1
公开(公告)日：2012-08-09
申请号：US13448925
申请日：2012-04-17
申请人： Erik BREILAND , Charles S. CHIU , Prince GEORGE
发明人： Erik BREILAND , Charles S. CHIU , Prince GEORGE
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The invention generally relates to systems and methods for modeling I/O simultaneous switching noise, and, more particularly, to systems and methods for modeling I/O simultaneous switching noise in a selected chip window area while accounting for the effect of current sharing among neighbors. A method includes determining a current sharing factor of areas of an integrated circuit (IC) chip package, and determining an offload scaling factor of the IC chip package based upon the current sharing factor and numbers of I/O devices in neighboring areas of the IC chip package.
摘要翻译：本发明一般涉及用于对I / O同时开关噪声进行建模的系统和方法，更具体地说，涉及用于在选择的芯片窗口区域中建模I / O同时开关噪声的系统和方法，同时考虑到邻居之间的电流共享的影响。一种方法包括确定集成电路（IC）芯片封装的区域的电流共享因子，以及基于IC的相邻区域中的I / O设备的当前共享因数和数量来确定IC芯片封装的卸载缩放因子芯片封装。

3. 发明授权

US06584596B2 Method of designing a voltage partitioned solder-bump package 有权
标题翻译：设计电压分隔焊料凸点封装的方法
公开(公告)号：US06584596B2
公开(公告)日：2003-06-24
申请号：US09682584
申请日：2001-09-24
申请人： Patrick H. Buffet , Charles S. Chiu , Yu H. Sun
发明人： Patrick H. Buffet , Charles S. Chiu , Yu H. Sun
IPC分类号： G06F1750
CPC分类号： G06F17/5036 , G06F2217/40
摘要： Disclosed is a method of designing voltage partitions in a solder bump package for a chip, comprising: determining the current requirements of a chip voltage island, the chip voltage island including chip power and signal pads, and creating an equivalent circuit model of the chip voltage island; defining a package voltage island, the package voltage island including power and signal package pins, and creating an equivalent circuit model of the package voltage island; analyzing electrical attributes of a combination of the chip voltage island model and the package voltage island model; and modifying the package voltage island until the electrical attributes are acceptable.
摘要翻译：公开了一种设计用于芯片的焊料凸块封装中的电压隔板的方法，包括：确定芯片电压岛的电流要求，芯片电压岛包括芯片功率和信号焊盘，并创建芯片电压的等效电路模型岛; 定义封装电压岛，封装电压岛包括电源和信号封装引脚，并创建封装电压岛的等效电路模型; 分析芯片电压岛模型和封装电压岛模型组合的电气属性; 并修改封装电压岛直到电气属性是可接受的。

4. 发明授权

US08312404B2 Multi-segments modeling bond wire interconnects with 2D simulations in high speed, high density wire bond packages 有权
标题翻译：多段建模粘合线与高速，高密度线焊包装中的2D模拟互连
公开(公告)号：US08312404B2
公开(公告)日：2012-11-13
申请号：US12492198
申请日：2009-06-26
申请人： Haitian Hu , Timothy W. Budell , Charles S. Chiu , Eric Tremble
发明人： Haitian Hu , Timothy W. Budell , Charles S. Chiu , Eric Tremble
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , H01L23/552 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/4809 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/484 , H01L2224/49171 , H01L2224/49173 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01055 , H01L2924/01076 , H01L2924/09701 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A method for modeling bond wires in an IC package for predicting noise effects generated by electromagnetic coupling in complex bond wire configurations. A look-up table of equivalent LC circuit models for the bond wires is generated that accurately predicts the effects of the bond wire circuitry of a signal transmission system. Switch and mirror techniques are applied to reduce the bond wire configurations necessary to simulate. The method includes: setting parameters related to the IC package layout of groups of bond wires; sub-dividing each group of bond wires into regions, each including a portion of the bond wire or its corresponding pad, and generating dissection planes for the regions consisting of the bond wires; performing a 3D simulation on the regions consisting of the corresponding pads, and a 2D simulation for each dissection plane; constructing equivalent circuit models for groups of bond wires and corresponding pads based on the 3D and 2D simulations results; inputting the equivalent circuit models into a circuit simulator to measure the noise effects; and modifying the layout geometry to meet noise targets.
摘要翻译：一种用于在IC封装中建模接合线的方法，用于预测复杂接合线配置中由电磁耦合产生的噪声影响。产生用于接合线的等效LC电路模型的查找表，其精确地预测信号传输系统的接合线电路的影响。应用开关和镜像技术来减少模拟所需的接合线配置。该方法包括：设置与电线组IC封装布局有关的参数; 将每组接合线分割成区域，每个区域包括接合线的一部分或其对应的衬垫，并为由接合线组成的区域产生解剖平面; 在由相应的垫组成的区域上进行3D模拟，以及对每个解剖平面进行2D模拟; 基于3D和2D模拟结果构建了用于焊接线组和相应焊盘组的等效电路模型; 将等效电路模型输入到电路模拟器中以测量噪声影响; 并修改布局几何以满足噪声目标。

5. 发明授权

US08234611B2 System and method for modeling I/O simultaneous switching noise 有权
标题翻译： I / O同时开关噪声建模的系统和方法
公开(公告)号：US08234611B2
公开(公告)日：2012-07-31
申请号：US12166550
申请日：2008-07-02
申请人： Erik Breiland , Charles S. Chiu , Prince George
发明人： Erik Breiland , Charles S. Chiu , Prince George
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The invention generally relates to systems and methods for modeling I/O simultaneous switching noise, and, more particularly, to systems and methods for modeling I/O simultaneous switching noise in a selected chip window area while accounting for the effect of current sharing among neighbors. A method includes determining a current sharing factor of areas of an integrated circuit (IC) chip package, and determining an offload scaling factor of the IC chip package based upon the current sharing factor and numbers of I/O devices in neighboring areas of the IC chip package.
摘要翻译：本发明一般涉及用于对I / O同时开关噪声进行建模的系统和方法，更具体地说，涉及用于在选择的芯片窗口区域中建模I / O同时开关噪声的系统和方法，同时考虑到邻居之间的电流共享的影响。一种方法包括确定集成电路（IC）芯片封装的区域的电流共享因子，以及基于IC的相邻区域中的I / O设备的当前共享因数和数量来确定IC芯片封装的卸载缩放因子芯片封装。

6. 发明授权

US07197446B2 Hierarchical method of power supply noise and signal integrity analysis 失效
标题翻译：电源噪声和信号完整性分析的分层方法
公开(公告)号：US07197446B2
公开(公告)日：2007-03-27
申请号：US10711168
申请日：2004-08-30
申请人： Erik Breiland , Timothy W. Budell , Charles S. Chiu , Paul L. Clouser , Charles K. Erdelyi , Brian P. Welch
发明人： Erik Breiland , Timothy W. Budell , Charles S. Chiu , Paul L. Clouser , Charles K. Erdelyi , Brian P. Welch
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/78
摘要： The invention relates generally to a method of power supply noise and signal integrity analysis for creating frequency-dependent electrical models particularly related to microelectronic packages. The method discloses creation of equivalent circuits for geometries encountered in a typical chip package, including how to partition the geometry into cells which are less then 1/20 the minimum wavelength (λ) in size, and how to handle signal and power supply vias, signal wires, and power planes. The method also instructs how to assign values to each of the inductors, capacitors, resistors, and transmission lines in each equivalent circuit. The method further provides modeling of only those interactions which occur between adjacent cells.
摘要翻译：本发明一般涉及一种用于产生与微电子封装特别相关的频率相关的电气模型的电源噪声和信号完整性分析方法。该方法公开了在典型芯片封装中遇到的几何形状的等效电路的创建，包括如何将几何划分成小于小于最小波长（λ）的1/20的单元，以及如何处理信号和电源通孔，信号线和电源平面。该方法还指示如何为每个等效电路中的每个电感器，电容器，电阻器和传输线分配值。该方法还提供仅在相邻小区之间发生的那些相互作用的建模。

7. 发明授权

US06523150B1 Method of designing a voltage partitioned wirebond package 失效
标题翻译：电压分隔引线封装的设计方法
公开(公告)号：US06523150B1
公开(公告)日：2003-02-18
申请号：US09682621
申请日：2001-09-28
申请人： Patrick H. Buffet , Charles S. Chiu , Yu H. Sun
发明人： Patrick H. Buffet , Charles S. Chiu , Yu H. Sun
IPC分类号： G06F1750
CPC分类号： H01L24/06 , G06F17/5036 , G06F2217/40 , H01L23/50 , H01L23/5286 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/85399 , H01L2924/00014 , H01L2924/01006 , H01L2924/14 , H01L2924/15312 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2224/45099 , H01L2924/00
摘要： Disclosed is a method of designing voltage partitions in a package for a chip, comprising: determining the current requirements of a chip voltage island comprising a voltage island and power and signal chip pads; computing the voltage drop across power buses in the chip voltage island; assigning additional chip pads to the chip voltage island for use as power pads if the voltage drop is not acceptable; defining a package voltage island, the package voltage island including power and signal package pads; analyzing electrical attributes of a combination of the chip voltage island, the package voltage island and conductive interconnects connecting chip voltage island pads to package voltage island pads; and assigning additional chip pads to the chip voltage island and additional package pads to the package voltage island for use as power pads until the electrical attributes are acceptable.
摘要翻译：公开了一种设计用于芯片的封装中的电压分区的方法，包括：确定包括电压岛的芯片电压岛和功率和信号芯片焊盘的电流要求; 计算芯片电压岛中电源总线的电压降; 如果电压降不可接受，则将额外的芯片焊盘分配给芯片电压岛用作电源焊盘; 定义封装电压岛，封装电压岛包括电源和信号封装焊盘; 分析芯片电压岛，封装电压岛和将芯片电压岛焊盘连接到封装电压岛焊盘的导电互连的组合的电气属性; 并将附加的芯片焊盘分配给芯片电压岛和附加的封装焊盘到封装电压岛，以用作电源焊盘，直到电气属性是可接受的。

8. 发明授权

US08438520B2 Early decoupling capacitor optimization method for hierarchical circuit design 失效
标题翻译：用于分层电路设计的早期去耦电容优化方法
公开(公告)号：US08438520B2
公开(公告)日：2013-05-07
申请号：US13219813
申请日：2011-08-29
申请人： Kurt A. Carlsen , Charles S. Chiu , Umberto Garofano , Ze Gui Pang , Eric W. Tremble , David Toub , Ivan L. Wemple
发明人： Kurt A. Carlsen , Charles S. Chiu , Umberto Garofano , Ze Gui Pang , Eric W. Tremble , David Toub , Ivan L. Wemple
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5063 , G06F2217/78 , G06F2217/82
摘要： Methods, systems, computer programs, etc., determine the required number of decoupling capacitors, and approximate locations for the decoupling capacitors, for a region of an integrated circuit. Switching elements of the region are entered into a simulation program running on a computerized device. Also, a power distribution model of the region is entered into the simulation program, and a power-supply voltage compression target is entered into the simulation program. These methods, systems, etc., generate an upper number of decoupling capacitors required to satisfy the compression target when all the switching elements concurrently switch. For each switching element, the methods, systems, etc., generate a specific number of decoupling capacitors required to satisfy the compression when only the element switches, calculate a fraction of the specific number to the upper number, assign the fraction of the total number of decoupling capacitors to each switching circuit element, and place the fraction of the total number of decoupling capacitors in electrical proximity to the element.
摘要翻译：方法，系统，计算机程序等为集成电路的一个区域确定所需数量的去耦电容器和去耦电容器的近似位置。该区域的切换元件被输入到在计算机化设备上运行的仿真程序中。此外，该区域的配电模型被输入到模拟程序中，并且将电源电压压缩目标输入到模拟程序中。当所有开关元件同时切换时，这些方法，系统等产生满足压缩目标所需的去耦电容器的数量。对于每个开关元件，方法，系统等产生特定数量的去耦电容器，以便在仅元件切换时满足压缩，将特定数量的一部分计算为上限，分配总数的分数的去耦电容器到每个开关电路元件，并将去耦电容器总数的一部分放置在电气附近的元件上。

9. 发明申请

US20100005435A1 SYSTEM AND METHOD FOR MODELING I/O SIMULTANEOUS SWITCHING NOISE 有权
标题翻译：用于建模I / O同时切换噪声的系统和方法
公开(公告)号：US20100005435A1
公开(公告)日：2010-01-07
申请号：US12166550
申请日：2008-07-02
申请人： Erik Breiland , Charles S. Chiu , Prince George
发明人： Erik Breiland , Charles S. Chiu , Prince George
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The invention generally relates to systems and methods for modeling I/O simultaneous switching noise, and, more particularly, to systems and methods for modeling I/O simultaneous switching noise in a selected chip window area while accounting for the effect of current sharing among neighbors. A method includes determining a current sharing factor of areas of an integrated circuit (IC) chip package, and determining an offload scaling factor of the IC chip package based upon the current sharing factor and numbers of I/O devices in neighboring areas of the IC chip package.
摘要翻译：本发明一般涉及用于对I / O同时开关噪声进行建模的系统和方法，更具体地说，涉及用于在选择的芯片窗口区域中建模I / O同时开关噪声的系统和方法，同时考虑到邻居之间的电流共享的影响。一种方法包括确定集成电路（IC）芯片封装的区域的电流共享因子，以及基于IC的相邻区域中的I / O设备的当前共享因数和数量来确定IC芯片封装的卸载缩放因子芯片封装。

10. 发明授权

US07110930B2 Integrated circuit and package modeling 失效
标题翻译：集成电路和封装建模
公开(公告)号：US07110930B2
公开(公告)日：2006-09-19
申请号：US10065753
申请日：2002-11-15
申请人： Charles S. Chiu , Umberto Garofano , James E. Jasmin
发明人： Charles S. Chiu , Umberto Garofano , James E. Jasmin
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method, system and program product for creating a simplified equivalent model for an IC that can be used for detailed analysis. The equivalent model takes into consideration the effects of all the I/O placement regardless of the non-uniformity of I/O placement. The equivalent model is generated, in part, by partitioning the IC into simulation windows and converting I/Os within each simulation window to a current source having the same current change rate, and then running a simulation on this intermediate model. A current change rate observed for a simulation window is then used to convert back to actual I/Os to create the equivalent model. The equivalent model can be simulated using conventional software, e.g., SPICE, for more detailed analysis such as signal integrity, timing of I/Os and noise.
摘要翻译：一种用于创建可用于详细分析的IC的简化等效模型的方法，系统和程序产品。等效模型考虑到所有I / O布局的影响，而不考虑I / O布局的不均匀性。产生等效模型，部分是通过将IC划分为模拟窗口，并将每个仿真窗口内的I / O转换为具有相同电流变化率的电流源，然后在该中间模型上运行仿真。然后使用仿真窗口观察到的当前变化率转换回实际I / O以创建等效模型。可以使用常规软件（例如SPICE）来模拟等效模型，以进行更详细的分析，例如信号完整性，I / O和噪声的定时。

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