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1. 发明授权

US07882469B2 Automatic verification of adequate conductive return-current paths 有权
标题翻译：自动验证足够的导通回路路径
公开(公告)号：US07882469B2
公开(公告)日：2011-02-01
申请号：US11945754
申请日：2007-11-27
申请人： Timothy W. Budell , David C. Reynolds , Eric W. Tremble
发明人： Timothy W. Budell , David C. Reynolds , Eric W. Tremble
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5081
摘要： After finding the shortest conductive signal return-current path for each signal, the invention assesses whether each conductive return-current path is adequate. The method analyzes each shortest conductive signal return-current path and determines if a significant portion of the signal return current flows as displacement current rather than following the conductive current path. A significant displacement current flows when the length of the conductive return-current path that diverges from a signal net is more than a previously defined limit based on the signal transition time. Further, a significant displacement current flows when the overall length of the signal differs from the overall length of the conductive return-current path by more than a previously defined limit based on the signal transition time.
摘要翻译：在找到每个信号的最短导通信号返回电流路径之后，本发明评估每个导通回路路径是否足够。该方法分析每个最短导通信号返回电流路径，并确定信号返回电流的有效部分是否以位移电流流动，而不是跟随导电电流路径。当从信号网发散的导电返回电流路径的长度大于基于信号转换时间的先前定义的极限时，显着的位移电流流动。此外，当信号的总长度与导电返回电流路径的总长度不同于基于信号转换时间的预先限定的极限时，显着的位移电流流动。

2. 发明申请

US20090094564A1 METHOD FOR RAPID RETURN PATH TRACING 审中-公开
标题翻译：快速返回路径追踪方法
公开(公告)号：US20090094564A1
公开(公告)日：2009-04-09
申请号：US11866591
申请日：2007-10-03
申请人： Timothy W. Budell , Charles S. Chiu , David C. Reynolds , Eric W. Tremble
发明人： Timothy W. Budell , Charles S. Chiu , David C. Reynolds , Eric W. Tremble
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method for quickly tracing minimum-length conductive return paths through an electronic structure utilizes a raster based (cellular) memory model comprising individual grids for each layer of the structure. Each grid comprises a reduced resolution N×M cell representation of the conductive structures on that layer. Cellular methodologies are then used to determine, for each signal net, the shortest return path. This information can then be used for various purposes, including determining if the return path is sufficient to ensure adequate signal integrity.
摘要翻译：用于快速跟踪通过电子结构的最小长度导电返回路径的方法利用基于光栅的（蜂窝）存储器模型，其包括用于结构的每个层的各个格栅。每个网格包括该层上的导电结构的降低分辨率的N×M单元表示。然后使用蜂窝方法来确定每个信号网络的最短返回路径。然后，该信息可用于各种目的，包括确定返回路径是否足以确保足够的信号完整性。

3. 发明申请

US20090138836A1 AUTOMATIC VERIFICATION OF ADEQUATE CONDUCTIVE RETURN-CURRENT PATHS 有权
标题翻译：自动验证适当的导通回路电流
公开(公告)号：US20090138836A1
公开(公告)日：2009-05-28
申请号：US11945754
申请日：2007-11-27
申请人： Timothy W. Budell , David C. Reynolds , Eric W. Tremble
发明人： Timothy W. Budell , David C. Reynolds , Eric W. Tremble
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： After finding the shortest conductive signal return-current path for each signal, the invention assesses whether each conductive return-current path is adequate. The method analyzes each shortest conductive signal return-current path and determines if a significant portion of the signal return current flows as displacement current rather than following the conductive current path. A significant displacement current flows when the length of the conductive return-current path that diverges from a signal net is more than a previously defined limit based on the signal transition time. Further, a significant displacement current flows when the overall length of the signal differs from the overall length of the conductive return-current path by more than a previously defined limit based on the signal transition time.
摘要翻译：在找到每个信号的最短导通信号返回电流路径之后，本发明评估每个导通回路路径是否足够。该方法分析每个最短导通信号返回电流路径，并确定信号返回电流的有效部分是否以位移电流流动，而不是跟随导电电流路径。当从信号网发散的导电返回电流路径的长度大于基于信号转换时间的先前定义的极限时，显着的位移电流流动。此外，当信号的总长度与导电返回电流路径的总长度不同于基于信号转换时间的预先限定的极限时，显着的位移电流流动。

4. 发明授权

US08429590B2 System-level method for reducing power supply noise in an electronic system 失效
标题翻译：用于减少电子系统中电源噪声的系统级方法
公开(公告)号：US08429590B2
公开(公告)日：2013-04-23
申请号：US13184909
申请日：2011-07-18
申请人： Timothy W. Budell , Eric W. Tremble
发明人： Timothy W. Budell , Eric W. Tremble
IPC分类号： G06F17/50 , G06F9/455 , G06F11/22 , G06G7/62 , G06G7/54
CPC分类号： G06F17/5036 , G06F2217/82
摘要： In one embodiment, a method for reducing power supply noise within an electronic system that includes an integrated circuit (IC), a package, and a printed circuit board (PCB) connected by a plurality of power delivery networks (PDN) is disclosed. Power supply noise within the system is reduced by defining a voltage compression limit for each PDN of the electronic system; determining a voltage compression for each PDN of the electronic system during a plurality of switching events; comparing the voltage compression of each PDN of the electronic system to the voltage compression limit for each switching event; and in response to the voltage compression of each PDN of the electronic system exceeding the limit, modifying the electronic system to reduce the voltage compression below the limit.
摘要翻译：在一个实施例中，公开了一种用于减少电子系统内的电源噪声的方法，所述电子系统包括由多个功率传递网络（PDN）连接的集成电路（IC），封装和印刷电路板（PCB）。通过为电子系统的每个PDN定义电压压缩限制来减小系统内的电源噪声; 在多个切换事件期间确定电子系统的每个PDN的电压压缩; 将电子系统的每个PDN的电压压缩与每个切换事件的电压压缩极限进行比较; 并且响应于电子系统的每个PDN的电压压缩超过限制，修改电子系统以将电压压缩降低到极限以下。

5. 发明申请

US20130024831A1 SYSTEM-LEVEL METHOD FOR REDUCING POWER SUPPLY NOISE IN AN ELECTRONIC SYSTEM 失效
标题翻译：用于减少电子系统中电源噪声的系统级方法
公开(公告)号：US20130024831A1
公开(公告)日：2013-01-24
申请号：US13184909
申请日：2011-07-18
申请人： Timothy W. Budell , Eric W. Tremble
发明人： Timothy W. Budell , Eric W. Tremble
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： In one embodiment, a method for reducing power supply noise within an electronic system that includes an integrated circuit (IC), a package, and a printed circuit board (PCB) connected by a plurality of power delivery networks (PDN) is disclosed. Power supply noise within the system is reduced by defining a voltage compression limit for each PDN of the electronic system; determining a voltage compression for each PDN of the electronic system during a plurality of switching events; comparing the voltage compression of each PDN of the electronic system to the voltage compression limit for each switching event; and in response to the voltage compression of each PDN of the electronic system exceeding the limit, modifying the electronic system to reduce the voltage compression below the limit.
摘要翻译：在一个实施例中，公开了一种用于减少电子系统内的电源噪声的方法，所述电子系统包括由多个功率传递网络（PDN）连接的集成电路（IC），封装和印刷电路板（PCB）。通过为电子系统的每个PDN定义电压压缩限制来减小系统内的电源噪声; 在多个切换事件期间确定电子系统的每个PDN的电压压缩; 将电子系统的每个PDN的电压压缩与每个切换事件的电压压缩极限进行比较; 并且响应于电子系统的每个PDN的电压压缩超过限制，修改电子系统以将电压压缩降低到极限以下。

6. 发明授权

US06945791B2 Integrated circuit redistribution package 失效
标题翻译：集成电路再分配封装
公开(公告)号：US06945791B2
公开(公告)日：2005-09-20
申请号：US10776737
申请日：2004-02-10
申请人： Timothy W. Budell , Eric W. Tremble , Brian P. Welch
发明人： Timothy W. Budell , Eric W. Tremble , Brian P. Welch
IPC分类号： H01L23/498 , H01L23/50 , H01R12/00
CPC分类号： H01L23/49838 , H01L23/49822 , H01L23/49827 , H01L23/50 , H01L2224/16 , H01L2924/15159 , H01L2924/15174 , H01L2924/15311 , H01L2924/3011
摘要： The present invention provides a redistribution package having an upper surface that includes contacts with reduced pitch that correspond, for example, to that of a Controlled Collapse Chip Connection (“C4”) structure formed on a chip, and a lower surface having contacts with increased pitch that correspond, for example, to a printed circuit board employing ball grid array (“BGA”) pads. A series of power, signal and ground conductors extend through the body of the redistribution package and interconnect the circuit board contacts to the chip contacts.
摘要翻译：本发明提供一种再分配封装，其具有上表面，该上表面包括减小的间距的触点，例如与形成在芯片上的受控塌陷芯片连接（“C4”）结构对应，并且具有增加的触点的下表面间距，例如对应于使用球栅阵列（“BGA”）焊盘的印刷电路板。一系列电源，信号和接地导体延伸穿过再分配封装的主体，并将电路板触点与芯片触点相互连接。

7. 发明申请

US20130054202A1 EARLY DECOUPLING CAPACITOR OPTIMIZATION METHOD FOR HIERARCHICAL CIRCUIT DESIGN 失效
标题翻译：用于分层电路设计的早期解耦电容优化方法
公开(公告)号：US20130054202A1
公开(公告)日：2013-02-28
申请号：US13219813
申请日：2011-08-29
申请人： Kurt A. Carlsen , Charles S. Chiu , Umberto Garofano , Ze Gui Pang , Eric W. Tremble , David Toub , Ivan L. Wemple
发明人： Kurt A. Carlsen , Charles S. Chiu , Umberto Garofano , Ze Gui Pang , Eric W. Tremble , David Toub , Ivan L. Wemple
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5063 , G06F2217/78 , G06F2217/82
摘要： Methods, systems, computer programs, etc., determine the required number of decoupling capacitors, and approximate locations for the decoupling capacitors, for a region of an integrated circuit. Switching elements of the region are entered into a simulation program running on a computerized device. Also, a power distribution model of the region is entered into the simulation program, and a power-supply voltage compression target is entered into the simulation program. These methods, systems, etc., generate an upper number of decoupling capacitors required to satisfy the compression target when all the switching elements concurrently switch. For each switching element, the methods, systems, etc., generate a specific number of decoupling capacitors required to satisfy the compression when only the element switches, calculate a fraction of the specific number to the upper number, assign the fraction of the total number of decoupling capacitors to each switching circuit element, and place the fraction of the total number of decoupling capacitors in electrical proximity to the element.
摘要翻译：方法，系统，计算机程序等为集成电路的一个区域确定所需数量的去耦电容器和去耦电容器的近似位置。该区域的切换元件被输入到在计算机化设备上运行的仿真程序中。此外，该区域的配电模型被输入到模拟程序中，并且将电源电压压缩目标输入到模拟程序中。当所有开关元件同时切换时，这些方法，系统等产生满足压缩目标所需的去耦电容器的数量。对于每个开关元件，方法，系统等产生特定数量的去耦电容器，以便在仅元件切换时满足压缩，将特定数量的一部分计算为上限，分配总数的分数的去耦电容器到每个开关电路元件，并将去耦电容器总数的一部分放置在电气附近的元件上。

8. 发明授权

US08438520B2 Early decoupling capacitor optimization method for hierarchical circuit design 失效
标题翻译：用于分层电路设计的早期去耦电容优化方法
公开(公告)号：US08438520B2
公开(公告)日：2013-05-07
申请号：US13219813
申请日：2011-08-29
申请人： Kurt A. Carlsen , Charles S. Chiu , Umberto Garofano , Ze Gui Pang , Eric W. Tremble , David Toub , Ivan L. Wemple
发明人： Kurt A. Carlsen , Charles S. Chiu , Umberto Garofano , Ze Gui Pang , Eric W. Tremble , David Toub , Ivan L. Wemple
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5063 , G06F2217/78 , G06F2217/82
摘要： Methods, systems, computer programs, etc., determine the required number of decoupling capacitors, and approximate locations for the decoupling capacitors, for a region of an integrated circuit. Switching elements of the region are entered into a simulation program running on a computerized device. Also, a power distribution model of the region is entered into the simulation program, and a power-supply voltage compression target is entered into the simulation program. These methods, systems, etc., generate an upper number of decoupling capacitors required to satisfy the compression target when all the switching elements concurrently switch. For each switching element, the methods, systems, etc., generate a specific number of decoupling capacitors required to satisfy the compression when only the element switches, calculate a fraction of the specific number to the upper number, assign the fraction of the total number of decoupling capacitors to each switching circuit element, and place the fraction of the total number of decoupling capacitors in electrical proximity to the element.
摘要翻译：方法，系统，计算机程序等为集成电路的一个区域确定所需数量的去耦电容器和去耦电容器的近似位置。该区域的切换元件被输入到在计算机化设备上运行的仿真程序中。此外，该区域的配电模型被输入到模拟程序中，并且将电源电压压缩目标输入到模拟程序中。当所有开关元件同时切换时，这些方法，系统等产生满足压缩目标所需的去耦电容器的数量。对于每个开关元件，方法，系统等产生特定数量的去耦电容器，以便在仅元件切换时满足压缩，将特定数量的一部分计算为上限，分配总数的分数的去耦电容器到每个开关电路元件，并将去耦电容器总数的一部分放置在电气附近的元件上。

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