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1. 发明申请

US20080090412A1 Pre-silicide spacer removal 失效
标题翻译：预硅化物间隔物去除
公开(公告)号：US20080090412A1
公开(公告)日：2008-04-17
申请号：US11548842
申请日：2006-10-12
申请人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Jun Jung Kim , Yaocheng Liu , Huilong Zhu
发明人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Jun Jung Kim , Yaocheng Liu , Huilong Zhu
IPC分类号： H01L21/44
CPC分类号： H01L29/665 , H01L21/32 , H01L29/6653 , H01L29/66545 , H01L29/6659
摘要： A method forms a gate conductor over a substrate, and simultaneously forms spacers on sides of the gate conductor and a gate cap on the top of the gate conductor. Isolation regions are formed in the substrate and the method implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers to form source and drain regions. The method deposits a mask over the gate conductor, the spacers, and the source and drain regions. The mask is recessed to a level below a top of the gate conductor but above the source and drain regions, such that the spacers are exposed and the source and drain regions are protected by the mask. With the mask in place, the method then safely removes the spacers and the gate cap, without damaging the source/drain regions or the isolation regions (which are protected by the mask). Next, the method removes the mask and then forms silicide regions on the gate conductor and the source and drain regions.
摘要翻译：一种方法在衬底上形成栅极导体，同时在栅极导体的侧面和栅极导体的顶部上形成栅极盖。在衬底中形成隔离区域，并且该方法将杂质注入未被栅极导体和间隔物保护的衬底的暴露区域中以形成源区和漏区。该方法在栅极导体，间隔物以及源极和漏极区域上沉积掩模。掩模凹陷到栅极导体的顶部下方但在源极和漏极区域之上的水平面，使得间隔物被暴露，并且源极和漏极区域被掩模保护。在掩模就位的情况下，该方法然后安全地去除间隔物和栅极盖，而不损坏源极/漏极区域或隔离区域（被掩模保护）。接下来，该方法移除掩模，然后在栅极导体和源极和漏极区域上形成硅化物区域。

2. 发明授权

US07504309B2 Pre-silicide spacer removal 失效
标题翻译：预硅化物间隔物去除
公开(公告)号：US07504309B2
公开(公告)日：2009-03-17
申请号：US11548842
申请日：2006-10-12
申请人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Jun Jung Kim , Yaocheng Liu , Huilong Zhu
发明人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Jun Jung Kim , Yaocheng Liu , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L29/665 , H01L21/32 , H01L29/6653 , H01L29/66545 , H01L29/6659
摘要： A method forms a gate conductor over a substrate, and simultaneously forms spacers on sides of the gate conductor and a gate cap on the top of the gate conductor. Isolation regions are formed in the substrate and the method implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers to form source and drain regions. The method deposits a mask over the gate conductor, the spacers, and the source and drain regions. The mask is recessed to a level below a top of the gate conductor but above the source and drain regions, such that the spacers are exposed and the source and drain regions are protected by the mask. With the mask in place, the method then safely removes the spacers and the gate cap, without damaging the source/drain regions or the isolation regions (which are protected by the mask). Next, the method removes the mask and then forms silicide regions on the gate conductor and the source and drain regions.
摘要翻译：一种方法在衬底上形成栅极导体，同时在栅极导体的侧面和栅极导体的顶部上形成栅极盖。在衬底中形成隔离区域，并且该方法将杂质注入未被栅极导体和间隔物保护的衬底的暴露区域中以形成源区和漏区。该方法在栅极导体，间隔物以及源极和漏极区域上沉积掩模。掩模凹陷到栅极导体的顶部下方但在源极和漏极区域之上的水平面，使得间隔物被暴露，并且源极和漏极区域被掩模保护。在掩模就位的情况下，该方法然后安全地去除间隔物和栅极盖，而不损坏源极/漏极区域或隔离区域（被掩模保护）。接下来，该方法移除掩模，然后在栅极导体和源极和漏极区域上形成硅化物区域。

3. 发明申请

US20080185645A1 SEMICONDUCTOR STRUCTURE INCLUDING STEPPED SOURCE/DRAIN REGION 审中-公开
标题翻译：半导体结构，包括步进源/排水区
公开(公告)号：US20080185645A1
公开(公告)日：2008-08-07
申请号：US11670100
申请日：2007-02-01
申请人： Zhijiong Luo , Huilong Zhu , Sunfei Fang , Thomas W. Dyer
发明人： Zhijiong Luo , Huilong Zhu , Sunfei Fang , Thomas W. Dyer
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/28518 , H01L23/485 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/7834 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a stepped source and drain region located in part within a semiconductor substrate that preferably has a step in a direction of a gate electrode located over a channel region that adjoins the stepped source and drain region within the semiconductor substrate. A stepped portion of the stepped source and drain region covers an extension region within the stepped source and drain region.
摘要翻译：半导体结构包括部分地位于半导体衬底内的阶梯式源极和漏极区域，其优选地具有位于与半导体衬底内的阶梯式源极和漏极区域相邻的沟道区域上的栅极电极的方向上的台阶。阶梯式源极和漏极区域的阶梯部分覆盖阶梯式源极和漏极区域内的延伸区域。

4. 发明授权

US07923365B2 Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon 有权
标题翻译：在其上形成具有应力诱导侧壁绝缘间隔物的场效应晶体管的方法
公开(公告)号：US07923365B2
公开(公告)日：2011-04-12
申请号：US11874118
申请日：2007-10-17
申请人： Jun-jung Kim , Sang-jine Park , Min-ho Lee , Thomas W. Dyer , Sunfei Fang , O-sung Kwon , Johnny Widodo
发明人： Jun-jung Kim , Sang-jine Park , Min-ho Lee , Thomas W. Dyer , Sunfei Fang , O-sung Kwon , Johnny Widodo
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/7833 , H01L29/665 , H01L29/6653 , H01L29/7843
摘要： Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode.
摘要翻译：形成集成电路器件的方法包括形成具有栅电极的场效应晶体管，栅电极的侧壁上的牺牲隔离物和硅化源/漏区。当形成源极/漏极区域的高掺杂部分时，牺牲间隔物用作注入掩模。然后从栅电极的侧壁去除牺牲隔离物。然后，在栅电极的侧壁上形成应力诱导电绝缘层，其被配置为在场效应晶体管的沟道区域中引起净拉伸应力（用于NMOS晶体管）或压应力（用于PMOS晶体管）。

5. 发明申请

US20090101979A1 Methods of Forming Field Effect Transistors Having Stress-Inducing Sidewall Insulating Spacers Thereon and Devices Formed Thereby 有权
标题翻译：形成具有应力诱导侧壁绝缘垫片的场效应晶体管的方法和由此形成的器件
公开(公告)号：US20090101979A1
公开(公告)日：2009-04-23
申请号：US11874118
申请日：2007-10-17
申请人： Jun-jung Kim , Sang-jine Park , Min-ho Lee , Thomas W. Dyer , Sunfei Fang , O-sung Kwon , Johnny Widodo
发明人： Jun-jung Kim , Sang-jine Park , Min-ho Lee , Thomas W. Dyer , Sunfei Fang , O-sung Kwon , Johnny Widodo
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7833 , H01L29/665 , H01L29/6653 , H01L29/7843
摘要： Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode.
摘要翻译：形成集成电路器件的方法包括形成具有栅电极的场效应晶体管，栅电极的侧壁上的牺牲隔离物和硅化源/漏区。当形成源极/漏极区域的高掺杂部分时，牺牲间隔物用作注入掩模。然后从栅电极的侧壁去除牺牲隔离物。然后，在栅电极的侧壁上形成应力诱导电绝缘层，其被配置为在场效应晶体管的沟道区域中引起净拉伸应力（用于NMOS晶体管）或压应力（用于PMOS晶体管）。

6. 发明申请

US20110156110A1 Field Effect Transistors Having Gate Electrode Silicide Layers with Reduced Surface Damage 审中-公开
标题翻译：具有栅电极的场效应晶体管具有降低的表面损伤的硅化物层
公开(公告)号：US20110156110A1
公开(公告)日：2011-06-30
申请号：US13043059
申请日：2011-03-08
申请人： Jun-jung Kim , Sang-jine Park , Min-ho Lee , Thomas W. Dyer , Sunfei Fang , O-sung Kwon , Johnny Widodo
发明人： Jun-jung Kim , Sang-jine Park , Min-ho Lee , Thomas W. Dyer , Sunfei Fang , O-sung Kwon , Johnny Widodo
IPC分类号： H01L29/772
CPC分类号： H01L29/7833 , H01L29/665 , H01L29/6653 , H01L29/7843
摘要： Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode.
摘要翻译：形成集成电路器件的方法包括形成具有栅电极的场效应晶体管，栅电极的侧壁上的牺牲隔离物和硅化源/漏区。当形成源极/漏极区域的高掺杂部分时，牺牲间隔物用作注入掩模。然后从栅电极的侧壁去除牺牲隔离物。然后，在栅电极的侧壁上形成应力诱导电绝缘层，其被配置为在场效应晶体管的沟道区域中引起净拉伸应力（用于NMOS晶体管）或压应力（用于PMOS晶体管）。

7. 发明授权

US07863693B2 Forming conductive stud for semiconductive devices 有权
标题翻译：形成用于半导体器件的导电螺柱
公开(公告)号：US07863693B2
公开(公告)日：2011-01-04
申请号：US12013622
申请日：2008-01-14
申请人： Thomas W. Dyer , Sunfei Fang , Jiang Yan
发明人： Thomas W. Dyer , Sunfei Fang , Jiang Yan
IPC分类号： H01L21/02
CPC分类号： H01L21/823871 , H01L21/76895 , H01L21/76897 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/7843
摘要： Embodiments of the present invention provide a method of forming a conductive stud contacting a semiconductor device. The method includes forming a protective layer covering the semiconductor device; selectively etching an opening down through the protective layer reaching a contact area of the semiconductor device, the opening being away from a protected area of the semiconductor device; and filling the opening with a conductive material to form the conductive stud. One embodiment may further include forming a dielectric liner directly on top of the semiconductor device, and forming the protective layer on top of the dielectric liner. Embodiments of the present invention also provide a semiconductor device made thereof.
摘要翻译：本发明的实施例提供一种形成与半导体器件接触的导电柱的方法。该方法包括形成覆盖半导体器件的保护层; 选择性地将开口向下蚀刻通过保护层到达半导体器件的接触区域，该开口远离半导体器件的保护区域; 并用导电材料填充开口以形成导电柱。一个实施例还可以包括直接在半导体器件的顶部上形成电介质衬垫，以及在电介质衬垫的顶部上形成保护层。本发明的实施例还提供由其制成的半导体器件。

8. 发明授权

US07393746B2 Post-silicide spacer removal 失效
标题翻译：后硅化物间隔物去除
公开(公告)号：US07393746B2
公开(公告)日：2008-07-01
申请号：US11548870
申请日：2006-10-12
申请人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Siddhartha Panda , Yong Meng Lee , JunJung Kim
发明人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Siddhartha Panda , Yong Meng Lee , JunJung Kim
IPC分类号： H01L21/33
CPC分类号： H01L21/32 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A method forms a gate conductor over a substrate, forms spacers (e.g., nitride spacers) on sides of the gate conductor, and implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers. Then the method forms a silicide on surfaces of the exposed regions of the substrate. The method forms a conformal protective layer (e.g., an oxide or other similar material) over the silicide, the spacers, and the gate conductor. Next, the method forms a non-conformal sacrificial layer (e.g., nitride or other material that can be selectively removed with respect to the protective layer) over the protective layer. A subsequent partial etching process partially etches the sacrificial layer such that relatively thinner regions of the sacrificial layer that are over the spacers are completely removed and the relatively thicker regions of the sacrificial layer that are over the substrate are not removed. The next step in the method removes only those portions of the protective layer that cover the spacers, without removing the portions of the protective layer that cover the silicide. As the spacers are now exposed and the silicide is protected by the protective and sacrificial layers, the method can safely remove the spacers without affecting the silicide.
摘要翻译：一种方法在衬底上形成栅极导体，在栅极导体的侧面上形成间隔物（例如，氮化物间隔物），并将杂质注入到未被栅极导体和间隔物保护的衬底的暴露区域中。然后，该方法在衬底的暴露区域的表面上形成硅化物。该方法在硅化物，间隔物和栅极导体之上形成共形保护层（例如，氧化物或其它类似材料）。接下来，该方法在保护层上形成非共形牺牲层（例如，可相对于保护层选择性去除的氮化物或其它材料）。随后的部分蚀刻工艺部分地蚀刻牺牲层，使得在间隔物之上的牺牲层的相对较薄的区域被完全去除，并且除去衬底之上的牺牲层的相对较厚的区域。该方法中的下一步骤仅去除覆盖间隔物的保护层的那些部分，而不去除覆盖硅化物的保护层的部分。由于间隔物现在被暴露并且硅化物被保护层和牺牲层保护，所以该方法可以安全地去除间隔物而不影响硅化物。

9. 发明申请

US20080054413A1 SELF-ALIGNED DUAL SEGMENT LINER AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：自对准双分段线束及其制造方法
公开(公告)号：US20080054413A1
公开(公告)日：2008-03-06
申请号：US11468536
申请日：2006-08-30
申请人： Thomas W. Dyer , Sunfei Fang , Jiang Yan
发明人： Thomas W. Dyer , Sunfei Fang , Jiang Yan
IPC分类号： H01L23/58 , H01L21/469
CPC分类号： H01L21/76829 , H01L21/823807 , H01L29/7843
摘要： A method of forming a dual segment liner covering a first and a second set of semiconductor devices is provided. The method includes forming a first liner and a first protective layer on top thereof, the first liner covering the first set of semiconductor devices; forming a second liner, the second liner having a first section covering the first protective layer, a transitional section, and a second section covering the second set of semiconductor devices, the second section being self-aligned to the first liner via the transitional section; forming a second protective layer on top of the second section of the second liner; removing the first section and at least part of the transitional section of the second liner; and obtaining the dual segment liner including the first liner, the transitional section and the second section of the second liner. A semiconductor structure with a self-aligned dual segment liner formed in accordance with one embodiment of the invention is also provided.
摘要翻译：提供一种形成覆盖第一组和第二组半导体器件的双段衬套的方法。该方法包括在其顶部形成第一衬垫和第一保护层，第一衬套覆盖第一组半导体器件; 形成第二衬垫，所述第二衬套具有覆盖所述第一保护层的第一部分，过渡部分和覆盖所述第二组半导体器件的第二部分，所述第二部分经由所述过渡部分自对准到所述第一衬里; 在所述第二衬垫的所述第二部分的顶部上形成第二保护层; 移除所述第二衬套的所述第一部分和所述过渡部分的至少一部分; 并且获得包括第一衬套，第二衬套的过渡部分和第二部分的双段衬管。还提供了根据本发明的一个实施例形成的具有自对准双段衬垫的半导体结构。

10. 发明申请

US20080090370A1 Post-silicide spacer removal 失效
公开(公告)号：US20080090370A1
公开(公告)日：2008-04-17
申请号：US11548870
申请日：2006-10-12
申请人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Siddhartha Panda , Yong Meng Lee
发明人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Siddhartha Panda , Yong Meng Lee
IPC分类号： H01L21/331
CPC分类号： H01L21/32 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A method forms a gate conductor over a substrate, forms spacers (e.g., nitride spacers) on sides of the gate conductor, and implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers. Then the method forms a silicide on surfaces of the exposed regions of the substrate. The method forms a conformal protective layer (e.g., an oxide or other similar material) over the silicide, the spacers, and the gate conductor. Next, the method forms a non-conformal sacrificial layer (e.g., nitride or other material that can be selectively removed with respect to the protective layer) over the protective layer. A subsequent partial etching process partially etches the sacrificial layer such that relatively thinner regions of the sacrificial layer that are over the spacers are completely removed and the relatively thicker regions of the sacrificial layer that are over the substrate are not removed. The next step in the method removes only those portions of the protective layer that cover the spacers, without removing the portions of the protective layer that cover the silicide. As the spacers are now exposed and the silicide is protected by the protective and sacrificial layers, the method can safely remove the spacers without affecting the silicide.

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