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1. 发明申请

US20080185645A1 SEMICONDUCTOR STRUCTURE INCLUDING STEPPED SOURCE/DRAIN REGION 审中-公开
标题翻译：半导体结构，包括步进源/排水区
公开(公告)号：US20080185645A1
公开(公告)日：2008-08-07
申请号：US11670100
申请日：2007-02-01
申请人： Zhijiong Luo , Huilong Zhu , Sunfei Fang , Thomas W. Dyer
发明人： Zhijiong Luo , Huilong Zhu , Sunfei Fang , Thomas W. Dyer
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/28518 , H01L23/485 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/7834 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a stepped source and drain region located in part within a semiconductor substrate that preferably has a step in a direction of a gate electrode located over a channel region that adjoins the stepped source and drain region within the semiconductor substrate. A stepped portion of the stepped source and drain region covers an extension region within the stepped source and drain region.
摘要翻译：半导体结构包括部分地位于半导体衬底内的阶梯式源极和漏极区域，其优选地具有位于与半导体衬底内的阶梯式源极和漏极区域相邻的沟道区域上的栅极电极的方向上的台阶。阶梯式源极和漏极区域的阶梯部分覆盖阶梯式源极和漏极区域内的延伸区域。

2. 发明授权

US07220662B2 Fully silicided field effect transistors 有权
标题翻译：全硅化场效应晶体管
公开(公告)号：US07220662B2
公开(公告)日：2007-05-22
申请号：US10905549
申请日：2005-01-10
申请人： Huilong Zhu , Sunfei Fang , Zhijiong Luo
发明人： Huilong Zhu , Sunfei Fang , Zhijiong Luo
IPC分类号： H01L21/3205
CPC分类号： H01L21/28097 , H01L21/28518 , H01L29/665 , H01L29/66545
摘要： Fully silicided planar field effect transistors are formed by avoiding the conventional chemical-mechanical polishing step to expose the silicon gate by etching the sidewalls down to the silicon; depositing a sacrificial oxide layer thinner on the top of gate and sidewall of spacers, but thicker over the S/D areas, etching the oxide to expose the top of stacked gate while protecting the S/D; recessing the silicon; stripping the oxide; depositing metal and annealing to form silicide over the gate and S/D.
摘要翻译：通过避免常规的化学机械抛光步骤通过将侧壁蚀刻到硅来暴露硅栅来形成全硅化平面场效应晶体管; 在间隔物的栅极和侧壁的顶部上沉积牺牲氧化物层，但在S / D区域上较厚，在保护S / D的同时蚀刻氧化物以露出堆叠栅极的顶部; 凹陷硅; 剥离氧化物; 沉积金属和退火以在栅极和S / D上形成硅化物。

3. 发明申请

US20060154461A1 FULLY SILICIDED FIELD EFFECT TRANSISTORS 有权
标题翻译：全硅氧化物场效应晶体管
公开(公告)号：US20060154461A1
公开(公告)日：2006-07-13
申请号：US10905549
申请日：2005-01-10
申请人： Huilong Zhu , Sunfei Fang , Zhijiong Luo
发明人： Huilong Zhu , Sunfei Fang , Zhijiong Luo
IPC分类号： H01L21/4763 , H01L21/3205
CPC分类号： H01L21/28097 , H01L21/28518 , H01L29/665 , H01L29/66545
摘要： Fully silicided planar field effect transistors are formed by avoiding the conventional chemical-mechanical polishing step to expose the silicon gate by etching the sidewalls down to the silicon; depositing a sacrificial oxide layer thinner on the top of gate and sidewall of spacers, but thicker over the S/D areas, etching the oxide to expose the top of stacked gate while protecting the S/D; recessing the silicon; stripping the oxide; depositing metal and annealing to form silicide over the gate and S/D.
摘要翻译：通过避免常规的化学机械抛光步骤通过将侧壁蚀刻到硅来暴露硅栅来形成全硅化平面场效应晶体管; 在间隔物的栅极和侧壁的顶部上沉积牺牲氧化物层，但在S / D区域上较厚，在保护S / D的同时蚀刻氧化物以露出堆叠栅极的顶部; 凹陷硅; 剥离氧化物; 沉积金属和退火以在栅极和S / D上形成硅化物。

4. 发明授权

US08039331B2 Opto-thermal annealing methods for forming metal gate and fully silicided gate-field effect transistors 有权
标题翻译：用于形成金属栅极和全硅化栅场效应晶体管的光热退火方法
公开(公告)号：US08039331B2
公开(公告)日：2011-10-18
申请号：US12120286
申请日：2008-05-14
申请人： Scott D. Allen , Cyril Cabral, Jr. , Kevin K. Dezfulian , Sunfei Fang , Brian J. Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement H. Wann , Huilong Zhu
发明人： Scott D. Allen , Cyril Cabral, Jr. , Kevin K. Dezfulian , Sunfei Fang , Brian J. Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement H. Wann , Huilong Zhu
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/268 , H01L21/2686 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/28176 , H01L21/324 , H01L29/517 , H01L29/665
摘要： An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.
摘要翻译：用于形成场效应晶体管的光热退火方法使用反射金属栅极，使得当相邻的源极/漏极区域进行光热退火时，金属栅极的电特性以及金属栅极和栅极电介质之间的界面不受损害金属门。另一种光热退火方法可以用于同时光热退火：（1）硅层和形成硅化物的金属层以形成完全硅化的栅极; 和（2）源/漏区以形成退火的源/漏区。附加的光热退火方法可以使用与热吸收层结合的热绝缘体层来选择性地使硅层和形成硅化物的金属层光退火以形成完全硅化物栅极。

5. 发明授权

US07309901B2 Field effect transistors (FETs) with multiple and/or staircase silicide 失效
标题翻译：具有多个和/或阶梯硅化物的场效应晶体管（FET）
公开(公告)号：US07309901B2
公开(公告)日：2007-12-18
申请号：US10908087
申请日：2005-04-27
申请人： Xiangdong Chen , Sunfei Fang , Zhijiong Luo , Haining Yang , Huilong Zhu
发明人： Xiangdong Chen , Sunfei Fang , Zhijiong Luo , Haining Yang , Huilong Zhu
IPC分类号： H01L21/8232
CPC分类号： H01L29/7833 , H01L29/665 , H01L29/6659
摘要： A semiconductor structure and method for forming the same. The semiconductor structure comprises a field effect transistor (FET) having a channel region disposed between first and second source/drain (S/D) extension regions which are in turn in direct physical contact with first and second S/D regions, respective. First and second silicide regions are formed such that the first silicide region is in direct physical contact with the first S/D region and the first S/D extension region, whereas the second silicide region is in direct physical contact with the second S/D region and the second S/D extension region. The first silicide region is thinner for regions in contact with first S/D extension region than for regions in contact with the first S/D region. Similarly, the second silicide region is thinner for regions in contact with second S/D extension region than for regions in contact with the second S/D region.
摘要翻译：一种半导体结构及其形成方法。半导体结构包括场效应晶体管（FET），其具有设置在第一和第二源极/漏极（S / D）延伸区域之间的沟道区域，第一和第二源极/漏极（S / D）延伸区域又分别与第一和第二S / D区域直接物理接触。形成第一和第二硅化物区域，使得第一硅化物区域与第一S / D区域和第一S / D延伸区域直接物理接触，而第二硅化物区域与第二S / D区域直接物理接触区域和第二S / D扩展区域。对于与第一S / D延伸区域接触的区域，第一硅化物区域比与第一S / D区域接触的区域更薄。类似地，对于与第二S / D延伸区域接触的区域，第二硅化物区域比与第二S / D区域接触的区域更薄。

6. 发明申请

US20070249131A1 Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors 有权
标题翻译：用于形成金属栅极和全硅化栅场效应晶体管的光热退火方法
公开(公告)号：US20070249131A1
公开(公告)日：2007-10-25
申请号：US11408522
申请日：2006-04-21
申请人： Scott Allen , Cyril Cabral , Kevin Dezfulian , Sunfei Fang , Brian Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement Wann , Huilong Zhu
发明人： Scott Allen , Cyril Cabral , Kevin Dezfulian , Sunfei Fang , Brian Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement Wann , Huilong Zhu
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L21/268 , H01L21/2686 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/28176 , H01L21/324 , H01L29/517 , H01L29/665
摘要： An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.
摘要翻译：用于形成场效应晶体管的光热退火方法使用反射金属栅极，使得当相邻的源极/漏极区域进行光热退火时，金属栅极的电特性以及金属栅极和栅极电介质之间的界面不受损害金属门。另一种光热退火方法可以用于同时光热退火：（1）硅层和形成硅化物的金属层以形成完全硅化的栅极; 和（2）源/漏区以形成退火的源/漏区。附加的光热退火方法可以使用与热吸收层结合的热绝缘体层来选择性地使硅层和形成硅化物的金属层光退火以形成完全硅化物栅极。

7. 发明授权

US07105440B2 Self-forming metal silicide gate for CMOS devices 失效
标题翻译：用于CMOS器件的自成型金属硅化物栅极
公开(公告)号：US07105440B2
公开(公告)日：2006-09-12
申请号：US10905629
申请日：2005-01-13
申请人： Zhijiong Luo , Sunfei Fang , Huilong Zhu
发明人： Zhijiong Luo , Sunfei Fang , Huilong Zhu
IPC分类号： H01L21/44
CPC分类号： H01L29/4975 , H01L21/28097 , H01L21/823835 , H01L29/665 , H01L29/7833
摘要： A process for forming a metal suicide gate in an FET device, where the suicide is self-forming (that is, formed without the need for a separate metal/silicon reaction step), and no CMP or etchback of the silicon material is required. A first layer of silicon material (polysilicon or amorphous silicon) is formed overlying the gate dielectric; a layer of metal is then formed on the first layer, and a second layer of silicon on the metal layer. A high-temperature (>700° C.) processing step, such as source/drain activation anneal, is subsequently performed; this step is effective to form a silicide layer above the gate dielectric by reaction of the metal with silicon in the first layer. A second high-temperature processing step (such as source/drain silicidation) may be performed which is effective to form a second silicide layer from silicon in the second layer. The thicknesses of the layers are such that in the high-temperature processing, substantially all of the first layer and at least a portion of the second layer are replaced by silicide material. Accordingly, a fully silicided gate structure may be produced.
摘要翻译：在FET器件中形成金属硅化物栅极的方法，其中硅化物自成型（即，不需要单独的金属/硅反应步骤形成），并且不需要CMP材料的CMP或回蚀。第一层硅材料（多晶硅或非晶硅）形成在栅极电介质上方; 然后在第一层上形成金属层，在金属层上形成第二层硅。随后进行高温（> 700℃）处理步骤，例如源极/漏极激活退火; 该步骤通过金属与第一层中的硅的反应在栅电介质上形成硅化物层是有效的。可以进行第二高温处理步骤（例如源极/漏极硅化），其有效地从第二层中的硅形成第二硅化物层。层的厚度使得在高温处理中，基本上所有的第一层和第二层的至少一部分被硅化物材料代替。因此，可以产生完全硅化的栅极结构。

8. 发明申请

US20060154413A1 SELF-FORMING METAL SILICIDE GATE FOR CMOS DEVICES 失效
标题翻译：用于CMOS器件的自成型金属硅化物栅
公开(公告)号：US20060154413A1
公开(公告)日：2006-07-13
申请号：US10905629
申请日：2005-01-13
申请人： Zhijiong Luo , Sunfei Fang , Huilong Zhu
发明人： Zhijiong Luo , Sunfei Fang , Huilong Zhu
IPC分类号： H01L21/8234
CPC分类号： H01L29/4975 , H01L21/28097 , H01L21/823835 , H01L29/665 , H01L29/7833
摘要： A process for forming a metal suicide gate in an FET device, where the suicide is self-forming (that is, formed without the need for a separate metal/silicon reaction step), and no CMP or etchback of the silicon material is required. A first layer of silicon material (polysilicon or amorphous silicon) is formed overlying the gate dielectric; a layer of metal is then formed on the first layer, and a second layer of silicon on the metal layer. A high-temperature (>700° C.) processing step, such as source/drain activation anneal, is subsequently performed; this step is effective to form a silicide layer above the gate dielectric by reaction of the metal with silicon in the first layer. A second high-temperature processing step (such as source/drain silicidation) may be performed which is effective to form a second silicide layer from silicon in the second layer. The thicknesses of the layers are such that in the high-temperature processing, substantially all of the first layer and at least a portion of the second layer are replaced by silicide material. Accordingly, a fully silicided gate structure may be produced.
摘要翻译：在FET器件中形成金属硅化物栅极的方法，其中硅化物自成型（即，不需要单独的金属/硅反应步骤形成），并且不需要CMP材料的CMP或回蚀。第一层硅材料（多晶硅或非晶硅）形成在栅极电介质上方; 然后在第一层上形成金属层，在金属层上形成第二层硅。随后进行高温（> 700℃）处理步骤，例如源极/漏极激活退火; 该步骤通过金属与第一层中的硅的反应在栅电介质上形成硅化物层是有效的。可以进行第二高温处理步骤（例如源极/漏极硅化），其有效地从第二层中的硅形成第二硅化物层。层的厚度使得在高温处理中，基本上所有的第一层和第二层的至少一部分被硅化物材料代替。因此，可以产生完全硅化的栅极结构。

9. 发明授权

US07816219B2 Field effect transistors (FETs) with multiple and/or staircase silicide 有权
标题翻译：具有多个和/或阶梯硅化物的场效应晶体管（FET）
公开(公告)号：US07816219B2
公开(公告)日：2010-10-19
申请号：US11850076
申请日：2007-09-05
申请人： Xiangdong Chen , Sunfei Fang , Zhijiong Luo , Haining Yang , Huilong Zhu
发明人： Xiangdong Chen , Sunfei Fang , Zhijiong Luo , Haining Yang , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L29/665 , H01L29/6659
摘要： A semiconductor structure and method for forming the same. First, a semiconductor structure is provided, including (a) a semiconductor layer including (i) a channel region and (ii) first and second source/drain (S/D) extension regions, and (iii) first and second S/D regions, (b) a gate dielectric region in direction physical contact with the channel region via a first interfacing surface that defines a reference direction essentially perpendicular to the first interfacing surface, and (c) a gate region in direct physical contact with the gate dielectric region, wherein the gate dielectric region is sandwiched between and electrically insulates the gate region and the channel region. Then, (i) a first shallow contact region is formed in direct physical contact with the first S/D extension region, and (ii) a first deep contact region is formed in direct physical contact with the first S/D region and the first shallow contact region.
摘要翻译：一种半导体结构及其形成方法。首先，提供半导体结构，其包括（a）包括（i）沟道区和（ii）第一和第二源/漏（S / D）延伸区的半导体层，以及（iii）第一和第二S / D 区域，（b）通过限定基本上垂直于第一接口表面的参考方向的第一接口表面方向与沟道区域物理接触的栅极电介质区域，以及（c）与栅极电介质直接物理接触的栅极区域区域，其中栅极电介质区域夹在栅极区域和沟道区域之间并使电绝缘。然后，（i）第一浅接触区域形成为与第一S / D延伸区域直接物理接触，并且（ii）第一深接触区域形成为与第一S / D区域和第一浅/ 浅接触区域。

10. 发明申请

US20070298572A1 FIELD EFFECT TRANSISTORS (FETs) WITH MULTIPLE AND/OR STAIRCASE SILICIDE 有权
标题翻译：具有多个和/或多个硅化物的场效应晶体管（FET）
公开(公告)号：US20070298572A1
公开(公告)日：2007-12-27
申请号：US11850076
申请日：2007-09-05
申请人： Xiangdong Chen , Sunfei Fang , Zhijiong Luo , Haining Yang , Huilong Zhu
发明人： Xiangdong Chen , Sunfei Fang , Zhijiong Luo , Haining Yang , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L29/665 , H01L29/6659
摘要： A semiconductor structure and method for forming the same. First, a semiconductor structure is provided, including (a) a semiconductor layer including (i) a channel region and (ii) first and second source/drain (S/D) extension regions, and (iii) first and second S/D regions, (b) a gate dielectric region in direction physical contact with the channel region via a first interfacing surface that defines a reference direction essentially perpendicular to the first interfacing surface, and (c) a gate region in direct physical contact with the gate dielectric region, wherein the gate dielectric region is sandwiched between and electrically insulates the gate region and the channel region. Then, (i) a first shallow contact region is formed in direct physical contact with the first S/D extension region, and (ii) a first deep contact region is formed in direct physical contact with the first S/D region and the first shallow contact region.
摘要翻译：一种半导体结构及其形成方法。首先，提供半导体结构，其包括（a）包括（i）沟道区和（ii）第一和第二源/漏（S / D）延伸区的半导体层，以及（iii）第一和第二S / D 区域，（b）通过限定基本上垂直于第一接口表面的参考方向的第一接口表面方向与沟道区域物理接触的栅极电介质区域，以及（c）与栅极电介质直接物理接触的栅极区域区域，其中栅极电介质区域夹在栅极区域和沟道区域之间并使电绝缘。然后，（i）第一浅接触区域形成为与第一S / D延伸区域直接物理接触，并且（ii）第一深接触区域形成为与第一S / D区域和第一浅/ 浅接触区域。

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