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    • 1. 发明授权
    • Connector drawer
    • 连接器抽屉
    • US07217144B1
    • 2007-05-15
    • US11329632
    • 2006-01-11
    • Thomas M. CipollaLawrence S. Mok
    • Thomas M. CipollaLawrence S. Mok
    • H01L21/82
    • H01R27/02H01R13/73
    • An arrangement and a method of increasing the quantity of input and output connectors, which are available for the attachment to connection cables of electronic equipment. More particularly, the present invention relates to an arrangement, such as a connector drawer, which is adapted to be installed in a selectively retractable and extendable mode in a laptop computer and which provides for a versatile structure facilitating a elective increase in the quantity of input and output connectors as may be necessitated by specific utilization of the electronic equipment or laptop computers, particularly in conjunction with the connection therewith of auxiliary operating devices or components.
    • 一种增加输入和输出连接器的数量的装置和方法,其可用于连接到电子设备的连接电缆。 更具体地,本发明涉及一种诸如连接器抽屉的装置,其适于以笔记本电脑中的可选择性地伸缩和可延伸的方式安装,并且其提供通用结构,便于输入量的选择性增加 以及通过电子设备或膝上型计算机的特定利用可能需要的输出连接器,特别是与辅助操作装置或部件的连接。
    • 10. 发明授权
    • Massively parallel supercomputer
    • 大型并行超级计算机
    • US07555566B2
    • 2009-06-30
    • US10468993
    • 2002-02-25
    • Matthias A. BlumrichDong ChenGeorge L. ChiuThomas M. CipollaPaul W. CoteusAlan G. GaraMark E. GiampapaPhilip HeidelbergerGerard V. KopcsayLawrence S. MokTodd E. Takken
    • Matthias A. BlumrichDong ChenGeorge L. ChiuThomas M. CipollaPaul W. CoteusAlan G. GaraMark E. GiampapaPhilip HeidelbergerGerard V. KopcsayLawrence S. MokTodd E. Takken
    • G06F15/16
    • H05K7/20836F24F11/77G06F9/52G06F9/526G06F15/17381G06F17/142G09G5/008H04L7/0338
    • A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. In the preferred embodiment, the multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. For particular classes of parallel algorithms, or parts of parallel calculations, this architecture exhibits exceptional computational performance, and may be enabled to perform calculations for new classes of parallel algorithms. Additional networks are provided for external connectivity and used for Input/Output, System Management and Configuration, and Debug and Monitoring functions. Special node packaging techniques implementing midplane and other hardware devices facilitates partitioning of the supercomputer in multiple networks for optimizing supercomputing resources.
    • 数百个teraOPS级别的新型大规模并行超级计算机包括基于片上系统技术的节点架构,即,每个处理节点包括单个专用集成电路(ASIC)。 在每个ASIC节点内是多个处理元件,每个处理元件由中央处理单元(CPU)和多个浮点处理器组成,以实现计算性能,封装密度,低成本以及功率和冷却​​要求的最佳平衡。 单个节点内的多个处理器可以单独使用或同时使用,以在任何时间点解决或执行的特定算法所要求的任何计算或通信组合上工作。 片上系统ASIC节点通过多个独立网络互连,从而最大限度地最大限度地提高了分组通信吞吐量并最大限度地减少了延迟。 在优选实施例中,多个网络包括用于并行算法消息传递的三个高速网络,包括提供全局障碍和通知功能的环形,全局树和全球异步网络。 这些多个独立网络可以根据用于优化算法处理性能的算法的需求或阶段来协同或独立地利用。 对于特定类别的并行算法或并行计算的部分,该架构具有出色的计算性能,并且可以启用对新类并行算法执行计算。 为外部连接提供附加网络,用于输入/输出,系统管理和配置以及调试和监控功能。 实现中平面和其他硬件设备的特殊节点打包技术有助于在多个网络中划分超级计算机,以优化超级计算资源。