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1. 发明授权

US06258658B1 Memory cell configuration and corresponding fabrication method 有权
标题翻译：存储单元配置及相应的制造方法
公开(公告)号：US06258658B1
公开(公告)日：2001-07-10
申请号：US09250362
申请日：1999-02-12
申请人： Thomas Böhm , Volker Weinrich , Manfred Hain , Armin Kohlhase , Yoichi Otani , Andreas Rusch , Till Schlösser
发明人： Thomas Böhm , Volker Weinrich , Manfred Hain , Armin Kohlhase , Yoichi Otani , Andreas Rusch , Till Schlösser
IPC分类号： H01L218242
CPC分类号： H01L27/10823 , H01L27/10808
摘要： The memory cell configuration has a multiplicity of preferably ferroelectric memory cells in a semiconductor substrate. Mutually parallel bit line trenches run in the longitudinal direction in the main surface of the semiconductor substrate. Bit lines are disposed in the bottoms of the trenches. Source/drain regions are formed in the crowns of the trenches. Channel regions are provided in the walls of the trenches. The channel region on a wall in each case is configured such that a drivable selection transistor of the relevant memory cell is formed there, while the channel region on the other wall is configured such that the transistor located there is closed. Insulated word lines for driving the selection transistors run in the transverse direction along the main surface of the semiconductor substrate through the bit line trenches. Insulation trenches for insulating the source/drain regions in the longitudinal direction of neighboring memory cells run in the transverse direction in the main surface of the semiconductor substrate. A respective, preferably ferroelectric, capacitor is connected to the source/drain region of the respective memory cell and is arranged above the word lines.
摘要翻译：存储单元配置在半导体衬底中具有多个优选铁电存储单元。相互并行的位线沟槽在半导体衬底的主表面中沿纵向延伸。位线设置在沟槽的底部。源极/漏极区域形成在沟槽的冠部中。通道区域设置在沟槽的壁中。在每种情况下，壁上的沟道区域被构造成使得相关存储单元的可驱动选择晶体管形成在其中，而另一壁上的沟道区域被配置为使得位于那里的晶体管闭合。用于驱动选择晶体管的绝缘字线通过位线沟槽沿着半导体衬底的主表面在横向方向上延伸。用于绝缘沟槽，用于使相邻存储单元的纵向上的源极/漏极区域绝缘，在半导体衬底的主表面中沿横向延伸。相应的优选铁电电容器连接到相应存储单元的源极/漏极区域并且被布置在字线之上。

2. 发明授权

US06472696B1 Memory cell configuration and corresponding production process 失效
标题翻译：内存单元配置及相应的生产流程
公开(公告)号：US06472696B1
公开(公告)日：2002-10-29
申请号：US09645763
申请日：2000-08-25
申请人： Ulrich Zimmermann , Thomas Böhm , Manfred Hain , Armin Kohlhase , Yoichi Otani , Andreas Rusch , Alexander Trüby
发明人： Ulrich Zimmermann , Thomas Böhm , Manfred Hain , Armin Kohlhase , Yoichi Otani , Andreas Rusch , Alexander Trüby
IPC分类号： H01L2710
CPC分类号： H01L27/11273 , H01L27/112
摘要： The memory cell configuration has a large number of memory cells provided in a semiconductor substrate and having bit-line trenches which extend in parallel in the longitudinal direction in the main face of the semiconductor substrate, at the bottoms of which in each case a first conductive region is provided, at the peaks of which in each case a second conductive region of the same conduction type as the first conductive region is provided, and in the walls of which in each case an intermediately located channel region is 0 provided; and having word lines which extend in the transverse direction along the main face of the semiconductor substrate, through specific bit-line trenches, to activate transistors provided there. An additional dopant is introduced into the trench walls of the bit-line trenches which are located between the word lines, in order to increase the corresponding transistor turn-on voltage there to suppress leakage currents.
摘要翻译：存储单元配置具有设置在半导体衬底中的大量存储单元，并且具有在半导体衬底的主面中在纵向方向上平行延伸的位线沟槽，其底部在每种情况下都具有第一导电区域被提供，其峰值在每种情况下具有与第一导电区域相同的导电类型的第二导电区域，并且在其每一种情况下壁的中间位置的沟道区域为0; 并且具有通过特定位线沟槽沿着半导体衬底的主面在横向上延伸的字线，以激活在其中设置的晶体管。另外的掺杂剂被引入位于字线之间的位线沟槽的沟槽壁中，以便在其上增加对应的晶体管导通电压以抑制漏电流。

3. 发明授权

US07230877B1 Method of making a semiconductor memory device 有权
标题翻译：制造半导体存储器件的方法
公开(公告)号：US07230877B1
公开(公告)日：2007-06-12
申请号：US09685361
申请日：2000-10-10
申请人： Andreas Rusch , Steffen Rothenhäusser , Alexander Truby , Yoichi Otani , Ulrich Zimmermann
发明人： Andreas Rusch , Steffen Rothenhäusser , Alexander Truby , Yoichi Otani , Ulrich Zimmermann
IPC分类号： H01L21/8234
CPC分类号： H01L27/112 , H01L21/822 , H01L27/101
摘要： A method for fabricating a semiconductor memory device is described. An insulating layer is disposed on a semiconductor substrate. A matrix of semiconductor memory elements is disposed in the substrate. The semiconductor memory elements include a plurality of contact holes formed in the insulating layer. One contact hole is formed in the insulating layer for each of the semiconductor memory elements. A bit definition region is disposed in the semiconductor substrate underneath each of the contact holes. A contact plug is disposed in each of the contact holes and is in electrical contact with the bit definition region. The bit definition region is configured such that a contact resistance between the semiconductor substrate and the contact plug defines a bit to be stored in the semiconductor memory elements, An evaluation circuit is connected to and evaluates the contact resistance of the semiconductor memory elements.
摘要翻译：对半导体存储器件的制造方法进行说明。绝缘层设置在半导体衬底上。半导体存储元件的矩阵设置在基板中。半导体存储元件包括形成在绝缘层中的多个接触孔。对于每个半导体存储元件，在绝缘层中形成一个接触孔。位于每个接触孔下面的半导体衬底中的位定义区域。接触插头设置在每个接触孔中并且与位定义区域电接触。位定义区域被配置为使得半导体衬底和接触插塞之间的接触电阻限定要存储在半导体存储器元件中的位。评估电路连接到并评估半导体存储器元件的接触电阻。

4. 发明授权

US07807526B2 Method of fabricating high-density, trench-based non-volatile random access SONOS memory cells for SOC applications 失效
标题翻译：制造用于SOC应用的高密度，基于沟槽的非易失性随机接入SONOS存储器单元的方法
公开(公告)号：US07807526B2
公开(公告)日：2010-10-05
申请号：US11928615
申请日：2007-10-30
申请人： Herbert L. Ho , Jack A. Mandelman , Tak H. Ning , Yoichi Otani
发明人： Herbert L. Ho , Jack A. Mandelman , Tak H. Ning , Yoichi Otani
IPC分类号： H01L21/8238
CPC分类号： H01L27/115 , G11C16/0466 , H01L27/0207 , H01L27/105 , H01L27/11568 , H01L27/1157 , H01L27/11573 , H01L29/792 , H01L29/7926
摘要： The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as method of fabricating the same. In one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located with a trench structure having trench depth from 1 to 2 μm and the memory transistor is located on a surface of a semiconductor substrate adjoining the trench structure. In another embodiment, a 2-Tr SONOS memory cell is provided in which both the select transistor and the memory transistor are located within a trench structure having the depth mentioned above.
摘要翻译：本发明提供具有随机存取的存储位置的双晶体管氧化硅 - 氧化物 - 氧化物半导体（2-Tr SONOS）非易失性存储单元及其制造方法。在一个实施例中，提供了2-Tr SONOS单元，其中选择晶体管位于具有1至2μm的沟槽深度的沟槽结构，并且存储晶体管位于与沟槽结构相邻的半导体衬底的表面上。在另一个实施例中，提供了2-Tr SONOS存储单元，其中选择晶体管和存储晶体管都位于具有上述深度的沟槽结构内。

5. 发明申请

US20090321794A1 CMOS DEVICES INCORPORATING HYBRID ORIENTATION TECHNOLOGY (HOT) WITH EMBEDDED CONNECTORS 有权
标题翻译：嵌入式连接器的混合定向技术（HOT）的CMOS器件
公开(公告)号：US20090321794A1
公开(公告)日：2009-12-31
申请号：US12555350
申请日：2009-09-08
申请人： Byeong Y. Kim , Xiaomeng Chen , Yoichi Otani
发明人： Byeong Y. Kim , Xiaomeng Chen , Yoichi Otani
IPC分类号： H01L29/04
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1207
摘要： The present invention relates to complementary devices, such as n-FETs and p-FETs, which have hybrid channel orientations and are connected by conductive connectors that are embedded in a semiconductor substrate. Specifically, the semiconductor substrate has at least first and second device regions of different surface crystal orientations (i.e., hybrid orientations). An n-FET is formed at one of the first and second device regions, and a p-FET is formed at the other of the first and second device regions. The n-FET and the p-FET are electrically connected by a conductive connector that is located between the first and second device regions and embedded in the semiconductor substrate. Preferably, a dielectric spacer is first provided between the first and second device regions and recessed to form a gap therebetween. The conductive connector is then formed in the gap above the recessed dielectric spacer.
摘要翻译：本发明涉及具有混合通道取向并由嵌入在半导体衬底中的导电连接器连接的诸如n-FET和p-FET的互补器件。具体地，半导体衬底具有至少具有不同表面晶取向（即混合取向）的第一和第二器件区域。 n-FET形成在第一和第二器件区域中的一个处，并且p-FET形成在第一和第二器件区域中的另一个处。 n-FET和p-FET通过位于第一和第二器件区域之间的导电连接器电连接并嵌入在半导体衬底中。优选地，介电隔离件首先设置在第一和第二器件区域之间并且凹入以在它们之间形成间隙。然后将导电连接器形成在凹入的电介质间隔物上方的间隙中。

6. 发明申请

US20090158234A1 VERTICAL SOI TRENCH SONOS CELL 有权
标题翻译：垂直SOI TRENCH SONOS电池
公开(公告)号：US20090158234A1
公开(公告)日：2009-06-18
申请号：US11955913
申请日：2007-12-13
申请人： David M. Dobuzinsky , Herbert L. Ho , Jack A. Mandelman , Yoichi Otani
发明人： David M. Dobuzinsky , Herbert L. Ho , Jack A. Mandelman , Yoichi Otani
IPC分类号： G06F17/50
CPC分类号： H01L29/42352 , H01L21/28282 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L29/66833
摘要： A semiconductor memory device and a design structure including the semiconductor memory device embodied in a machine readable medium is provided. In particular the present invention includes a semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.
摘要翻译：提供半导体存储器件和包括体现在机器可读介质中的半导体存储器件的设计结构。特别地，本发明包括其中在绝缘体上半导体（SOI）衬底中产生垂直沟槽半导体 - 氧化物 - 氮化物 - 氧化物 - 半导体（SONOS）存储单元的半导体存储器件，其允许将基于SOI的互补金属氧化物半导体（CMOS）技术中的致密非易失性随机存取存储器（NVRAM）单元。使用常规沟槽处理处理沟槽，并且在本发明方法的开始附近处理允许将存储单元的制造完全从SOI逻辑处理分离开来的处理。

7. 发明申请

US20120292668A1 CMOS DEVICES INCORPORATING HYBRID ORIENTATION TECHNOLOGY (HOT) WITH EMBEDDED CONNECTORS 有权
标题翻译：嵌入式连接器的混合定向技术（HOT）的CMOS器件
公开(公告)号：US20120292668A1
公开(公告)日：2012-11-22
申请号：US13559877
申请日：2012-07-27
申请人： Byeong Y. Kim , Xiaomeng Chen , Yoichi Otani
发明人： Byeong Y. Kim , Xiaomeng Chen , Yoichi Otani
IPC分类号： H01L29/04
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1207
摘要： The present invention relates to complementary devices, such as n-FETs and p-FETs, which have hybrid channel orientations and are connected by conductive connectors that are embedded in a semiconductor substrate. Specifically, the semiconductor substrate has at least first and second device regions of different surface crystal orientations (i.e., hybrid orientations). An n-FET is formed at one of the first and second device regions, and a p-FET is formed at the other of the first and second device regions. The n-FET and the p-FET are electrically connected by a conductive connector that is located between the first and second device regions and embedded in the semiconductor substrate. Preferably, a dielectric spacer is first provided between the first and second device regions and recessed to form a gap therebetween. The conductive connector is then formed in the gap above the recessed dielectric spacer.
摘要翻译：本发明涉及具有混合通道取向并由嵌入在半导体衬底中的导电连接器连接的诸如n-FET和p-FET的互补器件。具体地，半导体衬底具有至少具有不同表面晶取向（即混合取向）的第一和第二器件区域。 n-FET形成在第一和第二器件区域中的一个处，并且p-FET形成在第一和第二器件区域中的另一个处。 n-FET和p-FET通过位于第一和第二器件区域之间的导电连接器电连接并嵌入在半导体衬底中。优选地，介电隔离件首先设置在第一和第二器件区域之间并且凹入以在它们之间形成间隙。然后将导电连接器形成在凹入的电介质间隔物上方的间隙中。

8. 发明授权

US07514323B2 Vertical SOI trench SONOS cell 有权
标题翻译：垂直SOI沟槽SONOS单元
公开(公告)号：US07514323B2
公开(公告)日：2009-04-07
申请号：US11164513
申请日：2005-11-28
申请人： David M. Dobuzinsky , Herbert L. Ho , Jack A. Mandelman , Yoichi Otani
发明人： David M. Dobuzinsky , Herbert L. Ho , Jack A. Mandelman , Yoichi Otani
IPC分类号： H01L29/00
CPC分类号： H01L29/792 , H01L21/26586 , H01L27/115 , H01L27/11568 , H01L29/7926
摘要： A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.
摘要翻译：提供一种半导体存储器件，其中在绝缘体上半导体（SOI）衬底中形成垂直沟槽半导体氧化物 - 氮化物 - 氧化物半导体（SONOS）存储单元，其允许将致密的非易失性随机存取基于SOI的互补金属氧化物半导体（CMOS）技术的存储器（NVRAM）单元。使用常规沟槽处理处理沟槽，并且在本发明方法的开始附近处理允许将存储单元的制造完全从SOI逻辑处理分离开来的处理。

9. 发明申请

US20060118850A1 COLLARLESS TRENCH DRAM DEVICE 失效
标题翻译：无缝TRENCH DRAM设备
公开(公告)号：US20060118850A1
公开(公告)日：2006-06-08
申请号：US10904933
申请日：2004-12-06
申请人： Yoichi Otani , Herbert Ho , Babar Khan , Paul Parries
发明人： Yoichi Otani , Herbert Ho , Babar Khan , Paul Parries
IPC分类号： H01L29/76 , H01L21/20
CPC分类号： H01L29/945 , H01L27/1087
摘要： The present invention provides collarless trench semiconductor memory devices having minimized vertical parasitic FET leakage and methods of forming the same.
摘要翻译：本发明提供了具有最小化的垂直寄生FET泄漏的无凹槽沟槽半导体存储器件及其形成方法。

10. 发明授权

US08120095B2 High-density, trench-based non-volatile random access SONOS memory SOC applications 有权
标题翻译：高密度，基于沟槽的非易失性随机存取SONOS存储器SOC应用
公开(公告)号：US08120095B2
公开(公告)日：2012-02-21
申请号：US11955940
申请日：2007-12-13
申请人： Herbert L. Ho , Jack A. Mandelman , Tak H. Ning , Yoichi Otani
发明人： Herbert L. Ho , Jack A. Mandelman , Tak H. Ning , Yoichi Otani
IPC分类号： H01L29/76
CPC分类号： H01L27/11568 , G11C16/0433 , H01L27/11565 , H01L27/1157
摘要： The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as a design structure including the semiconductor memory devices embodied in a machine readable medium. In one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located with a trench structure having trench depth from 1 to 2 μm and the memory transistor is located on a surface of a semiconductor substrate adjoining the trench structure. In another embodiment, a 2-Tr SONOS memory cell is provided in which both the select transistor and the memory transistor are located within a trench structure having the depth mentioned above.
摘要翻译：本发明提供了具有可随机存取的存储位置的双晶体管氧化硅 - 氧化物 - 氧化物半导体（2-Tr SONOS）非易失性存储单元，以及包括体现在机器可读介质中的半导体存储器件的设计结构。在一个实施例中，提供了2-Tr SONOS单元，其中选择晶体管位于具有1至2μm的沟槽深度的沟槽结构，并且存储晶体管位于与沟槽结构相邻的半导体衬底的表面上。在另一个实施例中，提供了2-Tr SONOS存储单元，其中选择晶体管和存储晶体管都位于具有上述深度的沟槽结构内。

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