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1. 发明授权

US06258658B1 Memory cell configuration and corresponding fabrication method 有权
标题翻译：存储单元配置及相应的制造方法
公开(公告)号：US06258658B1
公开(公告)日：2001-07-10
申请号：US09250362
申请日：1999-02-12
申请人： Thomas Böhm , Volker Weinrich , Manfred Hain , Armin Kohlhase , Yoichi Otani , Andreas Rusch , Till Schlösser
发明人： Thomas Böhm , Volker Weinrich , Manfred Hain , Armin Kohlhase , Yoichi Otani , Andreas Rusch , Till Schlösser
IPC分类号： H01L218242
CPC分类号： H01L27/10823 , H01L27/10808
摘要： The memory cell configuration has a multiplicity of preferably ferroelectric memory cells in a semiconductor substrate. Mutually parallel bit line trenches run in the longitudinal direction in the main surface of the semiconductor substrate. Bit lines are disposed in the bottoms of the trenches. Source/drain regions are formed in the crowns of the trenches. Channel regions are provided in the walls of the trenches. The channel region on a wall in each case is configured such that a drivable selection transistor of the relevant memory cell is formed there, while the channel region on the other wall is configured such that the transistor located there is closed. Insulated word lines for driving the selection transistors run in the transverse direction along the main surface of the semiconductor substrate through the bit line trenches. Insulation trenches for insulating the source/drain regions in the longitudinal direction of neighboring memory cells run in the transverse direction in the main surface of the semiconductor substrate. A respective, preferably ferroelectric, capacitor is connected to the source/drain region of the respective memory cell and is arranged above the word lines.
摘要翻译：存储单元配置在半导体衬底中具有多个优选铁电存储单元。相互并行的位线沟槽在半导体衬底的主表面中沿纵向延伸。位线设置在沟槽的底部。源极/漏极区域形成在沟槽的冠部中。通道区域设置在沟槽的壁中。在每种情况下，壁上的沟道区域被构造成使得相关存储单元的可驱动选择晶体管形成在其中，而另一壁上的沟道区域被配置为使得位于那里的晶体管闭合。用于驱动选择晶体管的绝缘字线通过位线沟槽沿着半导体衬底的主表面在横向方向上延伸。用于绝缘沟槽，用于使相邻存储单元的纵向上的源极/漏极区域绝缘，在半导体衬底的主表面中沿横向延伸。相应的优选铁电电容器连接到相应存储单元的源极/漏极区域并且被布置在字线之上。

2. 发明授权

US06852240B2 Method of manufacturing a ferroelectric capacitor configuration 失效
标题翻译：铁电电容器配置的制造方法
公开(公告)号：US06852240B2
公开(公告)日：2005-02-08
申请号：US09793350
申请日：2001-02-26
申请人： Walter Hartner , Günther Schindler , Volker Weinrich , Igor Kasko
发明人： Walter Hartner , Günther Schindler , Volker Weinrich , Igor Kasko
IPC分类号： H01L27/105 , H01L21/02 , H01L21/8246 , H01G13/00
CPC分类号： H01L28/55 , H01L28/60 , H01L28/75
摘要： A ferroelectric capacitor configuration is configured with at least two different coercitive voltages. A first electrode structure having a surface which forms at least two levels is firstly produced. A layer of ferroelectric material of varying thickness is deposited over the first electrode by spin coating. A second electrode structure is subsequently formed on the layer of ferroelectric material.
摘要翻译：铁电电容器配置配置有至少两个不同的强制电压。首先产生具有形成至少两个层的表面的第一电极结构。通过旋涂在第一电极上沉积不同厚度的铁电材料层。随后在铁电材料层上形成第二电极结构。

3. 发明授权

US06716643B1 Method for producing a semiconductor memory element 有权
标题翻译：半导体存储元件的制造方法
公开(公告)号：US06716643B1
公开(公告)日：2004-04-06
申请号：US10048192
申请日：2002-06-03
申请人： Manfred Engelhardt , Volker Weinrich
发明人： Manfred Engelhardt , Volker Weinrich
IPC分类号： H01G706
CPC分类号： H01L27/10852 , H01L21/31144 , H01L28/55
摘要： A method for fabricating a contact hole for a semiconductor memory element. The memory element includes a silicon substrate, an intermediate dielectric layer on the substrate, and an upper layer on the intermediate dielectric layer. The method includes forming a perforated mask on the upper layer, the mask including a material that exhibits temperature stability. The upper layer and a depression are etched into the intermediate dielectric layer as far as a residual thickness using the perforated mask. A layer including O3/TEOS-SiO2 is deposited onto a structure thus obtained. The layer including O3/TEOS-SiO2 is removed from a bottom of the depression by etching. The depression is lowered by etching to produce the contact hole as far as an interface with the silicon substrate, the silicon substrate being uncovered, and the layer including O3/TEOS-SiO2 serving as a lateral seal of the upper layer during the lowering of the depression.
摘要翻译：一种用于制造用于半导体存储元件的接触孔的方法。存储元件包括硅衬底，衬底上的中间电介质层和中间电介质层上的上层。该方法包括在上层上形成穿孔掩模，该掩模包括表现出温度稳定性的材料。使用穿孔掩模将上层和凹陷蚀刻到中间介电层中至达残留厚度。将包含O 3 / TEOS-SiO 2的层沉积到由此获得的结构上。通过蚀刻从凹陷的底部除去包含O 3 / TEOS-SiO 2的层。通过蚀刻降低凹陷以产生接触孔，直到与硅衬底的界面，硅衬底未被覆盖，并且包含O 3 / TEOS-SiO 2的层在下降期间作为上层的侧向密封萧条。

4. 发明授权

US6037256A Method for producing a noble metal-containing structure on a substrate, and semiconductor component having such a noble metal-containing structure 失效
标题翻译：在基板上制造含贵金属的结构体的方法以及具有这种含贵金属的结构的半导体部件
公开(公告)号：US6037256A
公开(公告)日：2000-03-14
申请号：US15452
申请日：1998-01-29
申请人： Volker Weinrich , Carlos Mazure-Espejo
发明人： Volker Weinrich , Carlos Mazure-Espejo
IPC分类号： H01L21/28 , H01G4/008 , H01L21/02 , H01L21/3205 , C23C16/04
CPC分类号： H01L28/65 , H01L28/55
摘要： A method for producing a noble metal-containing structure on a substrate, and a semiconductor component having such a noble metal-containing structure, include introducing a noble metal into a preliminary structure by converting a gaseous compound of the noble metal with a non-noble metal in a preliminary structure into elementary noble metal and a gaseous compound of the non-noble metal. The process continues until a desired amount of the non-noble metal in the preliminary structure is replaced by the noble metal.
摘要翻译：在基板上制造含贵金属的结构体的方法以及具有这种含贵金属的结构的半导体部件，包括：将贵金属的气态化合物与非贵金属初级结构中的金属成为基本贵金属和非贵金属的气态化合物。该过程持续到预备结构中所需量的非贵金属被贵金属代替。

5. 发明授权

US07045070B1 Method of producing an electrode configuration and method of electrically contacting the electrode configuration 失效
标题翻译：制造电极结构的方法和电接触电极结构的方法
公开(公告)号：US07045070B1
公开(公告)日：2006-05-16
申请号：US09645807
申请日：2000-08-24
申请人： Volker Weinrich , Manfred Engelhardt , Werner Pamler , Hermann Wendt
发明人： Volker Weinrich , Manfred Engelhardt , Werner Pamler , Hermann Wendt
IPC分类号： H01B13/00 , H01L21/00
CPC分类号： H01L28/60 , H01L21/32136 , H01L21/32139
摘要： The electrode configuration includes at least one structured layer. A mask is produced on the layer to be structured and the layer is dry etched. The mask is at least slightly etchable by dry etching. The mask contains a metal silicide, a metal nitride or a metal oxide.
摘要翻译：电极配置包括至少一个结构化层。在待结构的层上产生掩模，并且该层被干蚀刻。该掩模至少可通过干蚀刻轻微刻蚀。掩模包含金属硅化物，金属氮化物或金属氧化物。

6. 发明授权

US06649424B2 Method for fabricating an integrated semiconductor circuit having a strongly polarizable dielectric or ferroelectric 有权
公开(公告)号：US06649424B2
公开(公告)日：2003-11-18
申请号：US10154340
申请日：2002-05-23
申请人： Manfred Mört , Walter Hartner , Volker Weinrich , Günther Schindler
发明人： Manfred Mört , Walter Hartner , Volker Weinrich , Günther Schindler
IPC分类号： H01L2100
CPC分类号： H01L28/55 , H01L21/02197 , H01L21/02282 , H01L21/02285 , H01L21/31691
摘要： A method of fabricating semiconductor circuits having integrated capacitors that have a dielectric or a ferroelectric material between electrodes. The materials are subjected to heat treatment at high temperatures in an oxygen atmosphere for the purpose of crystallization. The dielectric or ferroelectric is heated separately from the semiconductor substrate, is comminuted into small particles and only afterward applied in this form to the semiconductor substrate. This makes it possible to integrate substances with arbitrarily high crystallization temperature without damaging the integrated semiconductor circuit, since the semiconductor substrate itself does not have to be heated. Diffusion barriers for oxygen are unnecessary. Previous limitations on the capacitor capacitance are obviated owing to the free choice of dielectric or ferroelectric made possible, and the packing density of the capacitors is increased.

7. 发明授权

US06495415B2 Method for fabricating a patterned layer 有权
公开(公告)号：US06495415B2
公开(公告)日：2002-12-17
申请号：US10027532
申请日：2001-12-26
申请人： Walter Hartner , Igor Kasko , Volker Weinrich , Frank Hintermaier , Günther Schindler , Hermann Wendt
发明人： Walter Hartner , Igor Kasko , Volker Weinrich , Frank Hintermaier , Günther Schindler , Hermann Wendt
IPC分类号： H01L218242
CPC分类号： B82Y30/00 , B82Y10/00 , H01L21/76838 , H01L27/10852 , H01L28/60
摘要： A method for fabricating a patterned layer from a layer material. The method includes steps of: providing a substrate with at least one target region and at least one migration region; applying a layer material; adding a material to the layer material; and performing a heat treatment such that the layer material migrates from the migration region to the target region and a layer which is self-aligned and self-patterned with respect to the target region is formed. The method has the advantage that the layer material, which can often only be etched with difficulty, does not have to be patterned directly. The desired structure of the layer is predetermined by preliminarily structuring the substrate into a target region and a migration region, and is produced by the migration of the layer material as a result of the heat treatment.

8. 发明授权

US6136659A Production process for a capacitor electrode formed of a platinum metal 失效
标题翻译：由铂金属形成的电容器电极的制造方法
公开(公告)号：US6136659A
公开(公告)日：2000-10-24
申请号：US47850
申请日：1998-03-25
申请人： Gunther Schindler , Walter Hartner , Volker Weinrich , Carlos Mazure-Espejo
发明人： Gunther Schindler , Walter Hartner , Volker Weinrich , Carlos Mazure-Espejo
IPC分类号： H01L27/108 , H01L21/02 , H01L21/3213 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L21/20
CPC分类号： H01L28/65 , H01L21/32137
摘要： A production process for a capacitor electrode formed of a platinum metal includes producing a conductive electrode body on a substrate having a silicon-containing surface for the capacitor electrode. Platinum is deposited over the full surface, the platinum is silicized in a temperature step outside the electrode body and the platinum silicide is removed. The advantage of the invention is the avoidance of an etching process for metallic platinum.
摘要翻译：由铂金属形成的电容器电极的制造方法包括在具有用于电容器电极的含硅表面的基板上制造导电电极体。铂在整个表面上沉积，铂在电极体外部的温度阶段被硅化，除去铂硅化物。本发明的优点是避免金属铂的蚀刻工艺。

9. 发明授权

US06737692B2 Method for fabricating a component, and component having a metal layer and an insulation layer 失效
标题翻译：用于制造部件的方法，以及具有金属层和绝缘层的部件
公开(公告)号：US06737692B2
公开(公告)日：2004-05-18
申请号：US10370858
申请日：2003-02-20
申请人： Zvonimir Gabric , Werner Pamler , Volker Weinrich
发明人： Zvonimir Gabric , Werner Pamler , Volker Weinrich
IPC分类号： H01L2976
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/65
摘要： A method for improving the adhesion between a noble metal layer and an insulation layer includes configuring a silicon layer between the noble metal layer and the insulation layer. The silicon layer is siliconized and oxidized by a thermal treatment in an oxidative environment, resulting in an oxidized silicide layer with high intermixing of the noble metal and the formed oxide. The relatively large inner surface achieved as a result improves the adhesion between the noble metal layer and the insulation layer.
摘要翻译：一种用于改善贵金属层和绝缘层之间的粘附性的方法包括在贵金属层和绝缘层之间配置硅层。通过在氧化环境中的热处理将硅层硅化并氧化，得到氧化的硅化物层，其中贵金属和形成的氧化物的高混合。因此，实现的相对较大的内表面改善了贵金属层与绝缘层之间的粘合性。

10. 发明授权

US06708405B2 Method for producing an electrically conducting connection 有权
标题翻译：用于制造导电连接的方法
公开(公告)号：US06708405B2
公开(公告)日：2004-03-23
申请号：US09941955
申请日：2001-08-28
申请人： Barbara Hasler , Rainer Florian Schnabel , Guenther Schindler , Volker Weinrich
发明人： Barbara Hasler , Rainer Florian Schnabel , Guenther Schindler , Volker Weinrich
IPC分类号： H01K310
CPC分类号： H01L21/76847 , H01L21/76804 , H01L21/7687 , H01L21/76877 , H01L27/10855 , H01L28/60 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： A method is described for producing a conducting connection through insulating layers by way of a contact hole and conducting materials with which the contact hole is filled. The method permits the production of a contact hole resembling the shape of a wineglass, into which conducting filling material and barrier layers can be inserted without the known problems such as void formation, overetching trenches, and dielectric close-off. It is possible in this way, for example, to produce an electric connection between the diffusion zone of a selection transistor and the lower electrode of a storage capacitor of large-scale integrated DRAM and FeRAM components with the aid of only a few mask steps.
摘要翻译：描述了一种用于通过接触孔和通过接触孔填充的导电材料通过绝缘层产生导电连接的方法。该方法允许生产类似于酒杯的形状的接触孔，其中可以插入导电填充材料和阻挡层，而没有已知的问题，例如空隙形成，过蚀刻沟槽和介电封闭。以这种方式，可以借助于仅仅几个掩模步骤，在选择晶体管的扩散区和大规模集成DRAM的存储电容器的下电极和FeRAM组件之间产生电连接。

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