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1. 发明授权

US06408361B1 Autonomous way specific tag update 失效
标题翻译：自动方式特定标签更新
公开(公告)号：US06408361B1
公开(公告)日：2002-06-18
申请号：US09389446
申请日：1999-09-02
申请人： Thomas Albert Petersen , James Nolan Hardage, Jr. , Scott Ives Remington
发明人： Thomas Albert Petersen , James Nolan Hardage, Jr. , Scott Ives Remington
IPC分类号： G06F1200
CPC分类号： G06F12/0846 , G06F12/0831 , G06F12/0864
摘要： The present invention provides a method and apparatus for allowing autonomous, way specific tag updates. More specifically, the invention provides way specific tag and status updates while concurrently allowing reads of the ways not currently being updated. If a read hit is determined, then the read is processed in a typical fashion. However, if the read is a read miss and one of the ways is flagged as being updated, then all ways are read again once the specific way has completed its updated.
摘要翻译：本发明提供一种用于允许自主的，特定方式的标签更新的方法和装置。更具体地，本发明提供方式特定的标签和状态更新，同时允许读取当前不被更新的方式。如果确定了读命中，则以典型的方式处理读取。但是，如果读取是未命中，并且其中一种方式被标记为更新，则一旦特定方式完成更新，就会再次读取所有方法。

2. 发明授权

US06256713B1 Bus optimization with read/write coherence including ordering responsive to collisions 失效
标题翻译：具有读/写一致性的总线优化，包括响应于冲突的顺序
公开(公告)号：US06256713B1
公开(公告)日：2001-07-03
申请号：US09303365
申请日：1999-04-29
申请人： Srinath Audityan , James Nolan Hardage, Jr. , Thomas Albert Petersen
发明人： Srinath Audityan , James Nolan Hardage, Jr. , Thomas Albert Petersen
IPC分类号： G06F1200
CPC分类号： G06F13/18 , G06F12/0831
摘要： The present invention provides a method and apparatus for optimizing bus utilization while maintaining read and write coherence. More specifically the invention provides bus utilization optimization by prioritizing read transactions before write transactions, where there is no collision pending. When a collision pending is determined, then the read and write transactions are processed according to the age of the transaction(s) allowing for data coherency.
摘要翻译：本发明提供了一种在保持读写一致性的同时优化总线利用的方法和装置。更具体地，本发明通过在写入事务之前对读取事务进行优先级来提供总线利用率优化，其中没有冲突挂起。当确定冲突挂起时，则根据允许数据一致性的事务的年龄来处理读和写事务。

3. 发明授权

US06269360B1 Optimization of ordered stores on a pipelined bus via self-initiated retry 失效
标题翻译：通过自发重试优化流水线总线上的有序存储
公开(公告)号：US06269360B1
公开(公告)日：2001-07-31
申请号：US09066012
申请日：1998-04-24
申请人： Thomas Albert Petersen , James Nolan Hardage, Jr.
发明人： Thomas Albert Petersen , James Nolan Hardage, Jr.
IPC分类号： G06F1730
CPC分类号： G06F13/161 , Y10S707/99932
摘要： Where a plurality of ordered transactions are received for data transfers on a pipelined bus, each transaction in the series is initiated before all prospective retry responses to the preceding ordered transactions may be asserted. The address responses to all preceding ordered transfers are then monitored in connection with performance of the newly initiated transfer. If a retry response to any preceding ordered transaction is asserted, a self-initiated retry response for all subsequent transactions, including the newly initiated transfer, is also asserted. The system-retried transactions and all succeeding, ordered transactions are immediately reattempted. The overlapping performance of the ordered transfers reduces the latency of non-retried transfers, achieving performance comparable to non-ordered transactions. Even where a retry response is asserted, the total latency required for completion of both transactions in the ordered pair is reduced by at least a portion of the address-to-response latency, so that the impact of ordering requirements on system performance is minimized. Strict ordering is thus enforced while taking full advantage of the pipelined nature of the bus to maximize utilization of the bus bandwidth.
摘要翻译：在对流水线总线上的数据传输接收到多个有序事务的情况下，系列中的每个事务在所有对先前有序事务的预期重试响应可能被断言之前启动。然后，与新发起的传输的性能相关联地监视对所有先前有序传输的地址响应。如果对任何先前有序事务的重试响应被断言，则还会断言所有后续事务的自发起的重试响应，包括新发起的传输。系统重试的交易和所有后续的有序交易立即被重新尝试。有序传输的重叠性能降低了非重试传输的延迟，实现与非有序事务相当的性能。即使在重试响应被断言的情况下，完成有序对中的两个事务所需的总延迟也减少了地址到响应延迟的至少一部分，从而将排序要求对系统性能的影响降到最低。因此，在充分利用总线的流水线特性的同时强制执行严格排序，以最大限度地利用总线带宽。

4. 发明授权

US6023737A Multi-stage pipelined data coalescing for improved frequency operation 失效
标题翻译：多级流水线数据合并，提高频率运行
公开(公告)号：US6023737A
公开(公告)日：2000-02-08
申请号：US66014
申请日：1998-04-24
申请人： Thomas Albert Petersen , James Nolan Hardage, Jr.
发明人： Thomas Albert Petersen , James Nolan Hardage, Jr.
IPC分类号： G06F12/08 , G06F12/04 , G06F13/36 , G06F13/00
CPC分类号： G06F13/36
摘要： To implement full gathering of data transfers from a processor to a system bus without adding many levels of logic to the write enable logic for transaction queue entries or reducing the processor operating frequency, gatherable combinations are divided and gathering is performed in multiple stages operating in parallel. During the first stage, a subset of the full gathering is performed between incoming transactions and the last transaction received, coalescing the two transfers into a single transaction entry if one of the possible combinations within the subset is satisfied. During the second stage, existing queue entries are tested for the remainder of the full gather combination set and merged if a combination within the remaining subset is satisfied. The gathering logic may thus be split between the write enable logic and the entry control logic for the transaction queue, reducing the depth of logic required for any one path and increasing the set size of gatherable combinations implemented and/or the processor operating frequency. Any additional processor cycles required to complete full gathering are typically hidden by bus latency.
摘要翻译：为了实现从处理器到系统总线的数据传输的全面收集，而不会为事务队列条目的写使能逻辑增加许多级别的逻辑，或降低处理器的工作频率，可收集的组合被分割并且以并行运行的多个阶段进行采集。在第一阶段期间，在传入事务和所接收的最后事务之间执行完整收集的子集，如果满足子集内的可能组合之一，则将两个传输合并成单个事务条目。在第二阶段期间，如果剩余子集中的组合得到满足，则现有队列条目将针对完整集合组合集合的其余部分进行测试并合并。因此，采集逻辑可以在写入使能逻辑和用于事务队列的条目控制逻辑之间分开，从而减少任何一个路径所需的逻辑深度并增加实现的可收集组合和/或处理器工作频率的集合大小。总线延迟通常隐藏完成完全采集所需的任何其他处理器周期。

5. 发明授权

US06119204A Data processing system and method for maintaining translation lookaside buffer TLB coherency without enforcing complete instruction serialization 失效
标题翻译：用于保持翻译后备缓冲器TLB一致性的数据处理系统和方法，而不强制执行完整的指令串行化
公开(公告)号：US06119204A
公开(公告)日：2000-09-12
申请号：US108157
申请日：1998-06-30
申请人： Joseph Yih Chang , James Nolan Hardage, Jr. , Jose Melanio Nunez , Thomas Albert Petersen
发明人： Joseph Yih Chang , James Nolan Hardage, Jr. , Jose Melanio Nunez , Thomas Albert Petersen
IPC分类号： G06F12/10 , G06F13/14 , G06F12/08
CPC分类号： G06F12/1027 , G06F2212/682
摘要： A data processing system includes at least a first processor and a second processor that each have a respective translation lookaside buffer (TLB). In response to detection by the second processor of a TLB entry invalidation request, the second processor marks at least one memory referent instruction that is being processed by the second processor and invalidates a TLB entry in the TLB of the second processor. In response to receipt of a synchronization request at the second processor, the second processor indicates to the first processor that the second processor has invalidated the TLB entry if the second processor has completed processing the marked instruction. During the interval between receipt of the synchronization request and indicating to the first processor that the second processor has invalidated the TLB entry, the second processor continues to process instructions, including fetching instructions for processing. In this manner, the second processor is able to continue normal instruction processing during the process of TLB synchronization.
摘要翻译：数据处理系统至少包括第一处理器和第二处理器，每个具有相应的翻译后备缓冲器（TLB）。响应于第二处理器检测到TLB条目无效请求，第二处理器标记正在由第二处理器处理的至少一个存储器指示指令，并使第二处理器的TLB中的TLB条目无效。响应于在第二处理器处接收到同步请求，第二处理器向第一处理器指示如果第二处理器已经完成处理标记的指令，则第二处理器使TLB条目无效。在接收到同步请求和向第一处理器指示第二处理器使TLB条目无效的间隔期间，第二处理器继续处理指令，包括取指令进行处理。以这种方式，第二处理器能够在TLB同步的处理期间继续正常的指令处理。

6. 发明授权

US06898675B1 Data received before coherency window for a snoopy bus 失效
标题翻译：在Snoopy总线的一致性窗口之前收到的数据
公开(公告)号：US06898675B1
公开(公告)日：2005-05-24
申请号：US09138380
申请日：1998-08-24
申请人： Alexander Edward Okpisz , Thomas Albert Petersen
发明人： Alexander Edward Okpisz , Thomas Albert Petersen
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0831
摘要： Where a null response can be expected from devices snooping a load operation, data may be used by a requesting processor prior to the coherency response window. A null snoop response may be determined, for example, from the availability of the data without a bus transaction. The capability of accelerating data in this fashion requires only a few simple changes in processor state transitions, required to permit entry of the data completion wait state prior to the response wait state. Processors may forward accelerated data to execution units with the expectation that a null snoop response will be received during the coherency response window. If a non-null snoop response is received, an error condition is asserted. Data acceleration of the type described allows critical data to get back to the processor without waiting for the coherency response window.
摘要翻译：在设备侦听加载操作时可以期望空响应的情况下，请求处理器可以在相干性响应窗口之前使用数据。可以例如从没有总线事务的数据的可用性来确定空窥探响应。以这种方式加速数据的能力仅需要处理器状态转换的几个简单的改变，这是允许在响应等待状态之前输入数据完成等待状态所需要的。处理器可以将加速数据转发到执行单元，期望在一致性响应窗口期间将接收到空窥探响应。如果接收到非空窥探响应，则会发出错误条件。所描述类型的数据加速允许关键数据回到处理器，而不必等待一致性响应窗口。

7. 发明授权

US06317806B1 Static queue and index queue for storing values identifying static queue locations 失效
标题翻译：静态队列和索引队列，用于存储识别静态队列位置的值
公开(公告)号：US06317806B1
公开(公告)日：2001-11-13
申请号：US09315612
申请日：1999-05-20
申请人： Srinath Audityan , Thomas Albert Petersen , Robert Charles Podnar
发明人： Srinath Audityan , Thomas Albert Petersen , Robert Charles Podnar
IPC分类号： G06F1200
CPC分类号： G06F5/06 , G06F12/0855 , Y02D10/13
摘要： A queuing apparatus associated with a processor includes at least one static queue (11), an index generator (34), at least one index queue (37), and a static queue accessing arrangement. Each static queue (11) has a number of static queue locations (12), each for storing a static queue entry and an availability indicator (14) for indicating an availability status of the respective static queue location. The index generator (34) uses information from the static queue (11) to provide a unique index value for each static queue entry, the index value for a particular static queue entry identifying the static queue location (12) containing the particular static queue entry. Each index queue (37, 42) has a number of index queue locations (40), each for storing one of the index values provided by the index generator (34). The static queue accessing arrangement retrieves a selected index value from a particular index queue location (40), and uses the selected index value to retrieve the static queue entry with which the selected index value is associated. Multiple index queues (37, 42) facilitate prioritization of static queue entries, and reprioritization by transferring index queue values from one index queue to another. The index queues (37, 42) also facilitate compaction of unnecessary static queue entries.
摘要翻译：与处理器相关联的排队设备包括至少一个静态队列（11），索引生成器（34），至少一个索引队列（37）和静态队列访问布置。每个静态队列（11）具有多个静态队列位置（12），每个静态队列位置（12）用于存储静态队列条目和用于指示相应静态队列位置的可用性状态的可用性指示符（14）。索引生成器（34）使用来自静态队列（11）的信息为每个静态队列条目提供唯一的索引值，特定静态队列条目的索引值标识包含特定静态队列条目的静态队列位置（12）。每个索引队列（37,42）具有多个索引队列位置（40），每个索引队列位置（40）用于存储由索引生成器（34）提供的索引值之一。静态队列访问安排从特定索引队列位置（40）检索所选择的索引值，并使用所选择的索引值来检索与所选择的索引值相关联的静态队列条目。多个索引队列（37,42）有助于静态队列条目的优先化，并通过将索引队列值从一个索引队列传递到另一个索引队列来重新确定优先级。索引队列（37,42）还有助于压缩不必要的静态队列条目。

8. 发明授权

US07366092B2 Hash and route hardware with parallel routing scheme 失效
标题翻译：哈希和路由硬件并行路由方案
公开(公告)号：US07366092B2
公开(公告)日：2008-04-29
申请号：US10684871
申请日：2003-10-14
申请人： Laurent Moll , Barton J. Sano , Thomas Albert Petersen
发明人： Laurent Moll , Barton J. Sano , Thomas Albert Petersen
IPC分类号： H04J1/16 , H04L12/28
CPC分类号： H04L45/60 , H04L45/00 , H04L45/54 , H04L45/745 , H04L49/109
摘要： A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a parallel routing scheme for calculating routing information for incoming packets. Using the programmable hash and route routing scheme, a hash and route circuit can be programmed for a variety of applications, such as routing, flow-splitting or load balancing.
摘要翻译：结合用于计算输入分组的路由信息的并行路由方案来描述基本上在单个CMOS集成电路上实现的多处理器交换设备。使用可编程散列和路由路由方案，哈希和路由电路可以针对各种应用进行编程，例如路由，流分解或负载平衡。

9. 发明授权

US06615323B1 Optimizing pipelined snoop processing 有权
标题翻译：优化流水线窥探处理
公开(公告)号：US06615323B1
公开(公告)日：2003-09-02
申请号：US09389445
申请日：1999-09-02
申请人： Thomas Albert Petersen , Jose Melanio Nunez , Marie Jeannette Sullivan
发明人： Thomas Albert Petersen , Jose Melanio Nunez , Marie Jeannette Sullivan
IPC分类号： G06F1342
CPC分类号： G06F12/0831
摘要： A system and method are provided for maintaining cache coherency in symmetric multiprocessor system by having logic for performing snoop queries separate from logic for performing snoop actions. This logic split permits increased throughput because pending snoop queries must no longer wait until snoop actions complete. Two state machines are disclosed: a pipeline state machine for snoop queries; and a snoop action state machine, for executing the split logic handling snoop requests.
摘要翻译：提供了一种用于通过具有用于执行窥探查询的逻辑与用于执行窥探动作的逻辑分离的逻辑来在对称多处理器系统中维持高速缓存一致性的系统和方法。此逻辑拆分允许增加吞吐量，因为未完成的侦听查询必须不再等待，直到窥探操作完成。公开了两种状态机：用于窥探查询的流水线状态机; 和窥探动作状态机，用于执行分离逻辑处理侦听请求。

10. 发明授权

US06460133B1 Queue resource tracking in a multiprocessor system 失效
标题翻译：多处理器系统中的队列资源跟踪
公开(公告)号：US06460133B1
公开(公告)日：2002-10-01
申请号：US09315488
申请日：1999-05-20
申请人： Jose Melanio Nunez , Thomas Albert Petersen
发明人： Jose Melanio Nunez , Thomas Albert Petersen
IPC分类号： G06F900
CPC分类号： G06F13/1642 , G06F9/3824 , G06F9/3836 , G06F12/0831
摘要： A multiprocessor computer system including a set of processors where each processor in the set includes an execution unit for issuing operations and a processor queue suitable for queuing previously issued and still pending operations. The multiprocessor further includes means for forwarding operations issued by the processor to the processor queue and to an operation block queue of a memory subsystem that is connected to the multiprocessor. The depth of (i.e., the number of entries in) the operation block queue matches the depth of the processor queue. The processor queue, when full, inhibits the processor from issuing additional operations. In this manner, an operation issued by the processor is guaranteed an available entry in the operation block queue of the memory subsystem thereby eliminating the need for operation retry circuitry and protocols such as handshaking. Preferably, each processor queue includes a processor load queue and a processor store queue and the operation block queue includes a load queue and a store queue. In this embodiment, the depth of each of the processor load and store queues matches the depth of the operation block load and store queues respectively. In the preferred embodiment, the operation block is comprised of a load miss block that includes the operation block load queue and a store miss block that includes the operation block store queue. Still further preferably, the operation block store queue includes a set of store queues corresponding to the set of processors and the operation block load queue includes a set of load queues corresponding to the set of processors. Each queue entry preferably includes state information indicative of the status of the corresponding entry.
摘要翻译：一种包括一组处理器的多处理器计算机系统，其中集合中的每个处理器包括用于发布操作的执行单元和适于排队先前发布和尚待处理的操作的处理器队列。多处理器还包括用于将由处理器发出的操作转发到处理器队列和连接到多处理器的存储器子系统的操作块队列的装置。操作块队列的深度（即条目数）与处理器队列的深度相匹配。处理器队列在满时禁止处理器发出其他操作。以这种方式，由处理器发出的操作保证在存储器子系统的操作块队列中的可用条目，从而消除对操作重试电路和协议（例如握手）的需要。优选地，每个处理器队列包括处理器负载队列和处理器存储队列，并且操作块队列包括加载队列和存储队列。在该实施例中，每个处理器加载和存储队列的深度分别与操作块加载和存储队列的深度匹配。在优选实施例中，操作块包括包括操作块加载队列的负载未命中块和包括操作块存储队列的存储错误块。更优选地，操作块存储队列包括与该组处理器对应的一组存储队列，并且操作块加载队列包括与该组处理器对应的一组加载队列。每个队列条目优选地包括指示对应条目的状态的状态信息。

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