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1. 发明授权

US06317806B1 Static queue and index queue for storing values identifying static queue locations 失效
标题翻译：静态队列和索引队列，用于存储识别静态队列位置的值
公开(公告)号：US06317806B1
公开(公告)日：2001-11-13
申请号：US09315612
申请日：1999-05-20
申请人： Srinath Audityan , Thomas Albert Petersen , Robert Charles Podnar
发明人： Srinath Audityan , Thomas Albert Petersen , Robert Charles Podnar
IPC分类号： G06F1200
CPC分类号： G06F5/06 , G06F12/0855 , Y02D10/13
摘要： A queuing apparatus associated with a processor includes at least one static queue (11), an index generator (34), at least one index queue (37), and a static queue accessing arrangement. Each static queue (11) has a number of static queue locations (12), each for storing a static queue entry and an availability indicator (14) for indicating an availability status of the respective static queue location. The index generator (34) uses information from the static queue (11) to provide a unique index value for each static queue entry, the index value for a particular static queue entry identifying the static queue location (12) containing the particular static queue entry. Each index queue (37, 42) has a number of index queue locations (40), each for storing one of the index values provided by the index generator (34). The static queue accessing arrangement retrieves a selected index value from a particular index queue location (40), and uses the selected index value to retrieve the static queue entry with which the selected index value is associated. Multiple index queues (37, 42) facilitate prioritization of static queue entries, and reprioritization by transferring index queue values from one index queue to another. The index queues (37, 42) also facilitate compaction of unnecessary static queue entries.
摘要翻译：与处理器相关联的排队设备包括至少一个静态队列（11），索引生成器（34），至少一个索引队列（37）和静态队列访问布置。每个静态队列（11）具有多个静态队列位置（12），每个静态队列位置（12）用于存储静态队列条目和用于指示相应静态队列位置的可用性状态的可用性指示符（14）。索引生成器（34）使用来自静态队列（11）的信息为每个静态队列条目提供唯一的索引值，特定静态队列条目的索引值标识包含特定静态队列条目的静态队列位置（12）。每个索引队列（37,42）具有多个索引队列位置（40），每个索引队列位置（40）用于存储由索引生成器（34）提供的索引值之一。静态队列访问安排从特定索引队列位置（40）检索所选择的索引值，并使用所选择的索引值来检索与所选择的索引值相关联的静态队列条目。多个索引队列（37,42）有助于静态队列条目的优先化，并通过将索引队列值从一个索引队列传递到另一个索引队列来重新确定优先级。索引队列（37,42）还有助于压缩不必要的静态队列条目。

2. 发明授权

US06256713B1 Bus optimization with read/write coherence including ordering responsive to collisions 失效
标题翻译：具有读/写一致性的总线优化，包括响应于冲突的顺序
公开(公告)号：US06256713B1
公开(公告)日：2001-07-03
申请号：US09303365
申请日：1999-04-29
申请人： Srinath Audityan , James Nolan Hardage, Jr. , Thomas Albert Petersen
发明人： Srinath Audityan , James Nolan Hardage, Jr. , Thomas Albert Petersen
IPC分类号： G06F1200
CPC分类号： G06F13/18 , G06F12/0831
摘要： The present invention provides a method and apparatus for optimizing bus utilization while maintaining read and write coherence. More specifically the invention provides bus utilization optimization by prioritizing read transactions before write transactions, where there is no collision pending. When a collision pending is determined, then the read and write transactions are processed according to the age of the transaction(s) allowing for data coherency.
摘要翻译：本发明提供了一种在保持读写一致性的同时优化总线利用的方法和装置。更具体地，本发明通过在写入事务之前对读取事务进行优先级来提供总线利用率优化，其中没有冲突挂起。当确定冲突挂起时，则根据允许数据一致性的事务的年龄来处理读和写事务。

3. 发明授权

US06516420B1 Data synchronizer using a parallel handshaking pipeline wherein validity indicators generate and send acknowledgement signals to a different clock domain 有权
标题翻译：使用并行握手管道的数据同步器，其中有效性指示符生成并向不同的时钟域发送确认信号
公开(公告)号：US06516420B1
公开(公告)日：2003-02-04
申请号：US09426265
申请日：1999-10-25
申请人： Srinath Audityan , Chris Randall Stone , Ritesh Radheshyam Agrawal
发明人： Srinath Audityan , Chris Randall Stone , Ritesh Radheshyam Agrawal
IPC分类号： G06F1342
CPC分类号： G06F5/12 , H04L7/02
摘要： A data synchronizer transfers information across an asynchronous interface by using system domain and core domain logic on either side of the asynchronous interface. Information registers receive data beats from a data bus coupled to an external system. Each data beat is loaded into the registers in sequential order. A corresponding system valid bit is provided for each register and is set when the corresponding register is loaded. In the core domain, a corresponding set of core valid bit registers is set in response to the system valid bit registers being set. A data sampler monitors the core valid bits in sequential order and controls a multiplexor to select a corresponding one of the registers that contains valid data. The data sampler resets the core valid bits which in-turn reset the system valid bits to signal the completion of a data transfer across the asynchronous interface.
摘要翻译：数据同步器通过使用异步接口任意一侧的系统域和核心域逻辑跨异步接口传输信息。信息寄存器从耦合到外部系统的数据总线接收数据节拍。每个数据节拍按顺序加载到寄存器中。为每个寄存器提供相应的系统有效位，并在对应的寄存器加载时置1。在核心域中，响应于设置了系统有效位寄存器，设置相应的一组核心有效位寄存器。数据采样器按顺序监视核心有效位，并控制多路复用器选择包含有效数据的相应的一个寄存器。数据采样器将复位核心有效位，从而重置系统有效位，以通知异步接口数据传输的完成。

4. 发明授权

US06898682B2 Automatic READ latency calculation without software intervention for a source-synchronous interface 失效
标题翻译：自动读取延迟计算，无需软件干预源同步接口
公开(公告)号：US06898682B2
公开(公告)日：2005-05-24
申请号：US10217174
申请日：2002-08-12
申请人： James A. Welker , Srinath Audityan , Jose M. Nunez , Robert C. Podnar
发明人： James A. Welker , Srinath Audityan , Jose M. Nunez , Robert C. Podnar
IPC分类号： G06F12/00 , G06F12/14 , G06F13/42
CPC分类号： G06F13/4217
摘要： In response to a clock cycle and a pending READ command for data with a variably recurring access latency, a clock cycle count is adjusted. If a latency value has not been locked and if the READ command is a first READ command, the clock cycle count is stored as a locked latency value upon receiving a synchronized data available event (DQS for instance). Each subsequent READ command has an associated clock cycle count to enable pipelining wherein the clock cycle count for each READ starts incrementing when the individual READ command is issued. For subsequent READ commands, if the cycle count compares favorably with the locked latency value, data can be sampled safely from the interface at the identical latency for every READ request issued. The locked latency value can be read and/or written by software/hardware such that the read latency is consistent across multiple devices for reproducibility during debug.
摘要翻译：响应于具有可变重复访问延迟的数据的时钟周期和待处理的READ命令，调整时钟周期计数。如果延迟值未被锁定，并且READ命令是第一个READ命令，则在接收到同步数据可用事件（例如DQS）时，时钟周期计数被存储为锁定延迟值。每个随后的READ命令具有关联的时钟周期计数以启用流水线，其中当发出各个READ命令时，每个READ的时钟周期计数开始递增。对于随后的READ命令，如果循环计数与锁定的延迟值相比有利，则可以按照发出的每个READ请求以相同的等待时间从接口对数据进行安全采样。锁定的延迟值可以由软件/硬件读取和/或写入，使得读取延迟在多个设备之间保持一致，以便在调试期间重现。

5. 发明授权

US06847990B2 Data transfer unit with support for multiple coherency granules 有权
标题翻译：支持多个一致性粒子的数据传输单元
公开(公告)号：US06847990B2
公开(公告)日：2005-01-25
申请号：US10150671
申请日：2002-05-17
申请人： Srinath Audityan , Marie J. Sullivan , Jose M. Nunez
发明人： Srinath Audityan , Marie J. Sullivan , Jose M. Nunez
IPC分类号： G06F12/08 , G06F12/00 , G06F13/28 , G06F13/42
CPC分类号： G06F13/4208 , G06F12/0835 , G06F13/28
摘要： A data transfer unit is able to read data from a source at the source coherency granule size and write data at the destination coherency granule size even though the two granule sizes may be different. A data transfer unit has registers for storing the granule size information in preparation of performing a transfer of a data block between a source and a destination. The data block is transferred in sub-blocks. Except for the first and last sub-blocks, the sub-blocks, for a read, are sized to the source coherency granule size, which is the transfer size that has been optimized for the source. For the write, the sub-blocks are sized to the destination coherency granule size, which is the transfer size that has been optimized for the destination. Thus, both the read and the write are optimized even though the transfers themselves are among devices with different coherency granules.
摘要翻译：数据传输单元能够以源一致性粒度大小从源读取数据，并且以目的一致性粒度大小写入数据，即使两个粒度大小可能不同。数据传送单元具有用于在准备执行源和目的地之间的数据块的传送的情况下存储颗粒大小信息的寄存器。数据块在子块中传输。除了第一个和最后一个子块之外，用于读取的子块的大小与源相关性粒度大小相同，这是源已经优化的传输大小。对于写入，子块的大小与目标一致性粒度大小相同，这是目标优化的传输大小。因此，即使传输本身在具有不同一致性颗粒的设备中，读取和写入都被优化。

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