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1. 发明授权

US07366092B2 Hash and route hardware with parallel routing scheme 失效
标题翻译：哈希和路由硬件并行路由方案
公开(公告)号：US07366092B2
公开(公告)日：2008-04-29
申请号：US10684871
申请日：2003-10-14
申请人： Laurent Moll , Barton J. Sano , Thomas Albert Petersen
发明人： Laurent Moll , Barton J. Sano , Thomas Albert Petersen
IPC分类号： H04J1/16 , H04L12/28
CPC分类号： H04L45/60 , H04L45/00 , H04L45/54 , H04L45/745 , H04L49/109
摘要： A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a parallel routing scheme for calculating routing information for incoming packets. Using the programmable hash and route routing scheme, a hash and route circuit can be programmed for a variety of applications, such as routing, flow-splitting or load balancing.
摘要翻译：结合用于计算输入分组的路由信息的并行路由方案来描述基本上在单个CMOS集成电路上实现的多处理器交换设备。使用可编程散列和路由路由方案，哈希和路由电路可以针对各种应用进行编程，例如路由，流分解或负载平衡。

2. 发明申请

US20080198867A1 Hash and Route Hardware with Parallel Routing Scheme 审中-公开
标题翻译：并行路由方案的哈希和路由硬件
公开(公告)号：US20080198867A1
公开(公告)日：2008-08-21
申请号：US12109459
申请日：2008-04-25
申请人： Laurent Moll , Barton J. Sano , Thomas Albert Petersen
发明人： Laurent Moll , Barton J. Sano , Thomas Albert Petersen
IPC分类号： H04L12/56
CPC分类号： H04L45/60 , H04L45/00 , H04L45/54 , H04L45/745 , H04L49/109
摘要： A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a parallel routing scheme for calculating routing information for incoming packets. Using the programmable hash and route routing scheme, a hash and route circuit can be programmed for a variety of applications, such as routing, flow-splitting or load balancing.
摘要翻译：结合用于计算输入分组的路由信息的并行路由方案来描述基本上在单个CMOS集成电路上实现的多处理器交换设备。使用可编程散列和路由路由方案，哈希和路由电路可以针对各种应用进行编程，例如路由，流分解或负载平衡。

3. 发明申请

US20080228871A1 System having configurable interfaces for flexible system configurations 审中-公开
标题翻译：具有用于灵活系统配置的可配置接口的系统
公开(公告)号：US20080228871A1
公开(公告)日：2008-09-18
申请号：US12130044
申请日：2008-05-30
申请人： Barton J. Sano
发明人： Barton J. Sano
IPC分类号： G06F15/16
CPC分类号： G06F12/0831
摘要： An apparatus includes a plurality of memories, a plurality of systems, and a switch interface circuit. Each of the plurality of systems includes a memory controller coupled to a respective one of the plurality of memories. Additionally, each of the plurality of systems is coupled to at least one other one of the plurality of systems. Each of the plurality of systems further includes one or more coherent agents configured to access the plurality of memories, and wherein the plurality of systems enforce coherency across the plurality of systems for at least some accesses. At least one of the plurality of systems is coupled to the switch interface circuit separate from the interconnection of the plurality of systems. The switch interface circuit is configured to interface the apparatus to a switch fabric.
摘要翻译：一种装置包括多个存储器，多个系统和开关接口电路。多个系统中的每一个包括耦合到多个存储器中的相应一个的存储器控制器。另外，多个系统中的每一个耦合到多个系统中的至少另一个系统。所述多个系统中的每一个还包括被配置为访问所述多个存储器的一个或多个相干代理，并且其中所述多个系统在所述多个系统中执行用于至少一些访问的一致性。多个系统中的至少一个耦合到与多个系统的互连分离的开关接口电路。开关接口电路被配置为将设备连接到交换结构。

4. 发明授权

US06748479B2 System having interfaces and switch that separates coherent and packet traffic 有权
标题翻译：具有分离相干和分组业务的接口和交换机的系统
公开(公告)号：US06748479B2
公开(公告)日：2004-06-08
申请号：US10270029
申请日：2002-10-11
申请人： Barton J. Sano , Joseph B. Rowlands , James B. Keller , Laurent R. Moll , Koray Oner , Manu Gulati
发明人： Barton J. Sano , Joseph B. Rowlands , James B. Keller , Laurent R. Moll , Koray Oner , Manu Gulati
IPC分类号： G06F1300
CPC分类号： H04L49/901 , G06F12/0813 , G06F13/28 , H04L49/103 , H04L49/3009 , H04L49/90 , H04L49/9063 , H04L49/9073
摘要： An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.
摘要翻译：一种装置包括一个或多个接口电路，互连，存储器控制器，存储器桥，分组DMA电路和开关。存储器控制器，存储器桥和分组DMA电路耦合到互连。每个接口电路耦合到相应的接口以从接口接收分组和/或一致性命令。该开关耦合到接口电路，存储器桥和分组DMA电路。交换机被配置为将来自接口电路的相干命令路由到存储器桥以及从接口电路到分组DMA电路的分组。存储器桥被配置为响应于至少一些相关命令来在互连上发起相应的事务。分组DMA电路被配置为将互连上的写入事务传送到存储器控制器以将数据包存储在存储器中。

5. 发明授权

US07394823B2 System having configurable interfaces for flexible system configurations 有权
公开(公告)号：US07394823B2
公开(公告)日：2008-07-01
申请号：US10270014
申请日：2002-10-11
申请人： Barton J. Sano
发明人： Barton J. Sano
IPC分类号： H04L12/56
CPC分类号： G06F12/0831
摘要： An apparatus includes a plurality of memories, a plurality of systems, and a switch interface circuit. Each of the plurality of systems includes a memory controller coupled to a respective one of the plurality of memories. Additionally, each of the plurality of systems is coupled to at least one other one of the plurality of systems. Each of the plurality of systems further includes one or more coherent agents configured to access the plurality of memories, and wherein the plurality of systems enforce coherency across the plurality of systems for at least some accesses. At least one of the plurality of systems is coupled to the switch interface circuit separate from the interconnection of the plurality of systems. The switch interface circuit is configured to interface the apparatus to a switch fabric.

6. 发明授权

US06941406B2 System having interfaces and switch that separates coherent and packet traffic 有权
公开(公告)号：US06941406B2
公开(公告)日：2005-09-06
申请号：US10861624
申请日：2004-06-04
申请人： Barton J. Sano , Joseph B. Rowlands , James B. Keller , Laurent R. Moll , Koray Oner , Manu Gulati
发明人： Barton J. Sano , Joseph B. Rowlands , James B. Keller , Laurent R. Moll , Koray Oner , Manu Gulati
IPC分类号： G06F12/08 , G06F13/00 , G06F13/14 , G06F13/28 , G06F13/36 , G06F15/167 , H04L12/56 , H04Q11/00
CPC分类号： H04L49/901 , G06F12/0813 , G06F13/28 , H04L49/103 , H04L49/3009 , H04L49/90 , H04L49/9063 , H04L49/9073
摘要： An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

7. 发明授权

US06912602B2 System having two or more packet interfaces, a switch, and a shared packet DMA circuit 有权
标题翻译：具有两个或多个分组接口的系统，交换机和共享分组DMA电路
公开(公告)号：US06912602B2
公开(公告)日：2005-06-28
申请号：US10269666
申请日：2002-10-11
申请人： Barton J. Sano , Koray Oner , Laurent R. Moll , Manu Gulati
发明人： Barton J. Sano , Koray Oner , Laurent R. Moll , Manu Gulati
IPC分类号： G06F13/28 , H04L12/56
CPC分类号： H04L49/10 , H04L49/602
摘要： An apparatus includes a first interface circuit, a second interface circuit, a memory controller for configured to interface to a memory, and a packet DMA circuit. The first interface circuit is configured to couple to a first interface for receiving and transmitting packet data. Similarly, the second interface circuit is configured to couple to a second interface for receiving and transmitting packet data. The packet DMA circuit is coupled to receive a first packet from the first interface circuit and a second packet from the second interface circuit. The packet DMA circuit is configured to transmit the first packet and the second packet in write commands to the memory controller to be written to the memory. In some embodiments, a switch is coupled to the first interface circuit, the second interface circuit, and the packet DMA circuit.
摘要翻译：一种装置包括第一接口电路，第二接口电路，用于配置为与存储器接口的存储器控制器和分组DMA电路。第一接口电路被配置为耦合到用于接收和发送分组数据的第一接口。类似地，第二接口电路被配置为耦合到用于接收和发送分组数据的第二接口。分组DMA电路被耦合以从第一接口电路接收第一分组，并从第二接口电路接收第二分组。分组DMA电路被配置为以写入命令将第一分组和第二分组发送到存储器控制器以写入存储器。在一些实施例中，开关耦合到第一接口电路，第二接口电路和分组DMA电路。

8. 发明授权

US07424561B2 Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems 失效
标题翻译：使用分组，相干和非相干流量混合的系统来优化系统之间的传输
公开(公告)号：US07424561B2
公开(公告)日：2008-09-09
申请号：US11717511
申请日：2007-03-13
申请人： Barton J. Sano , Joseph B. Rowlands , Laurent R. Moll , Manu Gulati
发明人： Barton J. Sano , Joseph B. Rowlands , Laurent R. Moll , Manu Gulati
IPC分类号： G06F13/42 , G06F13/14 , G06F13/36 , G06F12/00
CPC分类号： G06F13/4022
摘要： An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second plurality of interface circuits, and each of the second plurality of interface circuits is configured to couple to a separate interface. A first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface. Both the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.
摘要翻译：装置可以包括第一系统和第二系统。第一系统包括第一多个接口电路，并且第一多个接口电路中的每一个配置成耦合到单独的接口。第二系统包括第二多个接口电路，并且第二多个接口电路中的每一个被配置为耦合到单独的接口。第一多个接口电路的第一接口电路和第二多个接口电路的第二接口电路耦合到第一接口。第一接口电路和第二接口电路均被配置为在第一接口上传送分组，相关命令和非相干命令。

9. 发明授权

US07227870B2 Systems including packet interfaces, switches, and packet DMA circuits for splitting and merging packet streams 有权
标题翻译：包括用于分组和合并分组流的分组接口，交换机和分组DMA电路的系统
公开(公告)号：US07227870B2
公开(公告)日：2007-06-05
申请号：US10270016
申请日：2002-10-11
申请人： Barton J. Sano , Laurent R. Moll , Manu Gulati
发明人： Barton J. Sano , Laurent R. Moll , Manu Gulati
IPC分类号： H04L12/56
CPC分类号： H04L47/40
摘要： An integrated circuit includes receive circuits for receiving packets, transmit circuits for transmitting packets, a packet DMA circuit for communicating packets to and from a memory controller, and a switch for selectively coupling the receive circuits to transmit circuits. The integrated circuit may flexibly merge and split the packet streams to provide for various packet processing/packet routing functions to be applied to different packets within the packet streams. An apparatus may include two or more of the integrated circuits, which may communicate packets between respective receive and transmit circuits.
摘要翻译：集成电路包括用于接收分组的接收电路，用于发送分组的发送电路，用于向存储器控制器传送分组的分组DMA电路和用于选择性地将接收电路耦合到发送电路的开关。集成电路可以灵活地合并和拆分分组流，以提供要应用于分组流内的不同分组的各种分组处理/分组路由功能。装置可以包括两个或更多个集成电路，其可以在相应的接收和发送电路之间传送分组。

10. 发明授权

US07206879B2 Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems 有权
标题翻译：使用分组，相干和非相干流量混合的系统来优化系统之间的传输
公开(公告)号：US07206879B2
公开(公告)日：2007-04-17
申请号：US10269922
申请日：2002-10-11
申请人： Barton J. Sano , Joseph B. Rowlands , Laurent R. Moll , Manu Gulati
发明人： Barton J. Sano , Joseph B. Rowlands , Laurent R. Moll , Manu Gulati
IPC分类号： G06F13/42 , G06F13/14 , G06F13/36 , G06F12/00
CPC分类号： G06F13/4022
摘要： An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second plurality of interface circuits, and each of the second plurality of interface circuits is configured to couple to a separate interface. A first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface. Both the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.
摘要翻译：装置可以包括第一系统和第二系统。第一系统包括第一多个接口电路，并且第一多个接口电路中的每一个被配置为耦合到单独的接口。第二系统包括第二多个接口电路，并且第二多个接口电路中的每一个被配置为耦合到单独的接口。第一多个接口电路的第一接口电路和第二多个接口电路的第二接口电路耦合到第一接口。第一接口电路和第二接口电路均被配置为在第一接口上传送分组，相关命令和非相干命令。

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