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1. 发明授权

US6023737A Multi-stage pipelined data coalescing for improved frequency operation 失效
标题翻译：多级流水线数据合并，提高频率运行
公开(公告)号：US6023737A
公开(公告)日：2000-02-08
申请号：US66014
申请日：1998-04-24
申请人： Thomas Albert Petersen , James Nolan Hardage, Jr.
发明人： Thomas Albert Petersen , James Nolan Hardage, Jr.
IPC分类号： G06F12/08 , G06F12/04 , G06F13/36 , G06F13/00
CPC分类号： G06F13/36
摘要： To implement full gathering of data transfers from a processor to a system bus without adding many levels of logic to the write enable logic for transaction queue entries or reducing the processor operating frequency, gatherable combinations are divided and gathering is performed in multiple stages operating in parallel. During the first stage, a subset of the full gathering is performed between incoming transactions and the last transaction received, coalescing the two transfers into a single transaction entry if one of the possible combinations within the subset is satisfied. During the second stage, existing queue entries are tested for the remainder of the full gather combination set and merged if a combination within the remaining subset is satisfied. The gathering logic may thus be split between the write enable logic and the entry control logic for the transaction queue, reducing the depth of logic required for any one path and increasing the set size of gatherable combinations implemented and/or the processor operating frequency. Any additional processor cycles required to complete full gathering are typically hidden by bus latency.
摘要翻译：为了实现从处理器到系统总线的数据传输的全面收集，而不会为事务队列条目的写使能逻辑增加许多级别的逻辑，或降低处理器的工作频率，可收集的组合被分割并且以并行运行的多个阶段进行采集。在第一阶段期间，在传入事务和所接收的最后事务之间执行完整收集的子集，如果满足子集内的可能组合之一，则将两个传输合并成单个事务条目。在第二阶段期间，如果剩余子集中的组合得到满足，则现有队列条目将针对完整集合组合集合的其余部分进行测试并合并。因此，采集逻辑可以在写入使能逻辑和用于事务队列的条目控制逻辑之间分开，从而减少任何一个路径所需的逻辑深度并增加实现的可收集组合和/或处理器工作频率的集合大小。总线延迟通常隐藏完成完全采集所需的任何其他处理器周期。

2. 发明授权

US06408361B1 Autonomous way specific tag update 失效
标题翻译：自动方式特定标签更新
公开(公告)号：US06408361B1
公开(公告)日：2002-06-18
申请号：US09389446
申请日：1999-09-02
申请人： Thomas Albert Petersen , James Nolan Hardage, Jr. , Scott Ives Remington
发明人： Thomas Albert Petersen , James Nolan Hardage, Jr. , Scott Ives Remington
IPC分类号： G06F1200
CPC分类号： G06F12/0846 , G06F12/0831 , G06F12/0864
摘要： The present invention provides a method and apparatus for allowing autonomous, way specific tag updates. More specifically, the invention provides way specific tag and status updates while concurrently allowing reads of the ways not currently being updated. If a read hit is determined, then the read is processed in a typical fashion. However, if the read is a read miss and one of the ways is flagged as being updated, then all ways are read again once the specific way has completed its updated.
摘要翻译：本发明提供一种用于允许自主的，特定方式的标签更新的方法和装置。更具体地，本发明提供方式特定的标签和状态更新，同时允许读取当前不被更新的方式。如果确定了读命中，则以典型的方式处理读取。但是，如果读取是未命中，并且其中一种方式被标记为更新，则一旦特定方式完成更新，就会再次读取所有方法。

3. 发明授权

US06269360B1 Optimization of ordered stores on a pipelined bus via self-initiated retry 失效
标题翻译：通过自发重试优化流水线总线上的有序存储
公开(公告)号：US06269360B1
公开(公告)日：2001-07-31
申请号：US09066012
申请日：1998-04-24
申请人： Thomas Albert Petersen , James Nolan Hardage, Jr.
发明人： Thomas Albert Petersen , James Nolan Hardage, Jr.
IPC分类号： G06F1730
CPC分类号： G06F13/161 , Y10S707/99932
摘要： Where a plurality of ordered transactions are received for data transfers on a pipelined bus, each transaction in the series is initiated before all prospective retry responses to the preceding ordered transactions may be asserted. The address responses to all preceding ordered transfers are then monitored in connection with performance of the newly initiated transfer. If a retry response to any preceding ordered transaction is asserted, a self-initiated retry response for all subsequent transactions, including the newly initiated transfer, is also asserted. The system-retried transactions and all succeeding, ordered transactions are immediately reattempted. The overlapping performance of the ordered transfers reduces the latency of non-retried transfers, achieving performance comparable to non-ordered transactions. Even where a retry response is asserted, the total latency required for completion of both transactions in the ordered pair is reduced by at least a portion of the address-to-response latency, so that the impact of ordering requirements on system performance is minimized. Strict ordering is thus enforced while taking full advantage of the pipelined nature of the bus to maximize utilization of the bus bandwidth.
摘要翻译：在对流水线总线上的数据传输接收到多个有序事务的情况下，系列中的每个事务在所有对先前有序事务的预期重试响应可能被断言之前启动。然后，与新发起的传输的性能相关联地监视对所有先前有序传输的地址响应。如果对任何先前有序事务的重试响应被断言，则还会断言所有后续事务的自发起的重试响应，包括新发起的传输。系统重试的交易和所有后续的有序交易立即被重新尝试。有序传输的重叠性能降低了非重试传输的延迟，实现与非有序事务相当的性能。即使在重试响应被断言的情况下，完成有序对中的两个事务所需的总延迟也减少了地址到响应延迟的至少一部分，从而将排序要求对系统性能的影响降到最低。因此，在充分利用总线的流水线特性的同时强制执行严格排序，以最大限度地利用总线带宽。

4. 发明授权

US06256713B1 Bus optimization with read/write coherence including ordering responsive to collisions 失效
标题翻译：具有读/写一致性的总线优化，包括响应于冲突的顺序
公开(公告)号：US06256713B1
公开(公告)日：2001-07-03
申请号：US09303365
申请日：1999-04-29
申请人： Srinath Audityan , James Nolan Hardage, Jr. , Thomas Albert Petersen
发明人： Srinath Audityan , James Nolan Hardage, Jr. , Thomas Albert Petersen
IPC分类号： G06F1200
CPC分类号： G06F13/18 , G06F12/0831
摘要： The present invention provides a method and apparatus for optimizing bus utilization while maintaining read and write coherence. More specifically the invention provides bus utilization optimization by prioritizing read transactions before write transactions, where there is no collision pending. When a collision pending is determined, then the read and write transactions are processed according to the age of the transaction(s) allowing for data coherency.
摘要翻译：本发明提供了一种在保持读写一致性的同时优化总线利用的方法和装置。更具体地，本发明通过在写入事务之前对读取事务进行优先级来提供总线利用率优化，其中没有冲突挂起。当确定冲突挂起时，则根据允许数据一致性的事务的年龄来处理读和写事务。

5. 发明授权

US06119204A Data processing system and method for maintaining translation lookaside buffer TLB coherency without enforcing complete instruction serialization 失效
标题翻译：用于保持翻译后备缓冲器TLB一致性的数据处理系统和方法，而不强制执行完整的指令串行化
公开(公告)号：US06119204A
公开(公告)日：2000-09-12
申请号：US108157
申请日：1998-06-30
申请人： Joseph Yih Chang , James Nolan Hardage, Jr. , Jose Melanio Nunez , Thomas Albert Petersen
发明人： Joseph Yih Chang , James Nolan Hardage, Jr. , Jose Melanio Nunez , Thomas Albert Petersen
IPC分类号： G06F12/10 , G06F13/14 , G06F12/08
CPC分类号： G06F12/1027 , G06F2212/682
摘要： A data processing system includes at least a first processor and a second processor that each have a respective translation lookaside buffer (TLB). In response to detection by the second processor of a TLB entry invalidation request, the second processor marks at least one memory referent instruction that is being processed by the second processor and invalidates a TLB entry in the TLB of the second processor. In response to receipt of a synchronization request at the second processor, the second processor indicates to the first processor that the second processor has invalidated the TLB entry if the second processor has completed processing the marked instruction. During the interval between receipt of the synchronization request and indicating to the first processor that the second processor has invalidated the TLB entry, the second processor continues to process instructions, including fetching instructions for processing. In this manner, the second processor is able to continue normal instruction processing during the process of TLB synchronization.
摘要翻译：数据处理系统至少包括第一处理器和第二处理器，每个具有相应的翻译后备缓冲器（TLB）。响应于第二处理器检测到TLB条目无效请求，第二处理器标记正在由第二处理器处理的至少一个存储器指示指令，并使第二处理器的TLB中的TLB条目无效。响应于在第二处理器处接收到同步请求，第二处理器向第一处理器指示如果第二处理器已经完成处理标记的指令，则第二处理器使TLB条目无效。在接收到同步请求和向第一处理器指示第二处理器使TLB条目无效的间隔期间，第二处理器继续处理指令，包括取指令进行处理。以这种方式，第二处理器能够在TLB同步的处理期间继续正常的指令处理。

6. 发明授权

US06449738B1 Apparatus for bus frequency independent wrap I/O testing and method therefor 失效
标题翻译：用于总线频率独立包装I / O测试的装置及其方法
公开(公告)号：US06449738B1
公开(公告)日：2002-09-10
申请号：US09204923
申请日：1998-12-03
申请人： Fahd Hinedi , James Nolan Hardage, Jr. , Lakshmikant Mamileti
发明人： Fahd Hinedi , James Nolan Hardage, Jr. , Lakshmikant Mamileti
IPC分类号： G01R3128
CPC分类号： G06F11/2221
摘要： A bus-clock-speed-independent apparatus and method of wrap input/output (I/O) testing of an I/O interface is provided. Launch data is launched in response to a launch clock. A capture clock is derived from the launch clock by delaying the launch clock through a programmable delay. Launch data is wrapped through the I/O interface buffers and captured in response to the capture clock. A initial value of the programmable delay is selected and successively increased or decreased until the launch data is just captured, or just fails to be captured, respectively. The value of the programmable delay when this occurs provides a measure of the limiting speed of the I/O interface.
摘要翻译：提供了一种总线时钟速度独立设备和一种I / O接口的输入/输出（I / O）测试方法。启动数据是响应发射时钟启动的。捕获时钟通过延迟启动时钟通过可编程延迟从启动时钟导出。启动数据通过I / O接口缓冲区进行包装，并根据捕获时钟进行捕获。选择可编程延迟的初始值并连续增加或减少，直到发射数据刚被捕获，或者仅仅不能被捕获。当这种情况发生时，可编程延迟的值提供了I / O接口极限速度的测量。

7. 发明授权

US06636980B1 System for launching data on a bus by using first clock for alternately selecting data from two data streams and using second clock for launching data thereafter 失效
标题翻译：用于通过使用第一时钟用于从两个数据流交替地选择数据并且之后使用第二时钟启动数据来在总线上启动数据的系统
公开(公告)号：US06636980B1
公开(公告)日：2003-10-21
申请号：US09377632
申请日：1999-08-19
申请人： Gilles Gervais , David George Caffo , James Nolan Hardage, Jr. , Stephen Douglas Weitzel
发明人： Gilles Gervais , David George Caffo , James Nolan Hardage, Jr. , Stephen Douglas Weitzel
IPC分类号： G06F106
CPC分类号： G06F13/4243
摘要： A bus interface apparatus and method are implemented. A pair of data streams is generated from the stream of data to be launched onto a data bus. Each stream is staged along a corresponding data path that includes a plurality of storage elements. Each path feeds an input of a multiplexer (MUX). The output of the MUX drives the bus, and the MUX selects a data value for launching onto the bus in response to a signal derived from an internal bus clock. The internal bus clock is also used to generate a bus clock that is output to the bus along with the data. The period of the bus clock may be a preselected multiple of the period of a processor clock. The data is staged along the two data streams in response to clocking signals derived from the processor clock. Each of the clocking signals is qualified by a corresponding hold signal, that, when asserted, holds the clocking signals in a predetermined state. The hold signals are generated in response to a plurality of control signals that are used to select the ratio of bus clock period to processor clock period. The bus interface may be asynchronously started in response to a signal from the startup logic in the central processing unit (CPU).
摘要翻译：实现总线接口装置和方法。从要发送到数据总线上的数据流生成一对数据流。每个流沿着包括多个存储元件的对应数据路径进行分级。每个路径馈送多路复用器（MUX）的输入。 MUX的输出驱动总线，并且MUX响应于从内部总线时钟导出的信号，选择用于发送到总线上的数据值。内部总线时钟也用于生成与数据一起输出到总线的总线时钟。总线时钟的周期可以是处理器时钟周期的预选倍数。响应于从处理器时钟导出的时钟信号，数据沿着两个数据流分段。每个时钟信号由相应的保持信号限定，当被断言时，将时钟信号保持在预定状态。响应于用于选择总线时钟周期与处理器时钟周期的比率的多个控制信号而产生保持信号。响应于来自中央处理单元（CPU）中的启动逻辑的信号，总线接口可以异步启动。

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