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1. 发明授权

US07366092B2 Hash and route hardware with parallel routing scheme 失效
标题翻译：哈希和路由硬件并行路由方案
公开(公告)号：US07366092B2
公开(公告)日：2008-04-29
申请号：US10684871
申请日：2003-10-14
申请人： Laurent Moll , Barton J. Sano , Thomas Albert Petersen
发明人： Laurent Moll , Barton J. Sano , Thomas Albert Petersen
IPC分类号： H04J1/16 , H04L12/28
CPC分类号： H04L45/60 , H04L45/00 , H04L45/54 , H04L45/745 , H04L49/109
摘要： A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a parallel routing scheme for calculating routing information for incoming packets. Using the programmable hash and route routing scheme, a hash and route circuit can be programmed for a variety of applications, such as routing, flow-splitting or load balancing.
摘要翻译：结合用于计算输入分组的路由信息的并行路由方案来描述基本上在单个CMOS集成电路上实现的多处理器交换设备。使用可编程散列和路由路由方案，哈希和路由电路可以针对各种应用进行编程，例如路由，流分解或负载平衡。

2. 发明申请

US20080198867A1 Hash and Route Hardware with Parallel Routing Scheme 审中-公开
标题翻译：并行路由方案的哈希和路由硬件
公开(公告)号：US20080198867A1
公开(公告)日：2008-08-21
申请号：US12109459
申请日：2008-04-25
申请人： Laurent Moll , Barton J. Sano , Thomas Albert Petersen
发明人： Laurent Moll , Barton J. Sano , Thomas Albert Petersen
IPC分类号： H04L12/56
CPC分类号： H04L45/60 , H04L45/00 , H04L45/54 , H04L45/745 , H04L49/109
摘要： A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a parallel routing scheme for calculating routing information for incoming packets. Using the programmable hash and route routing scheme, a hash and route circuit can be programmed for a variety of applications, such as routing, flow-splitting or load balancing.
摘要翻译：结合用于计算输入分组的路由信息的并行路由方案来描述基本上在单个CMOS集成电路上实现的多处理器交换设备。使用可编程散列和路由路由方案，哈希和路由电路可以针对各种应用进行编程，例如路由，流分解或负载平衡。

3. 发明授权

US06898675B1 Data received before coherency window for a snoopy bus 失效
标题翻译：在Snoopy总线的一致性窗口之前收到的数据
公开(公告)号：US06898675B1
公开(公告)日：2005-05-24
申请号：US09138380
申请日：1998-08-24
申请人： Alexander Edward Okpisz , Thomas Albert Petersen
发明人： Alexander Edward Okpisz , Thomas Albert Petersen
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0831
摘要： Where a null response can be expected from devices snooping a load operation, data may be used by a requesting processor prior to the coherency response window. A null snoop response may be determined, for example, from the availability of the data without a bus transaction. The capability of accelerating data in this fashion requires only a few simple changes in processor state transitions, required to permit entry of the data completion wait state prior to the response wait state. Processors may forward accelerated data to execution units with the expectation that a null snoop response will be received during the coherency response window. If a non-null snoop response is received, an error condition is asserted. Data acceleration of the type described allows critical data to get back to the processor without waiting for the coherency response window.
摘要翻译：在设备侦听加载操作时可以期望空响应的情况下，请求处理器可以在相干性响应窗口之前使用数据。可以例如从没有总线事务的数据的可用性来确定空窥探响应。以这种方式加速数据的能力仅需要处理器状态转换的几个简单的改变，这是允许在响应等待状态之前输入数据完成等待状态所需要的。处理器可以将加速数据转发到执行单元，期望在一致性响应窗口期间将接收到空窥探响应。如果接收到非空窥探响应，则会发出错误条件。所描述类型的数据加速允许关键数据回到处理器，而不必等待一致性响应窗口。

4. 发明授权

US06317806B1 Static queue and index queue for storing values identifying static queue locations 失效
标题翻译：静态队列和索引队列，用于存储识别静态队列位置的值
公开(公告)号：US06317806B1
公开(公告)日：2001-11-13
申请号：US09315612
申请日：1999-05-20
申请人： Srinath Audityan , Thomas Albert Petersen , Robert Charles Podnar
发明人： Srinath Audityan , Thomas Albert Petersen , Robert Charles Podnar
IPC分类号： G06F1200
CPC分类号： G06F5/06 , G06F12/0855 , Y02D10/13
摘要： A queuing apparatus associated with a processor includes at least one static queue (11), an index generator (34), at least one index queue (37), and a static queue accessing arrangement. Each static queue (11) has a number of static queue locations (12), each for storing a static queue entry and an availability indicator (14) for indicating an availability status of the respective static queue location. The index generator (34) uses information from the static queue (11) to provide a unique index value for each static queue entry, the index value for a particular static queue entry identifying the static queue location (12) containing the particular static queue entry. Each index queue (37, 42) has a number of index queue locations (40), each for storing one of the index values provided by the index generator (34). The static queue accessing arrangement retrieves a selected index value from a particular index queue location (40), and uses the selected index value to retrieve the static queue entry with which the selected index value is associated. Multiple index queues (37, 42) facilitate prioritization of static queue entries, and reprioritization by transferring index queue values from one index queue to another. The index queues (37, 42) also facilitate compaction of unnecessary static queue entries.
摘要翻译：与处理器相关联的排队设备包括至少一个静态队列（11），索引生成器（34），至少一个索引队列（37）和静态队列访问布置。每个静态队列（11）具有多个静态队列位置（12），每个静态队列位置（12）用于存储静态队列条目和用于指示相应静态队列位置的可用性状态的可用性指示符（14）。索引生成器（34）使用来自静态队列（11）的信息为每个静态队列条目提供唯一的索引值，特定静态队列条目的索引值标识包含特定静态队列条目的静态队列位置（12）。每个索引队列（37,42）具有多个索引队列位置（40），每个索引队列位置（40）用于存储由索引生成器（34）提供的索引值之一。静态队列访问安排从特定索引队列位置（40）检索所选择的索引值，并使用所选择的索引值来检索与所选择的索引值相关联的静态队列条目。多个索引队列（37,42）有助于静态队列条目的优先化，并通过将索引队列值从一个索引队列传递到另一个索引队列来重新确定优先级。索引队列（37,42）还有助于压缩不必要的静态队列条目。

5. 发明授权

US06256713B1 Bus optimization with read/write coherence including ordering responsive to collisions 失效
标题翻译：具有读/写一致性的总线优化，包括响应于冲突的顺序
公开(公告)号：US06256713B1
公开(公告)日：2001-07-03
申请号：US09303365
申请日：1999-04-29
申请人： Srinath Audityan , James Nolan Hardage, Jr. , Thomas Albert Petersen
发明人： Srinath Audityan , James Nolan Hardage, Jr. , Thomas Albert Petersen
IPC分类号： G06F1200
CPC分类号： G06F13/18 , G06F12/0831
摘要： The present invention provides a method and apparatus for optimizing bus utilization while maintaining read and write coherence. More specifically the invention provides bus utilization optimization by prioritizing read transactions before write transactions, where there is no collision pending. When a collision pending is determined, then the read and write transactions are processed according to the age of the transaction(s) allowing for data coherency.
摘要翻译：本发明提供了一种在保持读写一致性的同时优化总线利用的方法和装置。更具体地，本发明通过在写入事务之前对读取事务进行优先级来提供总线利用率优化，其中没有冲突挂起。当确定冲突挂起时，则根据允许数据一致性的事务的年龄来处理读和写事务。

6. 发明授权

US06615323B1 Optimizing pipelined snoop processing 有权
标题翻译：优化流水线窥探处理
公开(公告)号：US06615323B1
公开(公告)日：2003-09-02
申请号：US09389445
申请日：1999-09-02
申请人： Thomas Albert Petersen , Jose Melanio Nunez , Marie Jeannette Sullivan
发明人： Thomas Albert Petersen , Jose Melanio Nunez , Marie Jeannette Sullivan
IPC分类号： G06F1342
CPC分类号： G06F12/0831
摘要： A system and method are provided for maintaining cache coherency in symmetric multiprocessor system by having logic for performing snoop queries separate from logic for performing snoop actions. This logic split permits increased throughput because pending snoop queries must no longer wait until snoop actions complete. Two state machines are disclosed: a pipeline state machine for snoop queries; and a snoop action state machine, for executing the split logic handling snoop requests.
摘要翻译：提供了一种用于通过具有用于执行窥探查询的逻辑与用于执行窥探动作的逻辑分离的逻辑来在对称多处理器系统中维持高速缓存一致性的系统和方法。此逻辑拆分允许增加吞吐量，因为未完成的侦听查询必须不再等待，直到窥探操作完成。公开了两种状态机：用于窥探查询的流水线状态机; 和窥探动作状态机，用于执行分离逻辑处理侦听请求。

7. 发明授权

US06460133B1 Queue resource tracking in a multiprocessor system 失效
标题翻译：多处理器系统中的队列资源跟踪
公开(公告)号：US06460133B1
公开(公告)日：2002-10-01
申请号：US09315488
申请日：1999-05-20
申请人： Jose Melanio Nunez , Thomas Albert Petersen
发明人： Jose Melanio Nunez , Thomas Albert Petersen
IPC分类号： G06F900
CPC分类号： G06F13/1642 , G06F9/3824 , G06F9/3836 , G06F12/0831
摘要： A multiprocessor computer system including a set of processors where each processor in the set includes an execution unit for issuing operations and a processor queue suitable for queuing previously issued and still pending operations. The multiprocessor further includes means for forwarding operations issued by the processor to the processor queue and to an operation block queue of a memory subsystem that is connected to the multiprocessor. The depth of (i.e., the number of entries in) the operation block queue matches the depth of the processor queue. The processor queue, when full, inhibits the processor from issuing additional operations. In this manner, an operation issued by the processor is guaranteed an available entry in the operation block queue of the memory subsystem thereby eliminating the need for operation retry circuitry and protocols such as handshaking. Preferably, each processor queue includes a processor load queue and a processor store queue and the operation block queue includes a load queue and a store queue. In this embodiment, the depth of each of the processor load and store queues matches the depth of the operation block load and store queues respectively. In the preferred embodiment, the operation block is comprised of a load miss block that includes the operation block load queue and a store miss block that includes the operation block store queue. Still further preferably, the operation block store queue includes a set of store queues corresponding to the set of processors and the operation block load queue includes a set of load queues corresponding to the set of processors. Each queue entry preferably includes state information indicative of the status of the corresponding entry.
摘要翻译：一种包括一组处理器的多处理器计算机系统，其中集合中的每个处理器包括用于发布操作的执行单元和适于排队先前发布和尚待处理的操作的处理器队列。多处理器还包括用于将由处理器发出的操作转发到处理器队列和连接到多处理器的存储器子系统的操作块队列的装置。操作块队列的深度（即条目数）与处理器队列的深度相匹配。处理器队列在满时禁止处理器发出其他操作。以这种方式，由处理器发出的操作保证在存储器子系统的操作块队列中的可用条目，从而消除对操作重试电路和协议（例如握手）的需要。优选地，每个处理器队列包括处理器负载队列和处理器存储队列，并且操作块队列包括加载队列和存储队列。在该实施例中，每个处理器加载和存储队列的深度分别与操作块加载和存储队列的深度匹配。在优选实施例中，操作块包括包括操作块加载队列的负载未命中块和包括操作块存储队列的存储错误块。更优选地，操作块存储队列包括与该组处理器对应的一组存储队列，并且操作块加载队列包括与该组处理器对应的一组加载队列。每个队列条目优选地包括指示对应条目的状态的状态信息。

8. 发明授权

US06415362B1 Method and system for write-through stores of varying sizes 失效
标题翻译：不同大小的直写存储器的方法和系统
公开(公告)号：US06415362B1
公开(公告)日：2002-07-02
申请号：US09303364
申请日：1999-04-29
申请人： James Nolan Hardage , Alexander Edward Okpisz , Thomas Albert Petersen
发明人： James Nolan Hardage , Alexander Edward Okpisz , Thomas Albert Petersen
IPC分类号： G06F1200
CPC分类号： G06F12/0811 , G06F12/0831 , G06F12/0886
摘要： A method and system for performing write-through store operations of valid data of varying sizes in a data processing system, where the data processing system includes multiple processors that are coupled to an interconnect through a memory hierarchy, where the memory hierarchy includes multiple levels of cache, where at least one lower level of cache of the multiple of levels of cache requires store operations of all valid data of at least a predetermined size. First, it is determined whether or not a write-through store operation is a cache hit in a higher level of cache of the multiple levels of cache. In response to a determination that cache hit has occurred in the higher level of cache, the write-through store operation is merged with data read from the higher level of cache to provide a merged write-through operation of all valid data of at least the predetermined size to a lower level of cache. The merged write-through operation is performed in the lower level of cache, such that write-through operations of varying sizes to a lower level of cache which requires write operations of all valid data of at least a predetermined size are performed with data merged from a higher level of cache.
摘要翻译：一种用于在数据处理系统中执行不同大小的有效数据的直写存储操作的方法和系统，其中所述数据处理系统包括通过存储器层级耦合到互连的多个处理器，其中所述存储器层级包括高速缓存，其中多个级别的高速缓存的至少一个较低级别的高速缓存需要至少预定大小的所有有效数据的存储操作。首先，确定直写存储操作是否是多级高速缓存的更高级别的高速缓存命中。响应于在较高级别的缓存中发生高速缓存命中的确定，直写存储操作与从较高级别的高速缓存读取的数据合并，以提供所有有效数据的合并直写操作，所述有效数据至少为预定大小到较低级别的缓存。在较低级别的缓存中执行合并的直写操作，使得对需要至少预定大小的所有有效数据的写操作的高速缓存的较低级别的写入操作执行，其中从更高级的缓存。

9. 发明授权

US06119204A Data processing system and method for maintaining translation lookaside buffer TLB coherency without enforcing complete instruction serialization 失效
标题翻译：用于保持翻译后备缓冲器TLB一致性的数据处理系统和方法，而不强制执行完整的指令串行化
公开(公告)号：US06119204A
公开(公告)日：2000-09-12
申请号：US108157
申请日：1998-06-30
申请人： Joseph Yih Chang , James Nolan Hardage, Jr. , Jose Melanio Nunez , Thomas Albert Petersen
发明人： Joseph Yih Chang , James Nolan Hardage, Jr. , Jose Melanio Nunez , Thomas Albert Petersen
IPC分类号： G06F12/10 , G06F13/14 , G06F12/08
CPC分类号： G06F12/1027 , G06F2212/682
摘要： A data processing system includes at least a first processor and a second processor that each have a respective translation lookaside buffer (TLB). In response to detection by the second processor of a TLB entry invalidation request, the second processor marks at least one memory referent instruction that is being processed by the second processor and invalidates a TLB entry in the TLB of the second processor. In response to receipt of a synchronization request at the second processor, the second processor indicates to the first processor that the second processor has invalidated the TLB entry if the second processor has completed processing the marked instruction. During the interval between receipt of the synchronization request and indicating to the first processor that the second processor has invalidated the TLB entry, the second processor continues to process instructions, including fetching instructions for processing. In this manner, the second processor is able to continue normal instruction processing during the process of TLB synchronization.
摘要翻译：数据处理系统至少包括第一处理器和第二处理器，每个具有相应的翻译后备缓冲器（TLB）。响应于第二处理器检测到TLB条目无效请求，第二处理器标记正在由第二处理器处理的至少一个存储器指示指令，并使第二处理器的TLB中的TLB条目无效。响应于在第二处理器处接收到同步请求，第二处理器向第一处理器指示如果第二处理器已经完成处理标记的指令，则第二处理器使TLB条目无效。在接收到同步请求和向第一处理器指示第二处理器使TLB条目无效的间隔期间，第二处理器继续处理指令，包括取指令进行处理。以这种方式，第二处理器能够在TLB同步的处理期间继续正常的指令处理。

10. 发明授权

US06272601B1 Critical word forwarding in a multiprocessor system 失效
标题翻译：多处理器系统中的关键字转发
公开(公告)号：US06272601B1
公开(公告)日：2001-08-07
申请号：US09315541
申请日：1999-05-20
申请人： Jose Melanio Nunez , Thomas Albert Petersen
发明人： Jose Melanio Nunez , Thomas Albert Petersen
IPC分类号： G06F1208
CPC分类号： G06F12/0859 , G06F12/0811 , G06F12/0831
摘要： A multiprocessor computer system including a multiprocessor device preferably comprised of a set of processors, each including a respective L1 cache. The multiprocessor is preferably fabricated as a single device. The computer system includes a memory subsystem comprised of a load miss block adapted for queuing a load operation issued by a first processor that misses in an L1 cache of the first processor and a store miss block adapted for queuing store type operations. An arbiter of the memory subsystem is configured to receive queued operations from the load and store miss blocks and further configured to select and initiate one of the received operations. The subsystem further includes means for forwarding the address associated with the load miss operation to a lower level cache and means for receiving a hit/miss response from the lower level cache. In the preferred embodiment, the load miss block is adapted to detect the response from lower level cache and to request a bus interface unit to fetch data via a system bus if the lower level cache responds with a miss. The bus interface unit is configured to signal the load miss block when a first portion of the fetched data is available. In response thereto, the load miss block is configured to initiate a forwarding operation that returns the first potion of the data to the requesting processor if the forwarding operation can be initiated without displacing a valid load miss operation. The store and load miss block preferably each include separate store miss queues for each processor of the multiprocessor. The bus interface unit is preferably further configured to signal the load miss block when the entire granule (i.e., cache line) of requested data is available. The forwarding operation is preferably initiated if a first stage of a load miss block pipeline is invalid at some point after the first portion data is available, but before the entire requested data is available.
摘要翻译：一种多处理器计算机系统，包括优选地由一组处理器组成的多处理器设备，每个处理器包括相应的L1高速缓存。多处理器优选地被制造为单个设备。该计算机系统包括一个存储器子系统，该存储器子系统包括一个适用于对第一处理器发出的加载操作进行排队的负载丢失块，该第一处理器在第一处理器的L1高速缓存中丢失，以及适于排队存储类型操作的存储错误块。存储器子系统的仲裁器被配置为从加载和存储未命中的块接收排队的操作，并进一步被配置为选择并启动所接收的操作之一。子系统还包括用于将与加载未命中操作相关联的地址转发到较低级高速缓存的装置，以及用于从下级高速缓存接收命中/未命中响应的装置。在优选实施例中，如果下级高速缓存响应错误，则负载错误块适于检测来自较低级别高速缓存的响应，并请求总线接口单元经由系统总线提取数据。总线接口单元被配置为当获取的数据的第一部分可用时发信号通知加载未命中块。响应于此，负载丢失块被配置为启动转发操作，其将数据的第一部分返回到请求处理器，如果可以启动转发操作而不移动有效的加载未命中操作。存储和加载丢失块优选地每个包括用于多处理器的每个处理器的单独的存储缺失队列。总线接口单元优选地还被配置为当所请求的数据的整个颗粒（即，高速缓存行）可用时发信号通知加载未命中块。如果在第一部分数据可用之后但在整个所请求的数据可用之前的某个时刻，如果加载未命中流水线的第一级无效，则转发操作优选地被启动。

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