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1. 发明授权

US5112771A Method of fibricating a semiconductor device having a trench 失效
标题翻译：具有TRENCH的半导体器件的制备方法
公开(公告)号：US5112771A
公开(公告)日：1992-05-12
申请号：US349737
申请日：1989-06-12
申请人： Tatsuya Ishii , Yoji Mashiko , Masao Nagatomo , Michihiro Yamada
发明人： Tatsuya Ishii , Yoji Mashiko , Masao Nagatomo , Michihiro Yamada
IPC分类号： H01L21/308 , H01L21/763 , H01L27/108 , H01L29/94 , H01L21/76
CPC分类号： H01L27/10829 , H01L21/3081 , H01L21/3086 , H01L21/763 , H01L29/945
摘要： A semiconductor device having a trench (30) comprises a semiconductor substrate (11), a plurality of elements (13) provided on the semiconductor substrate, a trench (30) provided between the elements and an insulating material (12) embedded in the trench for isolating the elements. The trench has its bottom portion region enlarged in both sides.The semiconductor device is manufactured by enlarging the bottom portion region of the trench by etching.
摘要翻译：具有沟槽（30）的半导体器件包括半导体衬底（11），设置在半导体衬底上的多个元件（13），设置在元件之间的沟槽（30）和嵌入沟槽中的绝缘材料（12）用于隔离元件。沟槽的底部区域在两侧均扩大。通过蚀刻扩大沟槽的底部区域来制造半导体器件。

2. 发明授权

US5882780A Elastic polyester fibers and stretchable fiber articles containing same 失效
标题翻译：弹性聚酯纤维和含有它的可拉伸纤维制品
公开(公告)号：US5882780A
公开(公告)日：1999-03-16
申请号：US888103
申请日：1997-07-03
申请人： Yasuo Yamamura , Mikio Tashiro , Yasuyuki Yamazaki , Takeshi Honjou , Nobuyuki Yamamoto , Michihiro Yamada
发明人： Yasuo Yamamura , Mikio Tashiro , Yasuyuki Yamazaki , Takeshi Honjou , Nobuyuki Yamamoto , Michihiro Yamada
IPC分类号： D01F6/86 , D01F6/92 , D21H13/24 , D03D15/08 , D01F6/84
CPC分类号： D01F6/86 , Y10T428/249933 , Y10T442/602 , Y10T442/689
摘要： Elastic polyester fibers having a high anti-cohesive property (separability) include (A) a polyester elastomer and (B) 0.2 to 10%, based on the weight of the elastomer, of an anti-cohesive agent including (a) at least one alkali metal salt of organic sulfonic acid of the formula: R.sup.1 --S0.sub.3 M, wherein R.sup.1 =C.sub.5-25 hydrocarbon group, M=alkali metal, and (b) at least one compound of the formulae (2)-(6): R.sup.2 --X.sub.p --CH.sub.2 CH.sub.2 OH (2), R.sup.3 --COO--CH.sub.2 CH(OH)CH.sub.2 OH (3), R.sup.4 --COO--(CH.sub.2 CH.sub.2 O).sub.m --H (4), R.sup.5 --O--(CH.sub.2 CH.sub.2 O).sub.n H (5) and R.sup.6 --CONHCH.sub.2 CH.sub.2 NHCO--R.sup.7 (6), wherein R.sup.2 -R.sup.7 =C.sub.5-25 hydrocarbon group, X=--CONY or ##STR1## group, p=0 or 1, m, n=5 to 50.
摘要翻译：具有高抗粘结性（分离性）的弹性聚酯纤维包括（A）聚酯弹性体和（B）基于弹性体重量的0.2至10％的抗粘连剂，其包括（a）至少一种其中R1 = C5-25烃基，M =碱金属，和（b）至少一种式（2） - （6）的化合物：R2- （2），R3-COO-CH2CH（OH）CH2OH（3），R4-COO-（CH2CH2O）mH（4），R5-O-（CH2CH2O）nH（5）和R6-CONHCH2CH2NHCO-R7 6），其中R 2 -R 7 = C5-25烃基，X = -CONY或基团，p = 0或1，m，n = 5至50。

3. 发明授权

US5208474A Input circuit of a semiconductor device 失效
标题翻译：半导体器件的输入电路
公开(公告)号：US5208474A
公开(公告)日：1993-05-04
申请号：US646544
申请日：1991-01-28
申请人： Tadato Yamagata , Hiroshi Miyamoto , Michihiro Yamada
发明人： Tadato Yamagata , Hiroshi Miyamoto , Michihiro Yamada
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L21/8242 , H01L27/02 , H01L27/06 , H01L27/088 , H01L27/10 , H01L27/108
CPC分类号： H01L27/0251
摘要： An input circuit of a semiconductor device includes a P type well formed on the main surface of a semiconductor substrate, and an N type region formed on the main surface in the P type well. A P-N junction is formed by the N type region and the P type well. An input voltage is applied to the N type region, which input voltage is applied to an internal circuit formed on the semiconductor substrate. When the P-N junction is rendered conductive by an application of an excessive voltage to the input voltage, the current caused by the excessive voltage is absorbed to the supply potential through the P type region formed in the P well.
摘要翻译：半导体器件的输入电路包括在半导体衬底的主表面上良好地形成的P型阱和形成在P型阱的主表面上的N型区域。由N型区域和P型阱形成P-N结。输入电压施加到N型区域，该输入电压被施加到形成在半导体衬底上的内部电路。当通过对输入电压施加过大的电压使P-N结导通时，由过电压引起的电流通过形成在P阱中的P型区域吸收到电源电位。

4. 发明授权

US4803663A Semiconductor memory having divided bit lines and individual sense amplifiers 失效
标题翻译：具有划分位线和单独读出放大器的半导体存储器
公开(公告)号：US4803663A
公开(公告)日：1989-02-07
申请号：US27536
申请日：1987-03-18
申请人： Hiroshi Miyamoto , Michihiro Yamada
发明人： Hiroshi Miyamoto , Michihiro Yamada
IPC分类号： G11C11/401 , G11C11/4076 , G11C11/4091 , G11C11/4097 , G11C7/00 , G11C11/40 , H03K5/24
CPC分类号： G11C11/4091 , G11C11/4076 , G11C11/4097
摘要： A dynamic RAM having a plurality of pairs of folded bit lines each divided into a plurality of pairs of divided bit lines comprises transfer gates (QT1, QT2) provided for each pair of divided bit lines for connecting/disconnecting the pair of adjacent divided bit lines to each other, sense amplifiers (SA1, SA2) provided for each of the pairs of divided bit lines for detecting and amplifying potential difference between the pairs of divided bit lines, restore circuits (RE1, RE2) provided for each of the pairs of divided bit lines for boosting the potential on the bit line on the side of a high potential of the pairs of the divided bit lines, and a control circuit (TG) for turning the transfer gates (QT1, QT2) on after a predetermined time since the sense amplifier was operated in response to a sense amplifier activating signal.
摘要翻译：具有分成多对分割位线的多对折叠位线的动态RAM包括为每对分割位线提供的传输门（QT1，QT2），用于连接/断开该对相邻的分割位线为每个分割位线分别提供的读出放大器（SA1，SA2），用于检测和放大分配位线对之间的电位差，为每对分割位线提供的恢复电路（RE1，RE2）位线，用于升高分压位线对的高电位侧的位线上的电位;以及用于在从该位线开始的预定时间之后转动传输门（QT1，QT2）的控制电路（TG）感测放大器响应于读出放大器激活信号而被操作。

5. 发明授权

US5323348A Semiconductor memory device having multiple memory arrays and including redundancy circuit for repairing a faulty bit 失效
标题翻译：具有多个存储器阵列并且包括用于修复故障位的冗余电路的半导体存储器件
公开(公告)号：US5323348A
公开(公告)日：1994-06-21
申请号：US767316
申请日：1991-09-30
申请人： Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Mitsuya Kinoshita , Makoto Suwa , Shigeru Kikuda , Michihiro Yamada
发明人： Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Mitsuya Kinoshita , Makoto Suwa , Shigeru Kikuda , Michihiro Yamada
IPC分类号： G11C11/401 , G11C11/409 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/848
摘要： Column repairing circuits 7a, 7b for repairing a DRAM in which there are defective memory cells in two columns are disclosed. The connection state of switching elements or circuits 51-5n, 61-6n, 71-7 (n+1), 81-8 (n+1) is determined as illustrated by appropriately disconnecting fuses in fuse links provided respectively in circuits 7a, 7b. Accordingly, column selecting lines Y2a and Y (n+1) b in memory array blocks 891a, 891b are not activated. The two repairing circuits 7a, 7b are provided spaced apart from each other on a semiconductor substrate, so that excessive concentration of fuse elements and switching elements or circuits is prevented.
摘要翻译：公开了用于修复其中存在两列不良存储器单元的DRAM的列修复电路7a，7b。开关元件或电路51-5n，61-6n，71-7（n + 1），81-8（n + 1）的连接状态通过适当地断开分别设置在电路7a， 7b。因此，存储器阵列块891a，891b中的列选择线Y2a和Y（n + 1）b未被激活。两个修复电路7a，7b在半导体衬底上彼此间隔开设置，从而防止了熔丝元件和开关元件或电路的过度集中。

6. 发明授权

US5073874A Method of and apparatus for reducing current of semiconductor memory device 失效
标题翻译：减少半导体存储器件电流的方法和装置
公开(公告)号：US5073874A
公开(公告)日：1991-12-17
申请号：US417127
申请日：1989-10-04
申请人： Michihiro Yamada , Hiroshi Miyamoto
发明人： Michihiro Yamada , Hiroshi Miyamoto
IPC分类号： G11C11/407 , G11C11/4076
CPC分类号： G11C11/4076
摘要： A clock generator circuit of a dynamic RAM comprises a power-on reset circuit and an NOR gate connected to a RAS terminal and the reset circuit. In operation, the powre-on reset circuit generates a one-shot pulse immediately after the power supply is turned on. During a period of a pulse width of the one-shot pulse, this clock generator circuit operates as if it receives a high-level RAS signal and, as a result, it is possible to reduce an excessive current flowing into the dynamic RAM at the time of turning on the power supply.

7. 发明授权

US5019883A Input protective apparatus of semiconductor device 失效
标题翻译：半导体器件输入保护装置
公开(公告)号：US5019883A
公开(公告)日：1991-05-28
申请号：US443864
申请日：1989-11-30
申请人： Shigeru Mori , Michihiro Yamada , Hideshi Miyatake , Shuji Murakami
发明人： Shigeru Mori , Michihiro Yamada , Hideshi Miyatake , Shuji Murakami
IPC分类号： H01L29/78 , H01L21/8234 , H01L23/64 , H01L27/02 , H01L27/06 , H01L27/088 , H02H7/20
CPC分类号： H02H7/20 , H01L23/647 , H01L27/0251 , H01L2924/0002 , H01L2924/3011
摘要： An input protective apparatus for a semiconductor device (Q3) comprises an MOS transistor (Q4) having a thick gate insulating film formed therein. The MOS transistor (Q4) has one active layer connected to an input terminal (11) through a second resistor element (R2) and connected to a semiconductor device (Q3) to be protected through a first resistor element (R1), and an other active layer connected to a ground terminal. The input protective apparatus is adapted such that a resistance value R.sub.1 of a first resistor element (R1) and a resistance value R.sub.2 of the second resistor element (R2) satisfy the relation R.sub.1 >R.sub.2, and the on-resistance R.sub.3 of the MOS transistor (Q4) and the resistance value R.sub.2 satisfy the relation R.sub.3
摘要翻译：一种用于半导体器件（Q3）的输入保护装置包括其中形成有厚栅极绝缘膜的MOS晶体管（Q4）。 MOS晶体管（Q4）具有通过第二电阻元件（R2）连接到输入端子（11）并且连接到半导体器件（Q3）的一个有源层，以通过第一电阻元件（R1）被保护，另一个有源层连接到接地端子。输入保护装置适于使得第一电阻元件（R1）的电阻值R1和第二电阻元件（R2）的电阻值R2满足关系R1> R2，并且MOS晶体管的导通电阻R3 （Q4），电阻值R2满足R3 << R2的关系。

8. 发明授权

US4914326A Delay circuit 失效
标题翻译：延时电路
公开(公告)号：US4914326A
公开(公告)日：1990-04-03
申请号：US155541
申请日：1988-02-12
申请人： Shigeru Kikuda , Hiroshi Miyamoto , Michihiro Yamada
发明人： Shigeru Kikuda , Hiroshi Miyamoto , Michihiro Yamada
IPC分类号： H01L27/092 , H01L21/8238 , H03K5/00 , H03K5/04 , H03K5/13 , H03K19/0948
CPC分类号： H03K5/133 , H03K2005/00195
摘要： A delay circuit having a complementary insulated gate device comprises an inverter (10) having a series connection of a p type field effect transistor Q3 and an n type field effect transistor Q4 and a transmission gate (20) having a parallel connection of a p type field effect transistor Q1 and an n type field effect transistor Q2 connected to the preceding stage of the inverter (10), and the gates of the transistors Q1 and Q2 are connected together to an output terminal (3). The logical threshold voltage of the inverter (10) is set at a higher value in the range of the input voltage of the inverter (10). There is a peculiar period in which the transistors Q1 and Q2 of the transmission gate (20) transmit only a little increase of the input voltage to the inverter (10) during the increase of the input voltage. Due to the existence of this peculiar period, this circuit outputs a delayed output signal only when the input voltage increases. In addition, the rise time and fall time of the output signal are short.
摘要翻译：具有互补绝缘栅极器件的延迟电路包括具有ap型场效应晶体管Q3和n型场效应晶体管Q4的串联连接的反相器（10）和具有ap型场效应的并联连接的传输门（20）晶体管Q1和连接到反相器（10）的前级的n型场效应晶体管Q2，并且晶体管Q1和Q2的栅极连接到输出端子（3）。在逆变器（10）的输入电压的范围内，将逆变器（10）的逻辑门限电压设定为较高的值。在输入电压增加期间，传输门（20）的晶体管Q1和Q2仅传输到逆变器（10）的输入电压的一个特殊周期。由于存在这个特殊周期，该电路仅在输入电压增加时输出延迟的输出信号。另外，输出信号的上升时间和下降时间短。

9. 发明授权

US5481496A Semiconductor memory device and method of data transfer therefor 失效
标题翻译：半导体存储器件及其数据传输方法
公开(公告)号：US5481496A
公开(公告)日：1996-01-02
申请号：US236004
申请日：1994-05-02
申请人： Toshifumi Kobayashi , Yoshikazu Morooka , Michihiro Yamada , Takeshi Hamamoto
发明人： Toshifumi Kobayashi , Yoshikazu Morooka , Michihiro Yamada , Takeshi Hamamoto
IPC分类号： G11C7/06 , G11C7/10 , G11C7/12 , G11C7/00 , G11C8/00
CPC分类号： G11C7/065 , G11C7/1006 , G11C7/12
摘要： Sense amplifiers provided for each of the bit line pairs are divided into groups to be independently driven, whereby the influence of sense amplifiers of different groups can be prevented, and therefore the destruction of data of the non-selected memory cells during data transfer can be prevented. In transferring data from the data register to the memory cell array, the sense amplifier is not activated until the stored information of the memory cells selected by the word line is fully read to the corresponding bit lines, whereby the destruction of data stored in the non-selected memory cells can be prevented.
摘要翻译：为每个位线对提供的感测放大器被分成要被独立驱动的组，由此可以防止不同组的读出放大器的影响，因此数据传送期间未选择的存储器单元的数据的破坏可以是防止了在将数据从数据寄存器传送到存储单元阵列时，读出放大器不会被激活，直到由字线选择的存储单元的存储信息被完全读出到相应的位线为止，可以防止选择的存储单元。

10. 发明授权

US5053997A Dynamic random access memory with FET equalization of bit lines 失效
标题翻译：动态随机访问存储器，具有位线等效化
公开(公告)号：US5053997A
公开(公告)日：1991-10-01
申请号：US132646
申请日：1987-12-08
申请人： Hiroshi Miyamato , Michihiro Yamada
发明人： Hiroshi Miyamato , Michihiro Yamada
IPC分类号： G11C11/409 , G11C11/401 , G11C11/4076 , G11C11/4094 , G11C11/4096 , G11C11/4097 , G11C7/00 , G11C11/40
CPC分类号： G11C11/4097 , G11C11/4076 , G11C11/4094 , G11C11/4096
摘要： A dynamic random access memory with a folded bit line structure (BLL.sub.j1, BLL.sub.j1, BLR.sub.j1 BLR.sub.j1), each pair of bit lines being divided into a plurality of blocks (MCB.sub.j1, MCB.sub.j2), comprises equalizing transistors (Q.sub.j9, Q.sub.j10) each of which is provided for each pair of divided bit lines to equalize the pair of divided bit lines. The equalizing transistors (Q.sub.j9, Q.sub.j10) stop equalizing selectively and at different times among the blocks.

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