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1. 发明授权

US5063313A Delay circuit employing different threshold FET's 失效
标题翻译：延迟电路使用不同的阈值FET
公开(公告)号：US5063313A
公开(公告)日：1991-11-05
申请号：US459238
申请日：1989-12-29
申请人： Shigeru Kikuda , Hiroshi Miyamoto , Michihiro Yamada
发明人： Shigeru Kikuda , Hiroshi Miyamoto , Michihiro Yamada
IPC分类号： H01L27/092 , H01L21/8238 , H03K5/00 , H03K5/04 , H03K5/13 , H03K19/0948
CPC分类号： H03K5/133 , H03K2005/00195
摘要： A delay circuit having a complementary insulated gate device comprises an inverter (10) having a series connection of a p type field effect transistor Q3 and an n type field effect transistor Q4 and a transmission gate (20) having a parallel connection of a p type field effect transistor Q1 and an n type field effect transistor Q2 connected to the preceding stage of the inverter (10), and the gates of the transistors Q1 and Q2 are connected together to an output terminal (3). The logical threshold voltage of the inverter (10) is set at a higher value in the range of the input voltage of the inverter (10). There is a peculiar period in which the transistors Q1 and Q2 of the transmission gate (20) transmit only a litle increase of the input voltage to the inverter (10) during the increase of the input voltage. Due to the existence of this peculiar period, this circuit outputs a delayed output signal only when the input voltage increases. In addition, the rise time and fall time of the output signal are short.
摘要翻译：具有互补绝缘栅极器件的延迟电路包括具有ap型场效应晶体管Q3和n型场效应晶体管Q4的串联连接的反相器（10）和具有ap型场效应的并联连接的传输门（20）晶体管Q1和连接到反相器（10）的前级的n型场效应晶体管Q2，并且晶体管Q1和Q2的栅极连接到输出端子（3）。在逆变器（10）的输入电压的范围内，将逆变器（10）的逻辑门限电压设定为较高的值。在输入电压增加期间，传输门（20）的晶体管Q1和Q2仅传输到逆变器（10）的输入电压的一个特殊周期。由于存在这个特殊周期，该电路仅在输入电压增加时输出延迟的输出信号。另外，输出信号的上升时间和下降时间短。

2. 发明授权

US4984054A Electric fuse for a redundancy circuit 失效
标题翻译：电熔丝用于冗余电路
公开(公告)号：US4984054A
公开(公告)日：1991-01-08
申请号：US481683
申请日：1990-02-20
申请人： Michihiro Yamada , Hiroshi Miyamoto , Tadato Yamagata , Shigeru Mori
发明人： Michihiro Yamada , Hiroshi Miyamoto , Tadato Yamagata , Shigeru Mori
IPC分类号： H01L21/82 , H01H37/76 , H01L21/3205 , H01L23/525 , H01L27/10
CPC分类号： H01L23/5256 , H01L2924/0002
摘要： The present invention comprises a field oxide film formed on a silicon substrate, an underlying film of polycrystal silicon formed on a portion thereof and an insulating film formed so as to cover the field oxide film comprising the underlying film. A surface stepped portion of the insulating film is formed by a portion with an underlying film and a portion without an underlying film under the insulating film, and a blowout portion of a fuse is formed along the surface stepped portion. There are terminal portions at both ends of the blowout portion of the fuse and an aluminum line is connected thereto. In addition, the whole portions comprising the fuse portion are covered with another insulating film and the whole is protected. The fuse is employed as one example in a redundancy circuit of a MOS dynamic RAM having redundancy memory cells.
摘要翻译：本发明包括形成在硅衬底上的场氧化物膜，形成在其一部分上的多晶硅的下面的膜和形成为覆盖包括下面的膜的场氧化物膜的绝缘膜。绝缘膜的表面阶梯部分由具有下面的膜的部分和在绝缘膜下方没有下面的膜的部分形成，并且沿表面台阶形成熔丝的吹出部分。在保险丝的吹出部分的两端有端子部分，铝线连接到其上。此外，包括熔丝部分的整个部分被另一绝缘膜覆盖，并且整体被保护。在具有冗余存储单元的MOS动态RAM的冗余电路中采用熔丝作为一个例子。

3. 发明授权

US4933902A Method of and apparatus for reducing current of semiconductor memory device 失效
标题翻译：减少半导体存储器件电流的方法和装置
公开(公告)号：US4933902A
公开(公告)日：1990-06-12
申请号：US223693
申请日：1988-07-22
申请人： Michihiro Yamada , Hiroshi Miyamoto
发明人： Michihiro Yamada , Hiroshi Miyamoto
IPC分类号： G11C11/407 , G11C11/4076
CPC分类号： G11C11/4076
摘要： A clock generator circuit of a dynamic random access memory (RAM) comprises a power-on reset circuit and an NOR gate conneced to a row address strobe (RAS) terminal and the reset circuit. In operation, the power-on reset circuit generates a one-shot pulse immediately after the power supply is turned on. During a period of a pulse width of the one-shot pulse, this clock generator circuit operates as if it receives a high-level row address strobe (RAS) signal and, as a result, it is possible to reduce an excessive current flowing into the dynamic random access memory (RAM) at the time of turning on the power supply.
摘要翻译：动态随机存取存储器（RAM）的时钟发生器电路包括上电复位电路和与行地址选通（＆amp; R＆amp; R）端子和复位电路连接的NOR门。在操作中，上电复位电路在电源接通之后立即产生单触发脉冲。在单触发脉冲的脉冲宽度期间，该时钟发生器电路就像接收到高电平行地址选通（＆amp; R＆amp; R）信号一样工作，结果可以减少流过的电流在打开电源时进入动态随机存取存储器（RAM）。

4. 发明授权

US4931668A MIS transistor driven inverter circuit capable of individually controlling rising portion and falling portion of output waveform 失效
标题翻译：能够单独控制输出波形的上升部分和下降部分的MIS晶体管驱动的逆变器电路
公开(公告)号：US4931668A
公开(公告)日：1990-06-05
申请号：US143399
申请日：1988-01-13
申请人： Shigeru Kikuda , Michihiro Yamada , Hiroshi Miyamoto
发明人： Shigeru Kikuda , Michihiro Yamada , Hiroshi Miyamoto
IPC分类号： H03K4/94 , H03F1/52 , H03K5/01 , H03K5/12 , H03K17/04 , H03K17/08 , H03K19/003
CPC分类号： H03K5/01 , H03K19/00361
摘要： A resistor is connected to an input portion of a CMOS inverter. An input of the CMOS inverter is affected by a time constant of an RC circuit comprising the resistor and gate stray capacitance of the CMOS inverter. In addition, there is provided an n channel MOS transistor having a drain and a source connected to both ends of the resistor, respectively, and a gate connected to an input signal source. Only in the rising portion of an input signal, the n channel MOS transistor is turned on, so that the resistor is bypassed. Thus, a waveform of output of the CMOS inverter is not delayed at the falling portion. Only at the rising portion, the waveform thereof is delayed due to the time constant of the above described RC circuit.
摘要翻译：电阻器连接到CMOS反相器的输入部分。 CMOS反相器的输入受到包括CMOS反相器的电阻和栅杂散电容的RC电路的时间常数的影响。另外，提供了一个n沟道MOS晶体管，其漏极和源极分别连接到电阻器的两端，栅极连接到输入信号源。只有在输入信号的上升部分，n沟道MOS晶体管导通，使得电阻器被旁路。因此，CMOS反相器的输出波形在下降部分不延迟。仅在上升部分，由于上述RC电路的时间常数，其波形被延迟。

5. 发明授权

US4904885A Substrate bias circuit having substrate bias voltage clamp and operating method therefor 失效
标题翻译：具有衬底偏置电压钳的衬底偏置电路及其操作方法
公开(公告)号：US4904885A
公开(公告)日：1990-02-27
申请号：US204126
申请日：1988-06-06
申请人： Michihiro Yamada , Hiroshi Miyamoto , Tadato Yamagata , Shigeru Mori , Tetsuya Aono
发明人： Michihiro Yamada , Hiroshi Miyamoto , Tadato Yamagata , Shigeru Mori , Tetsuya Aono
IPC分类号： G11C11/407 , G05F3/20 , G11C11/4074 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , H03K19/094
CPC分类号： G11C11/4074 , G05F3/205
摘要： A substrate bias circuit controls application of a conventional substrate charge pump to the substrate of a semiconductor integrated circuit to prevent latching up of parasitic transistors at the time of turn on of power to the integrated circuit. The substrate bias circuit comprises a filed effect transistor having its source and drain electrodes connected between substrate and charge pump. The gate electrode of the transistor is driven through an RC circuit by the power supply to turn on the transistor for a predetermined time period at the time power is initially applied to the integrated circuit. There is no latching up of the parasitic transistors because application of positive bias voltage to the substrate during turn-on is prevented.
摘要翻译：衬底偏置电路控制将常规衬底电荷泵施加到半导体集成电路的衬底，以防止在集成电路接通电源时寄生晶体管的锁存。衬底偏置电路包括场效应晶体管，其源极和漏极连接在衬底和电荷泵之间。晶体管的栅极通过电源通过RC电路驱动，以在初始施加到集成电路的时间将晶体管导通预定时间段。寄生晶体管没有锁存，因为防止了在接通期间向衬底施加正偏置电压。

6. 发明授权

US4792927A Semiconductor memory device with bit line sense amplifiers 失效
标题翻译：具有位线读出放大器的半导体存储器件
公开(公告)号：US4792927A
公开(公告)日：1988-12-20
申请号：US20192
申请日：1987-02-26
申请人： Hiroshi Miyamoto , Michihiro Yamada
发明人： Hiroshi Miyamoto , Michihiro Yamada
IPC分类号： G11C11/401 , G11C11/4091 , G11C11/4097 , G11C7/00
CPC分类号： G11C11/4091 , G11C11/4097
摘要： In a dynamic random access memory with a folded bit line structure, in which a memory cell array is divided into a plurality of blocks (CAL1, CAL2) and the bit lines (BL1, BL1, BL2, BL2) of the adjacent blocks (CAL1, CAL2) are connected to each other by using transfer gate transistors (QT1, QT2), sense amplifiers (SA1, SA2) and restore circuits (RE1, RE2) for detecting potential difference between pair of bit lines are provided for each of the pairs of bit lines (BL1, BL1, BL2, BL2) of each of the blocks (CAL1, CAL2), the transfer gate transistors (QT1, QT2) to turned on by being triggered by an activating signal to a restore circuit first operated, out of restore circuits connected to bit lines connected to the transfer gate transistor (QT1, QT2).
摘要翻译：在具有折叠位线结构的动态随机存取存储器中，其中存储单元阵列被分成多个块（CAL1，CAL2）和相邻块（CAL1）的位线（BL1，BL1，BL2，BL2），CAL2）通过使用传输栅极晶体管（QT1，QT2），读出放大器（SA1，SA2）和用于检测位线对之间的电位差的恢复电路（RE1，RE2）彼此连接每个块（CAL1，CAL2）的位线（BL1，BL1，BL2，BL2），通过由初始操作的恢复电路的激活信号触发而导通的传输门晶体管（QT1，QT2）连接到连接到传输门晶体管（QT1，QT2）的位线的还原电路。

7. 发明授权

US5323348A Semiconductor memory device having multiple memory arrays and including redundancy circuit for repairing a faulty bit 失效
标题翻译：具有多个存储器阵列并且包括用于修复故障位的冗余电路的半导体存储器件
公开(公告)号：US5323348A
公开(公告)日：1994-06-21
申请号：US767316
申请日：1991-09-30
申请人： Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Mitsuya Kinoshita , Makoto Suwa , Shigeru Kikuda , Michihiro Yamada
发明人： Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Mitsuya Kinoshita , Makoto Suwa , Shigeru Kikuda , Michihiro Yamada
IPC分类号： G11C11/401 , G11C11/409 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/848
摘要： Column repairing circuits 7a, 7b for repairing a DRAM in which there are defective memory cells in two columns are disclosed. The connection state of switching elements or circuits 51-5n, 61-6n, 71-7 (n+1), 81-8 (n+1) is determined as illustrated by appropriately disconnecting fuses in fuse links provided respectively in circuits 7a, 7b. Accordingly, column selecting lines Y2a and Y (n+1) b in memory array blocks 891a, 891b are not activated. The two repairing circuits 7a, 7b are provided spaced apart from each other on a semiconductor substrate, so that excessive concentration of fuse elements and switching elements or circuits is prevented.
摘要翻译：公开了用于修复其中存在两列不良存储器单元的DRAM的列修复电路7a，7b。开关元件或电路51-5n，61-6n，71-7（n + 1），81-8（n + 1）的连接状态通过适当地断开分别设置在电路7a， 7b。因此，存储器阵列块891a，891b中的列选择线Y2a和Y（n + 1）b未被激活。两个修复电路7a，7b在半导体衬底上彼此间隔开设置，从而防止了熔丝元件和开关元件或电路的过度集中。

8. 发明授权

US5073874A Method of and apparatus for reducing current of semiconductor memory device 失效
标题翻译：减少半导体存储器件电流的方法和装置
公开(公告)号：US5073874A
公开(公告)日：1991-12-17
申请号：US417127
申请日：1989-10-04
申请人： Michihiro Yamada , Hiroshi Miyamoto
发明人： Michihiro Yamada , Hiroshi Miyamoto
IPC分类号： G11C11/407 , G11C11/4076
CPC分类号： G11C11/4076
摘要： A clock generator circuit of a dynamic RAM comprises a power-on reset circuit and an NOR gate connected to a RAS terminal and the reset circuit. In operation, the powre-on reset circuit generates a one-shot pulse immediately after the power supply is turned on. During a period of a pulse width of the one-shot pulse, this clock generator circuit operates as if it receives a high-level RAS signal and, as a result, it is possible to reduce an excessive current flowing into the dynamic RAM at the time of turning on the power supply.

9. 发明授权

US4914326A Delay circuit 失效
标题翻译：延时电路
公开(公告)号：US4914326A
公开(公告)日：1990-04-03
申请号：US155541
申请日：1988-02-12
申请人： Shigeru Kikuda , Hiroshi Miyamoto , Michihiro Yamada
发明人： Shigeru Kikuda , Hiroshi Miyamoto , Michihiro Yamada
IPC分类号： H01L27/092 , H01L21/8238 , H03K5/00 , H03K5/04 , H03K5/13 , H03K19/0948
CPC分类号： H03K5/133 , H03K2005/00195
摘要： A delay circuit having a complementary insulated gate device comprises an inverter (10) having a series connection of a p type field effect transistor Q3 and an n type field effect transistor Q4 and a transmission gate (20) having a parallel connection of a p type field effect transistor Q1 and an n type field effect transistor Q2 connected to the preceding stage of the inverter (10), and the gates of the transistors Q1 and Q2 are connected together to an output terminal (3). The logical threshold voltage of the inverter (10) is set at a higher value in the range of the input voltage of the inverter (10). There is a peculiar period in which the transistors Q1 and Q2 of the transmission gate (20) transmit only a little increase of the input voltage to the inverter (10) during the increase of the input voltage. Due to the existence of this peculiar period, this circuit outputs a delayed output signal only when the input voltage increases. In addition, the rise time and fall time of the output signal are short.
摘要翻译：具有互补绝缘栅极器件的延迟电路包括具有ap型场效应晶体管Q3和n型场效应晶体管Q4的串联连接的反相器（10）和具有ap型场效应的并联连接的传输门（20）晶体管Q1和连接到反相器（10）的前级的n型场效应晶体管Q2，并且晶体管Q1和Q2的栅极连接到输出端子（3）。在逆变器（10）的输入电压的范围内，将逆变器（10）的逻辑门限电压设定为较高的值。在输入电压增加期间，传输门（20）的晶体管Q1和Q2仅传输到逆变器（10）的输入电压的一个特殊周期。由于存在这个特殊周期，该电路仅在输入电压增加时输出延迟的输出信号。另外，输出信号的上升时间和下降时间短。

10. 发明授权

US5208474A Input circuit of a semiconductor device 失效
标题翻译：半导体器件的输入电路
公开(公告)号：US5208474A
公开(公告)日：1993-05-04
申请号：US646544
申请日：1991-01-28
申请人： Tadato Yamagata , Hiroshi Miyamoto , Michihiro Yamada
发明人： Tadato Yamagata , Hiroshi Miyamoto , Michihiro Yamada
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L21/8242 , H01L27/02 , H01L27/06 , H01L27/088 , H01L27/10 , H01L27/108
CPC分类号： H01L27/0251
摘要： An input circuit of a semiconductor device includes a P type well formed on the main surface of a semiconductor substrate, and an N type region formed on the main surface in the P type well. A P-N junction is formed by the N type region and the P type well. An input voltage is applied to the N type region, which input voltage is applied to an internal circuit formed on the semiconductor substrate. When the P-N junction is rendered conductive by an application of an excessive voltage to the input voltage, the current caused by the excessive voltage is absorbed to the supply potential through the P type region formed in the P well.
摘要翻译：半导体器件的输入电路包括在半导体衬底的主表面上良好地形成的P型阱和形成在P型阱的主表面上的N型区域。由N型区域和P型阱形成P-N结。输入电压施加到N型区域，该输入电压被施加到形成在半导体衬底上的内部电路。当通过对输入电压施加过大的电压使P-N结导通时，由过电压引起的电流通过形成在P阱中的P型区域吸收到电源电位。

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