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1. 发明申请

US20080017912A1 Non-volatile memory cell with embedded antifuse 有权
标题翻译：具有嵌入式反熔丝的非易失性存储单元
公开(公告)号：US20080017912A1
公开(公告)日：2008-01-24
申请号：US11819618
申请日：2007-06-28
申请人： Tanmay Kumar , S. Herner
发明人： Tanmay Kumar , S. Herner
IPC分类号： H01L29/76
CPC分类号： G11C5/02 , G11C11/39 , G11C11/5692 , G11C17/06 , G11C17/16 , G11C2213/71 , G11C2213/77 , H01L27/1021 , H01L29/0676
摘要： A nonvolatile memory device includes at least one memory cell which comprises a first diode portion, a second diode portion and an antifuse separating the first diode portion from the second diode portion.
摘要翻译：非易失性存储器件包括至少一个存储单元，其包括第一二极管部分，第二二极管部分和将第一二极管部分与第二二极管部分分开的反熔丝。

2. 发明申请

US20080007989A1 Programming methods to increase window for reverse write 3D cell 有权
标题翻译：编程方法增加反向写入3D单元格的窗口
公开(公告)号：US20080007989A1
公开(公告)日：2008-01-10
申请号：US11819077
申请日：2007-06-25
申请人： Tanmay Kumar , S. Herner , Christopher Petti
发明人： Tanmay Kumar , S. Herner , Christopher Petti
IPC分类号： G11C11/00 , G11C11/36
CPC分类号： G11C13/00 , G11C11/5692 , G11C13/0069 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2013/009 , G11C2213/33 , H01L27/101
摘要： A method of operating a nonvolatile memory cell includes providing the nonvolatile memory cell comprising a diode which is fabricated in a first resistivity, unprogrammed state, and applying a forward bias to the diode having a magnitude greater than a minimum voltage required for programming the diode to switch the diode to a second resistivity, programmed state. The second resistivity state is lower than the first resistivity state.
摘要翻译：一种操作非易失性存储单元的方法包括提供非易失性存储单元，该非易失性存储单元包括以第一电阻率，未编程状态制造的二极管，以及将正向偏压施加到具有大于将二极管编程所需的最小电压的二极管的幅度将二极管切换到第二电阻率，编程状态。第二电阻率状态低于第一电阻率状态。

3. 发明申请

US20080013364A1 Method of making non-volatile memory cell with embedded antifuse 有权
标题翻译：制造具有嵌入式反熔丝的非易失性存储单元的方法
公开(公告)号：US20080013364A1
公开(公告)日：2008-01-17
申请号：US11819595
申请日：2007-06-28
申请人： Tanmay Kumar , S. Herner
发明人： Tanmay Kumar , S. Herner
IPC分类号： G11C11/00 , H01L21/336
CPC分类号： G11C5/02 , G11C11/39 , G11C11/5692 , G11C17/06 , G11C17/16 , G11C2213/71 , G11C2213/77 , H01L27/1021 , H01L29/0676
摘要： A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell comprising a first diode portion, a second diode portion and an antifuse separating the first diode portion from the second diode portion, and forming a second electrode over the at least one nonvolatile memory cell.
摘要翻译：制造非易失性存储器件的方法包括形成第一电极，形成至少一个非易失性存储单元，该非易失性存储单元包括第一二极管部分，第二二极管部分和将第一二极管部分与第二二极管部分分离的反熔丝，以及形成第二电极在所述至少一个非易失性存储单元上。

4. 发明申请

US20070228414A1 Heterojunction device comprising a semiconductor and a resistivity-switching oxide or nitride 有权
标题翻译：异质结装置包括半导体和电阻率切换氧化物或氮化物
公开(公告)号：US20070228414A1
公开(公告)日：2007-10-04
申请号：US11395419
申请日：2006-03-31
申请人： Tanmay Kumar , S. Herner
发明人： Tanmay Kumar , S. Herner
IPC分类号： H01L29/732
CPC分类号： H01L29/868 , H01L21/84 , H01L27/1021 , H01L27/2409 , H01L29/165 , H01L29/22 , H01L29/267 , H01L29/417 , H01L29/737 , H01L29/8615 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： In the present invention a metal oxide or nitride compound which is a wide-band-gap semiconductor abuts a silicon, germanium, or alloy of silicon and/or germanium of the opposite conductivity type to form a p-n heterojunction. This p-n heterojunction can be used to advantage in various devices. In preferred embodiments, one terminal of a vertically oriented p-i-n heterojunction diode is a metal oxide or nitride layer, while the rest of the diode is formed of a silicon or silicon-germanium resistor; for example a diode may include a heavily doped n-type silicon region, an intrinsic silicon region, and a nickel oxide layer serving as the p-type terminal. Many of these metal oxides and nitrides exhibit resistivity-switching behavior, and such a heterojunction diode can be used in a nonvolatile memory cell, for example in a monolithic three dimensional memory array.
摘要翻译：在本发明中，作为宽带隙半导体的金属氧化物或氮化物化合物与相反导电型的硅和/或锗的硅，锗或合金相接触以形成p-n异质结。该p-n异质结可以用于各种装置中。在优选实施例中，垂直取向的p-i-n异质结二极管的一个端子是金属氧化物或氮化物层，而二极管的其余部分由硅或硅 - 锗电阻器形成; 例如二极管可以包括重掺杂的n型硅区，本征硅区和用作p型端的氧化镍层。这些金属氧化物和氮化物中的许多表现出电阻率切换行为，并且这种异质结二极管可以用在非易失性存储单元中，例如在单片三维存储器阵列中。

5. 发明申请

US20060250837A1 Nonvolatile memory cell comprising a diode and a resistance-switching material 有权
标题翻译：包括二极管和电阻切换材料的非易失性存储单元
公开(公告)号：US20060250837A1
公开(公告)日：2006-11-09
申请号：US11395995
申请日：2006-03-31
申请人： S. Herner , Tanmay Kumar , Christopher Petti
发明人： S. Herner , Tanmay Kumar , Christopher Petti
IPC分类号： G11C11/00
CPC分类号： H01L27/249 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146
摘要： In a novel nonvolatile memory cell formed above a substrate, a diode is paired with a reversible resistance-switching material, preferably a metal oxide or nitride such as, for example, NixOy, NbxOy, TixOy, HFxOy, AlxOy, MgxOy, CoxOy, CrxOy, VxOy, ZnxOy, ZrxOy, BxNy, and AlxNy. In preferred embodiments, the diode is formed as a vertical pillar disposed between conductors. Multiple memory levels can be stacked to form a monolithic three dimensional memory array. In some embodiments, the diode comprises germanium or a germanium alloy, which can be deposited and crystallized at relatively low temperatures, allowing use of aluminum or copper in the conductors. The memory cell of the present invention can be used as a rewriteable memory cell or a one-time-programmable memory cell, and can store two or more data states.
摘要翻译：在形成在衬底上方的新型非易失性存储单元中，二极管与可逆电阻切换材料配对，优选地为金属氧化物或氮化物，例如Ni x O y O y，铌，x O y，，，，，，，，，，，，，，，，，，，，，，，，，，，，，，，，，，，，，，SUB，SUB 其中，O x Y y O y，Y x O y，Y O x O x，X x O，O x O，X x O， y，x，x，y，y，x，y，x，y，x， / SUB＆gt; Y＆gt;和＆lt; N＆gt; N＆lt; / SUB＆gt;。在优选实施例中，二极管形成为设置在导体之间的垂直支柱。可以堆叠多个存储器级别以形成单片三维存储器阵列。在一些实施例中，二极管包括锗或锗合金，其可以在相对低的温度下沉积和结晶，从而允许在导体中使用铝或铜。本发明的存储单元可以用作可重写存储单元或一次可编程存储单元，并且可以存储两个或多个数据状态。

6. 发明申请

US20070114508A1 Reversible resistivity-switching metal oxide or nitride layer with added metal 有权
标题翻译：具有添加金属的可逆电阻率开关金属氧化物或氮化物层
公开(公告)号：US20070114508A1
公开(公告)日：2007-05-24
申请号：US11287452
申请日：2005-11-23
申请人： S. Herner , Tanmay Kumar
发明人： S. Herner , Tanmay Kumar
IPC分类号： H01L29/02 , H01L47/00
CPC分类号： H01L45/145 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1625 , H01L45/165 , H01L45/1658 , H01L45/1675
摘要： A layer of resistivity-switching metal oxide or nitride can attain at least two stable resistivity states. Such a layer may be used in a state-change element in a nonvolatile memory cell, storing its data state, for example a “0” or a “1”, in this resistivity state. Including additional metal atoms in a layer of such a resistivity-switching metal oxide or nitride compound decreases the current required to cause switching between resistivity states, reducing power requirements for an array of memory cells storing data in the resistivity state of such a layer. In various embodiments a memory cell may include a layer of resistivity-switching metal oxide or nitride compound with added metal formed in series with another element, such as a diode or a transistor.
摘要翻译：电阻率切换金属氧化物或氮化物层可达到至少两个稳定的电阻率状态。这种层可以用在非易失性存储单元中的状态变化元件中，在该电阻率状态下存储其数据状态，例如“0”或“1”。在这种电阻率切换金属氧化物或氮化物化合物的层中包括额外的金属原子降低了在电阻率状态之间导致切换所需的电流，从而降低了存储在这种层的电阻率状态下的数据的存储单元阵列的功率需求。在各种实施例中，存储器单元可以包括电阻率切换金属氧化物或具有与另一元件（例如二极管或晶体管）串联形成的附加金属的氮化物化合物层。

7. 发明申请

US20070102724A1 Vertical diode doped with antimony to avoid or limit dopant diffusion 审中-公开
标题翻译：掺杂锑的垂直二极管避免或限制掺杂剂扩散
公开(公告)号：US20070102724A1
公开(公告)日：2007-05-10
申请号：US11271078
申请日：2005-11-10
申请人： Tanmay Kumar , S. Herner
发明人： Tanmay Kumar , S. Herner
IPC分类号： H01L31/111
CPC分类号： H01L27/1021 , H01L29/167 , H01L29/861
摘要： Use of antimony as an n-type conductivity-enhancing dopant in semiconductor structures having a vertical dopant profile is described. Dopants tend to diffuse, and steep dopant gradients can be difficult to maintain. Specifically, when a silicon layer is doped with phosphorus or arsenic, both n-type dopants, dopant atoms tend to seek the surface as undoped silicon is deposited on top of the n-doped layer, rising through the undoped silicon during deposition. Antimony does not have this tendency, and also diffuses more slowly than either phosphorus or arsenic, and this is advantageously used to dope such structures.
摘要翻译：描述了在具有垂直掺杂剂分布的半导体结构中使用锑作为n型导电性增强掺杂剂。掺杂剂倾向于扩散，并且陡峭的掺杂剂梯度可能难以维持。具体地说，当硅层掺杂有磷或砷时，n型掺杂剂，掺杂剂原子倾向于寻找表面，因为未掺杂的硅沉积在n掺杂层的顶部，在沉积期间通过未掺杂的硅上升。锑不具有这种倾向，并且也比磷或砷更慢地扩散，并且有利地用于掺杂这种结构。

8. 发明申请

US20070090425A1 Memory cell comprising switchable semiconductor memory element with trimmable resistance 有权
标题翻译：存储单元包括具有可调整电阻的可切换半导体存储元件
公开(公告)号：US20070090425A1
公开(公告)日：2007-04-26
申请号：US11237167
申请日：2005-09-28
申请人： Tanmay Kumar , S. Herner
发明人： Tanmay Kumar , S. Herner
IPC分类号： H01L29/94
CPC分类号： G11C11/5692 , G11C11/005 , G11C11/5685 , G11C13/0007 , G11C13/003 , G11C17/14 , G11C2211/5641 , G11C2211/5646 , G11C2213/32 , G11C2213/71 , G11C2213/72 , G11C2213/76 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/148
摘要： A nonvolatile memory cell comprising doped semiconductor material and a diode can store memory states by changing the resistance of the doped semiconductor material by application of a set pulse (decreasing resistance) or a reset pulse (increasing resistance.) Set pulses are of short duration and above a threshold voltage, while reset pulses are longer duration and below a threshold voltage. In some embodiments multiple resistance states can be achieved, allowing for a multi-state cell, while restoring a prior high-resistance state allows for an rewriteable cell. In some embodiments, the diode and a switchable memory formed of doped semiconductor material are formed in series, while in other embodiments, the diode itself serves as the semiconductor switchable memory element.
摘要翻译：包括掺杂半导体材料和二极管的非易失性存储单元可以通过施加设置脉冲（降低电阻）或复位脉冲（增加电阻）来改变掺杂半导体材料的电阻来存储存储器状态。设置脉冲的持续时间短，高于阈值电压，而复位脉冲的持续时间更长并低于阈值电压。在一些实施例中，可以实现多个电阻状态，允许多状态单元，同时恢复先前的高电阻状态允许可重写单元。在一些实施例中，二极管和由掺杂半导体材料形成的可切换存储器是串联形成的，而在其它实施例中，二极管本身用作半导体可切换存储元件。

9. 发明授权

US08754671B2 Field programmable gate array utilizing two-terminal non-volatile memory 有权
公开(公告)号：US08754671B2
公开(公告)日：2014-06-17
申请号：US13194479
申请日：2011-07-29
申请人： Hagop Nazarian , Sang Thanh Nguyen , Tanmay Kumar
发明人： Hagop Nazarian , Sang Thanh Nguyen , Tanmay Kumar
IPC分类号： H03K19/0944 , H03K19/177 , G11C11/00
CPC分类号： H03K19/17776 , G11C13/0021 , H01L27/101 , H03K19/0013 , H03K19/00315 , H03K19/0944 , H03K19/1776
摘要： Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.

10. 发明授权

US08658476B1 Low temperature P+ polycrystalline silicon material for non-volatile memory device 有权
标题翻译：低温P +多晶硅材料用于非易失性存储器件
公开(公告)号：US08658476B1
公开(公告)日：2014-02-25
申请号：US13452657
申请日：2012-04-20
申请人： Xin Sun , Sung Hyun Jo , Tanmay Kumar
发明人： Xin Sun , Sung Hyun Jo , Tanmay Kumar
IPC分类号： H01L27/112 , H01L21/82 , H01L21/20 , H01L29/04 , H01L29/06 , H01L29/10
CPC分类号： H01L45/145 , H01L21/0245 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L27/101 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/148 , H01L45/1616 , H01L45/1675
摘要： A method of forming a non-volatile memory device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region of the substrate. A first electrode structure is formed overlying the first dielectric material and a p+ polycrystalline silicon germanium material is formed overlying the first electrode structure. A p+ polycrystalline silicon material is formed overlying the first electrode structure using the polycrystalline silicon germanium material as a seed layer at a deposition temperature ranging from about 430 Degree Celsius to about 475 Degree Celsius without further anneal. The method forms a resistive switching material overlying the polycrystalline silicon material, and a second electrode structure including an active metal material overlying the resistive switching material.
摘要翻译：一种形成非易失性存储器件的方法。该方法包括提供具有表面区域并形成覆盖在基板的表面区域上的第一介电材料的基板。形成第一电极结构，覆盖第一电介质材料，并且形成覆盖第一电极结构的p +多晶硅锗材料。在大约430摄氏度至大约475摄氏度的沉积温度下，使用多晶硅锗材料作为种子层，形成覆盖第一电极结构的p +多晶硅材料，而无需进一步退火。该方法形成覆盖多晶硅材料的电阻开关材料，以及包括覆盖电阻开关材料的活性金属材料的第二电极结构。

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