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1. 发明申请

US20130027081A1 FIELD PROGRAMMABLE GATE ARRAY UTILIZING TWO-TERMINAL NON-VOLATILE MEMORY 有权
标题翻译：现场可编程门阵列使用两端非易失性存储器
公开(公告)号：US20130027081A1
公开(公告)日：2013-01-31
申请号：US13194500
申请日：2011-07-29
申请人： Hagop Nazarian , Sang Thanh Nguyen , Tanmay Kumar
发明人： Hagop Nazarian , Sang Thanh Nguyen , Tanmay Kumar
IPC分类号： H03K19/0944 , H03K19/177
CPC分类号： H03K19/0013 , G11C13/0002 , G11C13/004 , G11C13/0069 , H03K19/0944 , H03K19/1776 , H03K19/17764 , H03K19/17776
摘要： Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.
摘要翻译：本文描述了利用电阻随机存取存储器（RRAM）技术提供现场可编程门阵列（FPGA）。作为示例，FPGA可以包括具有由垂直信号输出线交叉的并行信号输入线的开关块互连。可以在信号输入线和信号输出线的各个交叉处形成RRAM存储器单元。 RRAM存储器单元可以包括分压器，该分压器包括跨FPGA的VCC和VSS串联电串联的多个可编程电阻元件。分压器的公共节点驱动配置为激活或去激活交叉的通路晶体管的栅极。所公开的RRAM存储器可以提供高晶体管密度，高逻辑利用率，快速的编程速度，辐射抗扰度，快速上电和对FPGA技术的显着益处。

2. 发明申请

US20130027079A1 FIELD PROGRAMMABLE GATE ARRAY UTILIZING TWO-TERMINAL NON-VOLATILE MEMORY 有权
公开(公告)号：US20130027079A1
公开(公告)日：2013-01-31
申请号：US13194479
申请日：2011-07-29
申请人： Hagop Nazarian , Sang Thanh Nguyen , Tanmay Kumar
发明人： Hagop Nazarian , Sang Thanh Nguyen , Tanmay Kumar
IPC分类号： H03K19/177 , G11C11/00 , H01L21/82
CPC分类号： H03K19/17776 , G11C13/0021 , H01L27/101 , H03K19/0013 , H03K19/00315 , H03K19/0944 , H03K19/1776
摘要： Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.

3. 发明授权

US08754671B2 Field programmable gate array utilizing two-terminal non-volatile memory 有权
公开(公告)号：US08754671B2
公开(公告)日：2014-06-17
申请号：US13194479
申请日：2011-07-29
申请人： Hagop Nazarian , Sang Thanh Nguyen , Tanmay Kumar
发明人： Hagop Nazarian , Sang Thanh Nguyen , Tanmay Kumar
IPC分类号： H03K19/0944 , H03K19/177 , G11C11/00
CPC分类号： H03K19/17776 , G11C13/0021 , H01L27/101 , H03K19/0013 , H03K19/00315 , H03K19/0944 , H03K19/1776
摘要： Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.

4. 发明授权

US08674724B2 Field programmable gate array utilizing two-terminal non-volatile memory 有权
标题翻译：采用双端非易失性存储器的现场可编程门阵列
公开(公告)号：US08674724B2
公开(公告)日：2014-03-18
申请号：US13194500
申请日：2011-07-29
申请人： Hagop Nazarian , Sang Thanh Nguyen , Tanmay Kumar
发明人： Hagop Nazarian , Sang Thanh Nguyen , Tanmay Kumar
IPC分类号： H03K19/0944 , H03K19/177 , G11C11/00
CPC分类号： H03K19/0013 , G11C13/0002 , G11C13/004 , G11C13/0069 , H03K19/0944 , H03K19/1776 , H03K19/17764 , H03K19/17776
摘要： Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.
摘要翻译：本文描述了利用电阻随机存取存储器（RRAM）技术提供现场可编程门阵列（FPGA）。作为示例，FPGA可以包括具有由垂直信号输出线交叉的并行信号输入线的开关块互连。可以在信号输入线和信号输出线的各个交叉处形成RRAM存储器单元。 RRAM存储器单元可以包括分压器，该分压器包括跨FPGA的VCC和VSS串联电串联的多个可编程电阻元件。分压器的公共节点驱动配置为激活或去激活交叉的通路晶体管的栅极。所公开的RRAM存储器可以提供高晶体管密度，高逻辑利用率，快速的编程速度，辐射抗扰度，快速上电和对FPGA技术的显着益处。

5. 发明授权

US09001552B1 Programming a RRAM method and apparatus 有权
标题翻译：编程RRAM方法和设备
公开(公告)号：US09001552B1
公开(公告)日：2015-04-07
申请号：US13531449
申请日：2012-06-22
申请人： Sang Thanh Nguyen , Hagop Nazarian , Layne Armijo
发明人： Sang Thanh Nguyen , Hagop Nazarian , Layne Armijo
IPC分类号： G11C11/00 , G11C11/404
CPC分类号： G11C11/4045 , G11C13/0002 , G11C13/0069 , G11C2013/0066 , G11C2013/0078 , G11C2213/33
摘要： A circuit for programming a resistive switching device includes a resistive switching device characterized by a programmable resistance, the resistive switching device comprising a first terminal, a second terminal, and a resistive switching element, a first circuit configured to supply a programming voltage to the resistive switching device and to supply a predetermined current to flow in the resistive switching device, and a second circuit coupled to the first circuit and to the resistive switching device, wherein the second circuit is configured to terminate the supply of the programming voltage to the resistive switching device when the predetermined current flows in the resistive switching device.
摘要翻译：一种用于编程电阻性开关器件的电路包括一个以可编程电阻为特征的电阻开关器件，该电阻开关器件包括一个第一端子，一个第二端子和一个电阻性开关元件，第一电路被配置为向电阻并且提供预定电流以在所述电阻开关器件中流动;以及第二电路，耦合到所述第一电路和所述电阻开关器件，其中所述第二电路被配置为终止所述编程电压到所述电阻开关的供应当预定电流在电阻式开关装置中流动时，装置。

6. 发明授权

US08674749B2 Fast start charge pump for voltage regulators 有权
标题翻译：用于稳压器的快速启动电荷泵
公开(公告)号：US08674749B2
公开(公告)日：2014-03-18
申请号：US12726249
申请日：2010-03-17
申请人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung Q. Nguyen , Wingfu AAron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
发明人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung Q. Nguyen , Wingfu AAron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H02M3/07 , H02M1/36 , H02M1/44
摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.
摘要翻译：数字多电平存储器系统包括电荷泵和用于产生用于各种存储器操作的调节高电压的电压调节器。电荷泵可以包括多个升压电路，以在快速启动期间升高电荷泵的输出。之后，升压电路被禁止，使电荷泵产生高电压而不加速。升压电路可以被连续地使能以升高电压。升压电路可以是无负载的。电压调节器可以在开环中工作，并且可以包括电阻分压器作为用于调节来自电荷泵的高电压的参考电压。电荷泵可以包括扩频泵时钟，以减少用于电容器或电感器片上电荷泵浦的电磁推理。

7. 发明申请

US20130187707A1 Charge Pump Systems and Methods 有权
标题翻译：电荷泵系统和方法
公开(公告)号：US20130187707A1
公开(公告)日：2013-07-25
申请号：US13726522
申请日：2012-12-24
申请人： Hieu Van Tran , Sang Thanh Nguyen , Nasrin Jaffari , Hung Quoc Nguyen , Anh Ly
发明人： Hieu Van Tran , Sang Thanh Nguyen , Nasrin Jaffari , Hung Quoc Nguyen , Anh Ly
IPC分类号： G05F3/02
CPC分类号： G05F3/02 , H02M3/073 , H02M2001/322
摘要： Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.
摘要翻译：数字多电平存储器系统和方法包括用于为各种存储器操作产生调节的高电压的电荷泵。电荷泵可以包括多个泵级。示例性系统的方面可以包括在低电压操作条件下执行有序充电和放电的电荷泵。其他方面可以包括使状态状态泵送的特征，例如避免泵级之间的级联短路的电路。每个泵级还可以包括排放其节点的电路，例如通过相关联的泵互连通过自放电。另外的方面还可以包括以下功能：辅助各个泵级的上电，双电压，高电平移位，提供反并联电路配置和/或实现缓冲或预充电特征，例如自缓冲和自缓冲，预充电电路。

8. 发明授权

US08270213B2 Flash memory array system including a top gate memory cell 有权
标题翻译：包括顶栅存储单元的闪存阵列系统
公开(公告)号：US08270213B2
公开(公告)日：2012-09-18
申请号：US12962343
申请日：2010-12-07
申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
发明人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
IPC分类号： G11C16/12
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
摘要翻译：存储器系统包括布置在扇区中的存储器单元。对应于扇区的解码器禁止具有缺陷顶门的存储单元。解码器可以包括用于禁用的低电压或高电压锁存器。包括顶栅处理算法。存储器系统可以包括动态顶栅耦合。包括具有顶栅处理的编程算法和波形。

9. 发明授权

US08020055B2 Method and apparatus for testing the connectivity of a flash memory chip 有权
标题翻译：用于测试闪存芯片连接性的方法和装置
公开(公告)号：US08020055B2
公开(公告)日：2011-09-13
申请号：US12629302
申请日：2009-12-02
申请人： Sang Thanh Nguyen , Hieu Van Tran , Hung O. Nguyen , Phil Klotzkin
发明人： Sang Thanh Nguyen , Hieu Van Tran , Hung O. Nguyen , Phil Klotzkin
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/02 , G11C29/022 , G11C2029/3202
摘要： In one embodiment of the invention, circuitry and hardware for connectivity testing are fabricated on an IC, and in particular an IC containing a flash memory array. This testing circuitry is electrically connected to the bond pads of the IC. In some embodiments, the testing circuitry includes a boundary scan cell connected to each bond pad, allowing for rapid connectivity testing of flash memory chips in accordance with testing standards such as the JTAG standard. The invention further includes methods in which the pins and/or memory cells of a flash memory chip are sequentially sent a series of data so as to test the connectivity of portions of the IC. The sequentially-sent data is then retrieved and compared to the original data. Discrepancies between these sets of data thus highlight connectivity problems in the IC.
摘要翻译：在本发明的一个实施例中，用于连接测试的电路和硬件被制造在IC上，特别是包含闪存阵列的IC。该测试电路电连接到IC的接合焊盘。在一些实施例中，测试电路包括连接到每个接合焊盘的边界扫描单元，允许根据诸如JTAG标准的测试标准对闪存芯片进行快速连接测试。本发明还包括其中闪存芯片的引脚和/或存储单元被顺序发送一系列数据以测试IC的部分连通性的方法。然后检索顺序发送的数据并将其与原始数据进行比较。因此，这些数据集之间的差异突出了IC中的连接问题。

10. 发明授权

US07778080B2 Flash memory array system including a top gate memory cell 有权
公开(公告)号：US07778080B2
公开(公告)日：2010-08-17
申请号：US12200930
申请日：2008-08-28
申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
发明人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
IPC分类号： G11C16/34
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

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