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1. 发明授权

US08658476B1 Low temperature P+ polycrystalline silicon material for non-volatile memory device 有权
标题翻译：低温P +多晶硅材料用于非易失性存储器件
公开(公告)号：US08658476B1
公开(公告)日：2014-02-25
申请号：US13452657
申请日：2012-04-20
申请人： Xin Sun , Sung Hyun Jo , Tanmay Kumar
发明人： Xin Sun , Sung Hyun Jo , Tanmay Kumar
IPC分类号： H01L27/112 , H01L21/82 , H01L21/20 , H01L29/04 , H01L29/06 , H01L29/10
CPC分类号： H01L45/145 , H01L21/0245 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L27/101 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/148 , H01L45/1616 , H01L45/1675
摘要： A method of forming a non-volatile memory device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region of the substrate. A first electrode structure is formed overlying the first dielectric material and a p+ polycrystalline silicon germanium material is formed overlying the first electrode structure. A p+ polycrystalline silicon material is formed overlying the first electrode structure using the polycrystalline silicon germanium material as a seed layer at a deposition temperature ranging from about 430 Degree Celsius to about 475 Degree Celsius without further anneal. The method forms a resistive switching material overlying the polycrystalline silicon material, and a second electrode structure including an active metal material overlying the resistive switching material.
摘要翻译：一种形成非易失性存储器件的方法。该方法包括提供具有表面区域并形成覆盖在基板的表面区域上的第一介电材料的基板。形成第一电极结构，覆盖第一电介质材料，并且形成覆盖第一电极结构的p +多晶硅锗材料。在大约430摄氏度至大约475摄氏度的沉积温度下，使用多晶硅锗材料作为种子层，形成覆盖第一电极结构的p +多晶硅材料，而无需进一步退火。该方法形成覆盖多晶硅材料的电阻开关材料，以及包括覆盖电阻开关材料的活性金属材料的第二电极结构。

2. 发明授权

US09058865B1 Multi-level cell operation in silver/amorphous silicon RRAM 有权
标题翻译：银/非晶硅RRAM中的多层电池操作
公开(公告)号：US09058865B1
公开(公告)日：2015-06-16
申请号：US13525096
申请日：2012-06-15
申请人： Sung Hyun Jo , Tanmay Kumar
发明人： Sung Hyun Jo , Tanmay Kumar
IPC分类号： G11C13/00
CPC分类号： G11C13/00 , G11C11/56 , G11C11/5614 , G11C13/0002 , G11C13/0009 , G11C13/0011 , G11C13/0069 , G11C2013/0083 , G11C2213/33
摘要： A method of programming a non-volatile memory device includes providing a resistive switching device, the resistive switching device being in a first state and characterized by at least a first resistance, applying a first voltage to the resistive switching device in the first state to cause the resistive switching device to change to a second state wherein the second state is characterized by at least a second resistance, wherein the second resistance is greater than the first resistance, and applying a second voltage to the resistive switching device in the second state to cause the resistive switching device to change to a third state, wherein the third state is characterized by at least a third resistance, wherein the second voltage has a magnitude higher than a magnitude of the second voltage, and wherein the third resistance is greater than the second resistance.
摘要翻译：一种对非易失性存储器件进行编程的方法包括：提供电阻式开关器件，所述电阻开关器件处于第一状态，其特征在于至少第一电阻，在所述第一状态下向所述电阻开关器件施加第一电压以引起所述电阻式开关装置改变为第二状态，其中所述第二状态的特征在于至少第二电阻，其中所述第二电阻大于所述第一电阻，并且在所述第二状态下向所述电阻式开关装置施加第二电压以引起所述电阻性开关器件改变为第三状态，其中所述第三状态的特征在于至少第三电阻，其中所述第二电压具有高于所述第二电压的幅度的幅度，并且其中所述第三电阻大于所述第二电阻抵抗性。

3. 发明授权

US08569172B1 Noble metal/non-noble metal electrode for RRAM applications 有权
标题翻译：贵金属/非贵金属电极用于RRAM应用
公开(公告)号：US08569172B1
公开(公告)日：2013-10-29
申请号：US13585759
申请日：2012-08-14
申请人： Sung Hyun Jo , Kuk-Hwan Kim , Tanmay Kumar
发明人： Sung Hyun Jo , Kuk-Hwan Kim , Tanmay Kumar
IPC分类号： H01L21/44 , H01L21/00
CPC分类号： H01L45/146 , H01L27/2436 , H01L45/08 , H01L45/085 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/148 , H01L45/16 , H01L45/1616 , H01L45/1675
摘要： A method for forming a non-volatile memory device includes disposing a junction layer comprising a doped silicon-bearing material in electrical contact with a first conductive material, forming a switching layer comprising an undoped amorphous silicon-bearing material upon at least a portion of the junction layer, disposing a layer comprising a non-noble metal material upon at least a portion of the switching layer, disposing an active metal layer comprising a noble metal material upon at least a portion of the layer, and forming a second conductive material in electrical contact with the active metal layer.
摘要翻译：一种用于形成非易失性存储器件的方法包括设置包括掺杂的含硅材料与第一导电材料电接触的结层，在至少一部分所述第一导电材料上形成包含未掺杂的非晶硅承载材料的开关层将包含非贵金属材料的层设置在所述开关层的至少一部分上，在所述层的至少一部分上设置包含贵金属材料的活性金属层，以及在所述第一导电材料的至少一部分上形成第二导电材料与活性金属层接触。

4. 发明授权

US08971088B1 Multi-level cell operation using zinc oxide switching material in non-volatile memory device 有权
标题翻译：在非易失性存储器件中使用氧化锌切换材料的多级电池操作
公开(公告)号：US08971088B1
公开(公告)日：2015-03-03
申请号：US13426869
申请日：2012-03-22
申请人： Sung Hyun Jo , Tanmay Kumar
发明人： Sung Hyun Jo , Tanmay Kumar
IPC分类号： G11C11/00
CPC分类号： G11C11/5628 , G11C11/1675 , G11C11/2275 , G11C11/56 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2013/0092 , G11C2211/562 , G11C2211/5648 , G11C2213/15
摘要： A method for programming a non-volatile memory device includes providing an as-fabricated state-change device having an aluminum doped zinc oxide material first electrode, a p++ polysilicon material second electrode, and a zinc oxide (ZnO) material state-change material there between. A first amplitude bias voltage is applied to the first electrode of the as-fabricated state-change device causing the ZnO material to change form an as-fabricated state to a first state. A second amplitude bias voltage having an opposite polarity having an amplitude similar to the first amplitude is applied to cause the ZnO to change from the first state to a second state substantially similar as the as-fabricated state. A third amplitude bias voltage having a same polarity to the first bias voltage and having an amplitude dissimilar to the first bias voltage is applied to cause the ZnO to change from the second state to a third state.
摘要翻译：用于编程非易失性存储器件的方法包括提供一种具有铝掺杂氧化锌材料第一电极，p ++多晶硅材料第二电极和氧化锌（ZnO）材料状态变化材料的制造状态改变器件之间。第一幅度偏置电压被施加到制造状态改变器件的第一电极，使得ZnO材料从制造状态改变到第一状态。施加具有与第一幅度相似的振幅相反极性的第二幅度偏置电压，以使ZnO从第一状态转变为与制造状态基本相似的第二状态。施加与第一偏置电压具有相同极性且具有与第一偏置电压不同的幅度的第三幅度偏置电压，以使ZnO从第二状态变为第三状态。

5. 发明授权

US08946669B1 Resistive memory device and fabrication methods 有权
标题翻译：电阻式存储器件及其制造方法
公开(公告)号：US08946669B1
公开(公告)日：2015-02-03
申请号：US13586815
申请日：2012-08-15
申请人： Sung Hyun Jo , Kuk-Hwan Kim , Tanmay Kumar
发明人： Sung Hyun Jo , Kuk-Hwan Kim , Tanmay Kumar
IPC分类号： H01L29/02
CPC分类号： H01L27/2463 , H01L27/2436 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/148 , H01L45/1633 , H01L45/1675
摘要： A method for forming a resistive memory device includes providing a substrate comprising a first metal material, forming a conductive silicon-bearing layer on top of the first metal material, wherein the conductive silicon-bearing layer comprises an upper region and a lower region, and wherein the lower region is adjacent to the first metal material, forming an amorphous layer from the upper region of the conductive silicon-bearing layer, and disposing an active metal material above the amorphous layer.
摘要翻译：一种用于形成电阻式存储器件的方法包括提供包括第一金属材料的衬底，在第一金属材料的顶部上形成导电含硅层，其中导电含硅层包括上部区域和下部区域，以及其中所述下部区域与所述第一金属材料相邻，从所述导电含硅层的上部区域形成非晶层，并且在所述非晶层的上方设置活性金属材料。

6. 发明授权

US09508425B2 Nanoscale metal oxide resistive switching element 有权
标题翻译：纳米级金属氧化物电阻开关元件
公开(公告)号：US09508425B2
公开(公告)日：2016-11-29
申请号：US13167920
申请日：2011-06-24
申请人： Wei Lu , Sung Hyun Jo
发明人： Wei Lu , Sung Hyun Jo
IPC分类号： H01L47/00 , G11C11/56 , G11C13/00 , H01L27/24 , H01L45/00
CPC分类号： G11C11/5685 , G11C13/0007 , H01L27/2436 , H01L27/2472 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1633 , H01L45/1675
摘要： A non-volatile memory device structure. The non-volatile memory device structure comprises a first electrode formed from a first metal material, a resistive switching element overlying the first electrode. The resistive switching element comprises a metal oxide material characterized by one or more oxygen deficient sites. The device includes a second electrode overlying the resistive switching layer, the second electrode being formed from a second metal material. The second electrode is made from a noble metal. The one or more oxygen deficient sites are caused to migrate from one of the first electrode or the second electrode towards the other electrode upon a voltage applied to the first electrode or the second electrode. The device can have a continuous change in resistance upon applying a continuous voltage ramp, suitable for an analog device. Alternatively, the device can have a sharp change in resistance upon applying the continuous voltage ramp, suitable for a digital device.
摘要翻译：非易失性存储器件结构。非易失性存储器件结构包括由第一金属材料形成的第一电极，覆盖第一电极的电阻式开关元件。电阻式开关元件包括以一个或多个缺氧部位为特征的金属氧化物材料。该器件包括覆盖电阻开关层的第二电极，第二电极由第二金属材料形成。第二电极由贵金属制成。当施加到第一电极或第二电极的电压时，使一个或多个缺氧部位从第一电极或第二电极中的一个迁移到另一个电极。当施加适用于模拟装置的连续电压斜坡时，该装置可以具有连续的电阻变化。或者，在施加适用于数字设备的连续电压斜坡时，该装置可以具有急剧的电阻变化。

7. 发明授权

US08907317B2 Silicon based nanoscale crossbar memory 有权
标题翻译：硅基纳米尺度交叉记忆体
公开(公告)号：US08907317B2
公开(公告)日：2014-12-09
申请号：US13291094
申请日：2011-11-07
申请人： Wei Lu , Sung Hyun Jo , Kuk-Hwan Kim
发明人： Wei Lu , Sung Hyun Jo , Kuk-Hwan Kim
IPC分类号： H01L29/06 , H01L21/82 , G11C13/00 , H01L45/00 , H01L27/24 , G11C11/56 , B82Y10/00
CPC分类号： H01L45/1253 , B82Y10/00 , B82Y30/00 , G11C11/5614 , G11C13/0011 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/005 , G11C2013/0071 , G11C2213/11 , G11C2213/33 , G11C2213/77 , G11C2213/81 , H01L27/2409 , H01L27/2463 , H01L27/2472 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1266 , H01L45/148 , H01L45/1608 , H01L45/1675
摘要： The present application describes a crossbar memory array. The memory array includes a first array of parallel nanowires of a first material and a second array of parallel nanowires of a second material. The first and the second array are oriented at an angle with each other. The array further includes a plurality of nanostructures of non-crystalline silicon disposed between a nanowire of the first material and a nanowire of the second material at each intersection of the two arrays. The nanostructures form a resistive memory cell together with the nanowires of the first and second materials.
摘要翻译：本申请描述了一种交叉开关存储器阵列。存储器阵列包括第一材料的平行纳米线的第一阵列和第二材料的平行纳米线的第二阵列。第一和第二阵列彼此成一角度定向。阵列还包括布置在第一材料的纳米线和第二材料的纳米线之间的两个阵列的每个交叉处的非晶硅的多个纳米结构。纳米结构与第一和第二材料的纳米线一起形成电阻记忆单元。

8. 发明申请

US20140036605A1 RESISTIVE SWITCHING FOR NON VOLATILE MEMORY DEVICE USING AN INTEGRATED BREAKDOWN ELEMENT 有权
公开(公告)号：US20140036605A1
公开(公告)日：2014-02-06
申请号：US13735814
申请日：2013-01-07
申请人： Wei Lu , Sung Hyun Jo
发明人： Wei Lu , Sung Hyun Jo
IPC分类号： G11C13/00 , H02H9/08
CPC分类号： H01L45/1616 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2213/33 , G11C2213/76 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/08 , H01L45/085 , H01L45/12 , H01L45/1233 , H01L45/14 , H01L45/141 , H01L45/146 , H01L45/148 , H02H9/08
摘要： A method of suppressing propagation of leakage current in an array of switching devices. The method includes providing a dielectric breakdown element integrally and serially connected to a switching element within each of the switching device. A read voltage (for example) is applied to a selected cell. The propagation of leakage current is suppressed by each of the dielectric breakdown element in unselected cells in the array. The read voltage is sufficient to cause breakdown in the selected cells but insufficient to cause breakdown in the serially connected, unselected cells in a specific embodiment. Methods to fabricate of such devices and to program, to erase and to read the device are provided.

9. 发明授权

US08391049B2 Resistor structure for a non-volatile memory device and method 有权
公开(公告)号：US08391049B2
公开(公告)日：2013-03-05
申请号：US12894087
申请日：2010-09-29
申请人： Sung Hyun Jo
发明人： Sung Hyun Jo
IPC分类号： G11C11/00
CPC分类号： H01L28/20 , G11C11/22 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0069 , G11C2213/33 , G11C2213/56 , H01L27/2463 , H01L45/085 , H01L45/1253 , H01L45/1675
摘要： A non-volatile resistive switching memory device. The device includes a first electrode, a second electrode, a switching material in direct contact with a metal region of the second electrode, and a resistive material disposed between the second electrode and the switching material. The resistive material has an ohmic characteristic and a resistance substantially the same as an on state resistance of the switching device. The resistive material allows for a change in a resistance of the switching material upon application of voltage pulse without time delay and free of a reverse bias after the voltage pulse. The first voltage pulse causes a programming current to flow from the second electrode to the first electrode. The resistive material further causes the programming current to be no greater than a predetermined value.

10. 发明授权

US08274812B2 Write and erase scheme for resistive memory device 有权
标题翻译：电阻式存储器件的写入和擦除方案
公开(公告)号：US08274812B2
公开(公告)日：2012-09-25
申请号：US12815369
申请日：2010-06-14
申请人： Hagop Nazarian , Sung Hyun Jo
发明人： Hagop Nazarian , Sung Hyun Jo
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0011 , G11C13/0064 , G11C2013/0066 , G11C2213/15 , G11C2213/33
摘要： A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal to or greater than a predetermined value.
摘要翻译：一种用于编程两端电阻式存储器件的方法，所述方法包括：将偏置电压施加到所述器件的电阻存储器单元的第一电极; 测量流过电池的电流; 如果测量的电流等于或大于预定值，则停止施加偏置电压。

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