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1. 发明申请

US20080007989A1 Programming methods to increase window for reverse write 3D cell 有权
标题翻译：编程方法增加反向写入3D单元格的窗口
公开(公告)号：US20080007989A1
公开(公告)日：2008-01-10
申请号：US11819077
申请日：2007-06-25
申请人： Tanmay Kumar , S. Herner , Christopher Petti
发明人： Tanmay Kumar , S. Herner , Christopher Petti
IPC分类号： G11C11/00 , G11C11/36
CPC分类号： G11C13/00 , G11C11/5692 , G11C13/0069 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2013/009 , G11C2213/33 , H01L27/101
摘要： A method of operating a nonvolatile memory cell includes providing the nonvolatile memory cell comprising a diode which is fabricated in a first resistivity, unprogrammed state, and applying a forward bias to the diode having a magnitude greater than a minimum voltage required for programming the diode to switch the diode to a second resistivity, programmed state. The second resistivity state is lower than the first resistivity state.
摘要翻译：一种操作非易失性存储单元的方法包括提供非易失性存储单元，该非易失性存储单元包括以第一电阻率，未编程状态制造的二极管，以及将正向偏压施加到具有大于将二极管编程所需的最小电压的二极管的幅度将二极管切换到第二电阻率，编程状态。第二电阻率状态低于第一电阻率状态。

2. 发明申请

US20060250837A1 Nonvolatile memory cell comprising a diode and a resistance-switching material 有权
标题翻译：包括二极管和电阻切换材料的非易失性存储单元
公开(公告)号：US20060250837A1
公开(公告)日：2006-11-09
申请号：US11395995
申请日：2006-03-31
申请人： S. Herner , Tanmay Kumar , Christopher Petti
发明人： S. Herner , Tanmay Kumar , Christopher Petti
IPC分类号： G11C11/00
CPC分类号： H01L27/249 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146
摘要： In a novel nonvolatile memory cell formed above a substrate, a diode is paired with a reversible resistance-switching material, preferably a metal oxide or nitride such as, for example, NixOy, NbxOy, TixOy, HFxOy, AlxOy, MgxOy, CoxOy, CrxOy, VxOy, ZnxOy, ZrxOy, BxNy, and AlxNy. In preferred embodiments, the diode is formed as a vertical pillar disposed between conductors. Multiple memory levels can be stacked to form a monolithic three dimensional memory array. In some embodiments, the diode comprises germanium or a germanium alloy, which can be deposited and crystallized at relatively low temperatures, allowing use of aluminum or copper in the conductors. The memory cell of the present invention can be used as a rewriteable memory cell or a one-time-programmable memory cell, and can store two or more data states.
摘要翻译：在形成在衬底上方的新型非易失性存储单元中，二极管与可逆电阻切换材料配对，优选地为金属氧化物或氮化物，例如Ni x O y O y，铌，x O y，，，，，，，，，，，，，，，，，，，，，，，，，，，，，，，，，，，，，，SUB，SUB 其中，O x Y y O y，Y x O y，Y O x O x，X x O，O x O，X x O， y，x，x，y，y，x，y，x，y，x， / SUB＆gt; Y＆gt;和＆lt; N＆gt; N＆lt; / SUB＆gt;。在优选实施例中，二极管形成为设置在导体之间的垂直支柱。可以堆叠多个存储器级别以形成单片三维存储器阵列。在一些实施例中，二极管包括锗或锗合金，其可以在相对低的温度下沉积和结晶，从而允许在导体中使用铝或铜。本发明的存储单元可以用作可重写存储单元或一次可编程存储单元，并且可以存储两个或多个数据状态。

3. 发明申请

US20060221758A1 TRANSISTOR LAYOUT CONFIGURATION FOR TIGHT-PITCHED MEMORY ARRAY LINES 有权
标题翻译：用于紧凑的内存阵列的晶体管布局配置
公开(公告)号：US20060221758A1
公开(公告)日：2006-10-05
申请号：US11420787
申请日：2006-05-29
申请人： Christopher Petti , Roy Scheuerlein , Tanmay Kumar , Abhijit Bandyopadhyay
发明人： Christopher Petti , Roy Scheuerlein , Tanmay Kumar , Abhijit Bandyopadhyay
IPC分类号： G11C8/00
CPC分类号： G11C8/14 , G11C5/02 , G11C5/063 , G11C8/08 , H01L27/0207 , H01L27/0688 , H01L27/10894 , H01L27/10897
摘要： A multi-headed word line driver circuit incorporates bent-gate transistors to reduce the pitch otherwise achievable for interfacing to tightly-pitched array lines. In certain exemplary embodiments, a three-dimensional memory array includes multiple memory blocks and array lines traversing horizontally across at least one memory block. Vertical active area stripes are disposed beneath a first memory block, and a respective plurality of bent-gate electrodes intersects each respective active area stripe to define individual source/drain regions. Every other source/drain region is coupled to a bias node for the active area stripe, and remaining source/drain regions are respectively coupled to a respective array line associated with the first memory block, thereby forming a respective first driver transistor for the respective array line. In certain embodiments, a respective plurality of complementary array line driver circuits is disposed on each side of a connection area between adjacent memory blocks, and each such driver circuit is responsive to a single driver input node.
摘要翻译：多头字线驱动电路包括弯栅晶体管，以减少为了与紧密排列的阵列线连接而实现的间距。在某些示例性实施例中，三维存储器阵列包括穿过至少一个存储器块水平横越的多个存储器块和阵列线。垂直有源区条纹设置在第一存储块下方，并且相应的多个弯曲栅电极与每个相应的有源区条纹相交以限定各个源/漏区。每个其它源极/漏极区域耦合到用于有源区域条纹的偏置节点，并且剩余的源极/漏极区域分别耦合到与第一存储器模块相关联的相应阵列线，从而形成用于相应阵列的相应的第一驱动器晶体管线。在某些实施例中，相应的多个互补阵列线驱动器电路设置在相邻存储块之间的连接区域的每一侧上，并且每个这样的驱动器电路响应于单个驱动器输入节点。

4. 发明申请

US20060222962A1 Masking of repeated overlay and alignment marks to allow reuse of photomasks in a vertical structure 有权
公开(公告)号：US20060222962A1
公开(公告)日：2006-10-05
申请号：US11097496
申请日：2005-03-31
申请人： Yung-Tin Chen , Christopher Petti , Steven Radigan , Tanmay Kumar
发明人： Yung-Tin Chen , Christopher Petti , Steven Radigan , Tanmay Kumar
IPC分类号： G03C5/00 , G03F9/00 , G03F1/00
CPC分类号： H01L27/0688 , G03F7/70633 , G03F9/7084 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/5446
摘要： In formation of monolithic three dimensional memory arrays, a photomask may be used more than once. Reuse of a photomask creates second, third or more instances of reference marks used by the stepper to achieve alignment (alignment marks) and to measure alignment achieved (overlay marks) directly above prior instances of the same reference mark. The prior instances of the same reference mark may cause interference with the present instance of the reference mark, complicating alignment and measurement. Using the methods of the present invention, blocking structure is created vertically interposed between subsequent instances of the same reference mark, preventing interference.

5. 发明申请

US20070072360A1 Method for using a memory cell comprising switchable semiconductor memory element with trimmable resistance 有权
标题翻译：一种用于使用具有可调整电阻的可切换半导体存储元件的存储单元的方法
公开(公告)号：US20070072360A1
公开(公告)日：2007-03-29
申请号：US11496986
申请日：2006-07-31
申请人： Tanmay Kumar , S.B. Herner , Roy Scheuerlein , Christopher Petti
发明人： Tanmay Kumar , S.B. Herner , Roy Scheuerlein , Christopher Petti
IPC分类号： H01L21/8234
CPC分类号： G11C11/5692 , G11C13/0069 , G11C17/14 , G11C17/165 , G11C2013/0073 , H01L27/101
摘要： A nonvolatile memory cell comprising a diode formed of semiconductor material can store memory states by changing the resistance of the semiconductor material by application of a set pulse (decreasing resistance) or a reset pulse (increasing resistance.) In preferred embodiments, set pulses are applied with the diode under forward bias, while reset pulses are applied with the diode in reverse bias. By switching resistivity of the semiconductor material of the diode, a memory cell can be either one-time programmable or rewriteable, and can achieve two, three, four, or more distinct data states.
摘要翻译：包括由半导体材料形成的二极管的非易失性存储单元可以通过施加设置脉冲（降低电阻）或复位脉冲（增加电阻）来改变半导体材料的电阻来存储存储器状态。在优选实施例中，施加设定脉冲二极管在正向偏置下，而复位脉冲以二极管反向施加。通过切换二极管的半导体材料的电阻率，存储器单元可以是一次性可编程的或可重写的，并且可以实现两个，三个，四个或更多个不同的数据状态。

6. 发明申请

US20070007577A1 Integrated circuit embodying a non-volatile memory cell 审中-公开
标题翻译：集成电路体现了非易失性存储单元
公开(公告)号：US20070007577A1
公开(公告)日：2007-01-11
申请号：US11175688
申请日：2005-07-06
申请人： Abhijit Bandyopadhyay , Christopher Petti , Tanmay Kumar
发明人： Abhijit Bandyopadhyay , Christopher Petti , Tanmay Kumar
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , G11C16/0416 , G11C2216/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： An integrated circuit is provided including at least one memory cell. Such memory cell, in turn, includes a transistor and a capacitor. The transistor includes a source, a drain, and a gate. Further, the capacitor includes a well and a gate. The gate of the transistor remains in communication with the gate of the capacitor. In various other embodiments, the memory cell includes a transistor and a capacitor including wells of differing types (e.g. P-type, N-type). In such embodiments, the well of the transistor abuts the well of the capacitor. In still further embodiments, for a more compact design, a diffusion region of the transistor is situated less than 2.5 μm from a diffusion region of the capacitor.
摘要翻译：提供了包括至少一个存储单元的集成电路。这样的存储单元又包括晶体管和电容器。晶体管包括源极，漏极和栅极。此外，电容器包括阱和栅极。晶体管的栅极保持与电容器的栅极通信。在各种其他实施例中，存储单元包括晶体管和包括不同类型的阱（例如，P型，N型）的电容器。在这样的实施例中，晶体管的阱邻接电容器的阱。在另外的实施例中，为了更紧凑的设计，晶体管的扩散区域距离电容器的扩散区域小于2.5μm。

7. 发明申请

US20080017912A1 Non-volatile memory cell with embedded antifuse 有权
标题翻译：具有嵌入式反熔丝的非易失性存储单元
公开(公告)号：US20080017912A1
公开(公告)日：2008-01-24
申请号：US11819618
申请日：2007-06-28
申请人： Tanmay Kumar , S. Herner
发明人： Tanmay Kumar , S. Herner
IPC分类号： H01L29/76
CPC分类号： G11C5/02 , G11C11/39 , G11C11/5692 , G11C17/06 , G11C17/16 , G11C2213/71 , G11C2213/77 , H01L27/1021 , H01L29/0676
摘要： A nonvolatile memory device includes at least one memory cell which comprises a first diode portion, a second diode portion and an antifuse separating the first diode portion from the second diode portion.
摘要翻译：非易失性存储器件包括至少一个存储单元，其包括第一二极管部分，第二二极管部分和将第一二极管部分与第二二极管部分分开的反熔丝。

8. 发明申请

US20080013364A1 Method of making non-volatile memory cell with embedded antifuse 有权
标题翻译：制造具有嵌入式反熔丝的非易失性存储单元的方法
公开(公告)号：US20080013364A1
公开(公告)日：2008-01-17
申请号：US11819595
申请日：2007-06-28
申请人： Tanmay Kumar , S. Herner
发明人： Tanmay Kumar , S. Herner
IPC分类号： G11C11/00 , H01L21/336
CPC分类号： G11C5/02 , G11C11/39 , G11C11/5692 , G11C17/06 , G11C17/16 , G11C2213/71 , G11C2213/77 , H01L27/1021 , H01L29/0676
摘要： A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell comprising a first diode portion, a second diode portion and an antifuse separating the first diode portion from the second diode portion, and forming a second electrode over the at least one nonvolatile memory cell.
摘要翻译：制造非易失性存储器件的方法包括形成第一电极，形成至少一个非易失性存储单元，该非易失性存储单元包括第一二极管部分，第二二极管部分和将第一二极管部分与第二二极管部分分离的反熔丝，以及形成第二电极在所述至少一个非易失性存储单元上。

9. 发明申请

US20070228414A1 Heterojunction device comprising a semiconductor and a resistivity-switching oxide or nitride 有权
标题翻译：异质结装置包括半导体和电阻率切换氧化物或氮化物
公开(公告)号：US20070228414A1
公开(公告)日：2007-10-04
申请号：US11395419
申请日：2006-03-31
申请人： Tanmay Kumar , S. Herner
发明人： Tanmay Kumar , S. Herner
IPC分类号： H01L29/732
CPC分类号： H01L29/868 , H01L21/84 , H01L27/1021 , H01L27/2409 , H01L29/165 , H01L29/22 , H01L29/267 , H01L29/417 , H01L29/737 , H01L29/8615 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： In the present invention a metal oxide or nitride compound which is a wide-band-gap semiconductor abuts a silicon, germanium, or alloy of silicon and/or germanium of the opposite conductivity type to form a p-n heterojunction. This p-n heterojunction can be used to advantage in various devices. In preferred embodiments, one terminal of a vertically oriented p-i-n heterojunction diode is a metal oxide or nitride layer, while the rest of the diode is formed of a silicon or silicon-germanium resistor; for example a diode may include a heavily doped n-type silicon region, an intrinsic silicon region, and a nickel oxide layer serving as the p-type terminal. Many of these metal oxides and nitrides exhibit resistivity-switching behavior, and such a heterojunction diode can be used in a nonvolatile memory cell, for example in a monolithic three dimensional memory array.
摘要翻译：在本发明中，作为宽带隙半导体的金属氧化物或氮化物化合物与相反导电型的硅和/或锗的硅，锗或合金相接触以形成p-n异质结。该p-n异质结可以用于各种装置中。在优选实施例中，垂直取向的p-i-n异质结二极管的一个端子是金属氧化物或氮化物层，而二极管的其余部分由硅或硅 - 锗电阻器形成; 例如二极管可以包括重掺杂的n型硅区，本征硅区和用作p型端的氧化镍层。这些金属氧化物和氮化物中的许多表现出电阻率切换行为，并且这种异质结二极管可以用在非易失性存储单元中，例如在单片三维存储器阵列中。

10. 发明申请

US20070114508A1 Reversible resistivity-switching metal oxide or nitride layer with added metal 有权
标题翻译：具有添加金属的可逆电阻率开关金属氧化物或氮化物层
公开(公告)号：US20070114508A1
公开(公告)日：2007-05-24
申请号：US11287452
申请日：2005-11-23
申请人： S. Herner , Tanmay Kumar
发明人： S. Herner , Tanmay Kumar
IPC分类号： H01L29/02 , H01L47/00
CPC分类号： H01L45/145 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1625 , H01L45/165 , H01L45/1658 , H01L45/1675
摘要： A layer of resistivity-switching metal oxide or nitride can attain at least two stable resistivity states. Such a layer may be used in a state-change element in a nonvolatile memory cell, storing its data state, for example a “0” or a “1”, in this resistivity state. Including additional metal atoms in a layer of such a resistivity-switching metal oxide or nitride compound decreases the current required to cause switching between resistivity states, reducing power requirements for an array of memory cells storing data in the resistivity state of such a layer. In various embodiments a memory cell may include a layer of resistivity-switching metal oxide or nitride compound with added metal formed in series with another element, such as a diode or a transistor.
摘要翻译：电阻率切换金属氧化物或氮化物层可达到至少两个稳定的电阻率状态。这种层可以用在非易失性存储单元中的状态变化元件中，在该电阻率状态下存储其数据状态，例如“0”或“1”。在这种电阻率切换金属氧化物或氮化物化合物的层中包括额外的金属原子降低了在电阻率状态之间导致切换所需的电流，从而降低了存储在这种层的电阻率状态下的数据的存储单元阵列的功率需求。在各种实施例中，存储器单元可以包括电阻率切换金属氧化物或具有与另一元件（例如二极管或晶体管）串联形成的附加金属的氮化物化合物层。

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