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1. 发明授权

US6041400A Distributed extensible processing architecture for digital signal processing applications 失效
标题翻译：用于数字信号处理应用的分布式可扩展处理架构
公开(公告)号：US6041400A
公开(公告)日：2000-03-21
申请号：US179147
申请日：1998-10-26
申请人： Taner Ozcelik , Shirish Gadre , Yew-Koon Tan
发明人： Taner Ozcelik , Shirish Gadre , Yew-Koon Tan
IPC分类号： G06F15/16 , G06F15/173 , G06F15/80 , G06T1/20 , H04N5/14 , H04N5/44 , G06F19/00
CPC分类号： G06F15/8015
摘要： A circuit arrangement and method utilize a distributed extensible processing architecture to allocate various DSP functions or operations between multiple processing cores disposed on an integrated circuit device. Each processing core includes one or more hardwired datapaths to provide one or more DSP operations. Moreover, each processing core includes a programmable controller that controls the operation of each hardwired datapath via a local computer program executed by the controller. Furthermore, the processing cores are coupled to one another over a communications bus to permit data to be passed between the cores and thereby permit multiple DSP operations to be performed on data supplied to the device.
摘要翻译：电路布置和方法利用分布式可扩展处理架构来分配在集成电路设备上布置的多个处理核之间的各种DSP功能或操作。每个处理核心包括一个或多个硬连线数据路径，以提供一个或多个DSP操作。此外，每个处理核心包括可编程控制器，其通过由控制器执行的本地计算机程序来控制每个硬连线数据路径的操作。此外，处理核通过通信总线彼此耦合，以允许在核之间传递数据，从而允许对提供给设备的数据执行多个DSP操作。

2. 发明授权

US06518985B2 Display unit architecture 失效
标题翻译：显示单元架构
公开(公告)号：US06518985B2
公开(公告)日：2003-02-11
申请号：US09283376
申请日：1999-03-31
申请人： Taner Ozcelik , Shirish Gadre , Tomonari Tohara , Prakash Bare
发明人： Taner Ozcelik , Shirish Gadre , Tomonari Tohara , Prakash Bare
IPC分类号： G09G500
CPC分类号： H04N5/44591 , G09G5/06 , G09G5/14 , G09G2340/10 , H04N5/44504 , H04N21/4316
摘要： Display hardware which manages a plurality, e.g. three, potentially overlapping display windows each having its own pixel values and potentially having its own palette, with no limitation as to the position of the windows relative to each other. This capability is provided at a reduced hardware complexity as compared to a parallel hardware approach, by arranging substantial portions of the hardware in a multiplexed fashion so that the same hardware handles the lookup of palette entries for pixel values, regardless of the currently active window. The hardware is arranged so that it may switch in real time from processing data for one window to processing data for another window, whenever the current display coordinate crosses a window boundary.
摘要翻译：显示硬件，其管理多个，例如三个可能重叠的显示窗口各自具有其自己的像素值并且潜在地具有其自己的调色板，对于窗口相对于彼此的位置没有限制。与并行硬件方法相比，通过以多路复用的方式布置硬件的大部分，使得相同的硬件处理像素值的调色板条目的查找，而不管当前活动的窗口如何，提供了这种能力。硬件被布置为使得当当前显示坐标跨越窗口边界时，它可以实时地从一个窗口的处理数据切换到另一个窗口的处理数据。

3. 发明授权

US6128340A Decoder system with 2.53 frame display buffer 失效
标题翻译：解码器系统具有2.53帧显示缓冲区
公开(公告)号：US6128340A
公开(公告)日：2000-10-03
申请号：US818824
申请日：1997-03-14
申请人： Taner Ozcelik , Shirish Gadre
发明人： Taner Ozcelik , Shirish Gadre
IPC分类号： H04N7/26 , H04N7/32 , H04N7/50
CPC分类号： H04N19/90 , H04N19/127 , H04N19/152 , H04N19/174 , H04N19/423 , H04N19/427 , H04N19/61 , H04N19/50
摘要： A decoder system is provided for decoding an input video signal. A buffer memory hold slices of reconstructed B-pictures for display. The decoder is controlled in accordance with an amount of available memory in the buffer (the amount of available memory in the buffer depends both on how much data has been decoded and also upon how much data has been displayed). In addition, a buffer memory input controller controls into which locations of the buffer memory the slices of the reconstructed B-pictures are stored. As a result, only 2.53 frames of buffer memory are required.
摘要翻译：提供了一种用于解码输入视频信号的解码器系统。缓冲存储器保存用于显示的重构的B图像的切片。解码器根据缓冲器中的可用存储器的量来控制（缓冲器中的可用存储器量取决于已经解码了多少数据，并且还取决于显示了多少数据）。此外，缓冲存储器输入控制器控制缓冲存储器的哪些位置存储重构的B图像的切片。因此，只需要2.53帧的缓冲存储器。

4. 发明授权

US07333545B2 Digital video decoding, buffering and frame-rate converting method and apparatus 有权
标题翻译：数字视频解码，缓冲和帧率转换方法和装置
公开(公告)号：US07333545B2
公开(公告)日：2008-02-19
申请号：US10683508
申请日：2003-10-10
申请人： Cem I. Duruöz , Taner Ozcelik , Yoshinori Shimizu
发明人： Cem I. Duruöz , Taner Ozcelik , Yoshinori Shimizu
IPC分类号： H04N7/12 , G06K9/36
CPC分类号： H04N7/01 , H04N19/102 , H04N19/152 , H04N19/174 , H04N19/176 , H04N19/42 , H04N19/423 , H04N19/427 , H04N19/44 , H04N19/61 , H04N19/85
摘要： A decoder decodes full frame MPEG-2 video by a single method that applies regardless of buffer memory and frame rate conversion considerations. A display control module handles frame rate and field sequence in response to host configuration, trick play command signals, and information in the received bitstream. Pictures are decoded as buffer memory for the decoded pictures becomes available, and picture display attributes are assigned and stored in a table, one string for each decoded picture. Frame rate and field sequence are managed in light of memory constraints, to produce a high quality result without re-decoding data.
摘要翻译：解码器通过采用单一方法解码全帧MPEG-2视频，无论缓冲存储器和帧速率转换考虑如何。显示控制模块响应于主机配置，特技播放命令信号和接收的比特流中的信息来处理帧速率和场序列。图像被解码为用于解码图像的缓冲存储器变得可用，并且图像显示属性被分配并存储在表中，每个解码图像是一个字符串。根据存储器约束来管理帧速率和场序列，以产生高质量的结果而不需要重新解码数据。

5. 发明授权

US06259479B1 Letterbox filter apparatus and method 失效
标题翻译：信箱过滤装置和方法
公开(公告)号：US06259479B1
公开(公告)日：2001-07-10
申请号：US09096321
申请日：1998-06-11
申请人： Shirish C. Gadre , Taner Ozcelik
发明人： Shirish C. Gadre , Taner Ozcelik
IPC分类号： H04N701
CPC分类号： H04N7/0122 , H04N7/0135 , Y10S348/913
摘要： A method and apparatus for changing the number of scan lines in a frame of video data to produce an image represented by the video data that corresponds to a desired aspect ratio. The apparatus includes a pair of finite impulse response filters for processing the decoded chrominance and luminance pixel values stored in memory. The filters permit a plurality of scan lines of chrominance and luminance data to be read and filtered on a continuous basis with any scan line of data being read only once. Thus, the filters provide a very efficient method of providing a frame of a number of output scan lines of chrominance and luminance pixel values that are different from the number of scan lines of chrominance and luminance pixel values in a frame of video data stored in memory.
摘要翻译：一种用于改变视频数据帧中的扫描线数量以产生由对应于所需宽高比的视频数据表示的图像的方法和装置。该装置包括一对用于处理存储在存储器中的解码色度和亮度像素值的有限脉冲响应滤波器。滤波器允许在任何扫描数据线只读一次的情况下连续地读取和滤波多个色度和亮度数据扫描线。因此，滤波器提供了一种非常有效的方法，其提供与存储在存储器中的视频数据的帧中的色度和亮度像素值的扫描线的数量不同的色度和亮度像素值的多个输出扫描线的帧。

6. 发明授权

US5928321A Task and stack manager for digital video decoding 失效
标题翻译：任务和堆栈管理器用于数字视频解码
公开(公告)号：US5928321A
公开(公告)日：1999-07-27
申请号：US866419
申请日：1997-05-30
申请人： Taner Ozcelik , Shirish C. Gadre
发明人： Taner Ozcelik , Shirish C. Gadre
IPC分类号： G06F9/42 , G06F9/48 , G06F13/00
CPC分类号： G06F9/4812 , G06F9/4426 , G06F9/4881
摘要： A reduced instruction set CPU is programmed to provide software-controlled task management, a stack, and to manage virtual instruction memory. The CPU performs a task management procedure in which the CPU repeatedly checks task flags, and if a task flag is set, performs the task associated with the set task flag. If multiple task flags are set, the highest priority task of those associated with set task flags is performed. Whenever a subroutine call is needed, the subroutine call is implemented by calling a stack management routine. The stack management routine retrieves and stores a return address into a location in DRAM identified by a stack pointer, increments the stack pointer, and then executes a CALL instruction, causing program execution to sequence to the desired subroutine. At the end of each subroutine, a RETURN instruction is executed, in response to which, program execution returns to the stack management routine, and the stack management routine decrements the stack pointer, loads the previously-stored return address from a location in DRAM identified by the stack pointer register, and then causes program execution to sequence to the loaded return address. The stack management routine also provides virtual instruction memory management, by determining whether a routine is resident in the on-chip instruction memory available to the RISC CPU prior to calling or returning to the routine. If not, the virtual instruction memory management routine transfers the desired routine from off-chip DRAM into the on-chip instruction memory, and then executes the call or return.
摘要翻译：精简指令集CPU被编程为提供软件控制的任务管理，堆栈和管理虚拟指令存储器。 CPU执行任务管理过程，其中CPU重复检查任务标志，并且如果设置了任务标志，则执行与设置任务标志相关联的任务。如果设置了多个任务标志，则执行与设置任务标志相关联的最高优先级任务。每当需要子程序调用时，通过调用堆栈管理例程来实现子程序调用。堆栈管理例程检索并将返回地址存储到由堆栈指针识别的DRAM中的位置，增加堆栈指针，然后执行CALL指令，使程序执行顺序到期望的子程序。在每个子程序结束时，执行RETURN指令，响应于此程序执行返回到堆栈管理例程，并且堆栈管理例程减小堆栈指针，从DRAM中识别的位置加载先前存储的返回地址通过堆栈指针寄存器，然后使程序执行顺序到加载的返回地址。在调用或返回到例程之前，栈管理例程还提供虚拟指令存储器管理，通过确定一个例程是否驻留在可用于RISC CPU的片上指令存储器中。如果不是，虚拟指令存储器管理例程将期望的例程从片外DRAM传送到片上指令存储器，然后执行调用或返回。

7. 发明授权

US5903311A Run level pair buffering for fast variable length decoder circuit 失效
标题翻译：用于快速可变长度解码器电路的运行电平对缓冲
公开(公告)号：US5903311A
公开(公告)日：1999-05-11
申请号：US866701
申请日：1997-05-30
申请人： Taner Ozcelik , Shirish C. Gadre , Moshe Bublil , Sabyasachi Dutta , Subroto Bose
发明人： Taner Ozcelik , Shirish C. Gadre , Moshe Bublil , Sabyasachi Dutta , Subroto Bose
IPC分类号： G06T9/00 , H03M7/40 , H04N7/26 , H04N7/50 , A04N7/30
CPC分类号： H03M7/40 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/61 , H04N19/13 , H04N19/91
摘要： A decoding circuit for decoding (or decompressing) compressed video data includes an RL circuit, such as MPEG encoded video data. The RL circuit includes a buffer memory for storing run-level pairs during the decoding process. Because the buffer memory in the RL circuit can store ran-level pairs, Huffman-decoding and header decoding, performed by a variable length decoding (VLD) circuit, is decoupled from inverse discrete transform decoding, performed by an IDCT circuit. This decoupling speeds up the decoding pipeline by allowing more continuous operation by both the VLD and IDCT circuits.
摘要翻译：用于解码（或解压缩）压缩视频数据的解码电路包括诸如MPEG编码视频数据的RL电路。 RL电路包括用于在解码过程期间存储运行电平对的缓冲存储器。由于RL电路中的缓冲存储器可以存储运行电平对，由可变长度解码（VLD）电路执行的霍夫曼解码和报头解码与由IDCT电路执行的反离散变换解码分离。这种去耦通过允许VLD和IDCT电路的更连续的操作来加速解码流水线。

8. 发明授权

US06487642B1 Command manager 失效
标题翻译：指挥经理
公开(公告)号：US06487642B1
公开(公告)日：2002-11-26
申请号：US09177214
申请日：1998-10-22
申请人： Chem I. Duruoz , Taner Ozcelik , Pattabiraman Subramanian
发明人： Chem I. Duruoz , Taner Ozcelik , Pattabiraman Subramanian
IPC分类号： G06F1208
CPC分类号： G06F9/45512
摘要： This command manager is an Application Programming Interface (API) which provides a method for receiving and buffering commands from the host so that the host need not wait for the command to be executed, sorting these commands so that time-critical commands are executed appropriately, scheduling nonexclusive commands to the appropriate time, allowing for the prioritization of nonexclusive commands, providing macro command algorithms to allow for simplified interface with the host, providing micro command pass-through to provide an API with flexibility, and provide acknowledgment capability to the host when the command is executed.
摘要翻译：该命令管理器是一种应用编程接口（API），它提供了一种从主机接收和缓存命令的方法，使得主机不需要等待命令执行，对这些命令进行排序，以便适当执行时间关键的命令，将非排他性命令调度到适当的时间，允许非排他性命令的优先级，提供宏命令算法以允许与主机的简化接口，提供微命令传递以提供具有灵活性的API，并且向主机提供确认能力该命令被执行。

9. 发明授权

US06449311B1 Methods and apparatus for error concealment utilizing temporal domain motion vector estimation 失效
标题翻译：利用时域运动矢量估计的误差隐藏方法和装置
公开(公告)号：US06449311B1
公开(公告)日：2002-09-10
申请号：US09546782
申请日：2000-04-11
申请人： Taner Ozcelik , Gong-san Yu , Shrish C. Gadre
发明人： Taner Ozcelik , Gong-san Yu , Shrish C. Gadre
IPC分类号： H04N712
CPC分类号： H04N19/895 , H04N5/21 , H04N19/51 , H04N19/56
摘要： A method and apparatus for concealing errors during decoding of a video bit stream utilize estimates, if possible, motion vectors in the temporal domain. If estimation in the temporal domain is not possible, motion vectors are estimated in the spatial domain. A macroblock is then estimated based upon the estimated motion vector. If estimation in the spatial domain is not possible, macroblock estimation is made without the use of an estimated motion vector.
摘要翻译：用于在视频比特流的解码期间隐藏错误的方法和装置利用估计（如果可能的话）在时域中的运动矢量。如果在时域中的估计是不可能的，则在空间域中估计运动矢量。然后基于估计的运动矢量来估计宏块。如果空间域中的估计是不可能的，则在不使用估计的运动矢量的情况下进行宏块估计。

10. 发明授权

US6088047A Motion compensated digital video decoding with buffered picture storage memory map 失效
标题翻译：运动补偿数字视频解码与缓冲图像存储器映射
公开(公告)号：US6088047A
公开(公告)日：2000-07-11
申请号：US1129
申请日：1997-12-30
申请人： Subroto Bose , Shirish C. Gadre , Taner Ozcelik , Edward J. Paluch , Syed Reza
发明人： Subroto Bose , Shirish C. Gadre , Taner Ozcelik , Edward J. Paluch , Syed Reza
IPC分类号： H04N7/26 , H04N7/36 , H04N7/50 , G06F17/76 , H04N9/64
CPC分类号： H04N19/433 , H04N19/174 , H04N19/423 , H04N19/51 , H04N19/61
摘要： A digital video presentation system is provided with hardware and software logic for mapping the picture data into buffer memory in a way that permits both the reading of motion vector compensated macroblocks of data and the reading of horizontal picture wide scan lines with a low number of memory page crossings. Preferably, the memory is a plurality of rows, for example 16 rows, wide. Preferably, 16 lines of 8-pixel (two 32 pixel wide column) line segments of 8.times.8 pixel blocks are stored in consecutive storage locations followed by the consecutive storage vertically adjacent line segments until one line segment is stored in each logical row of the memory. Then the next horizontally adjacent set of line segments of similarly stored until the right boundary of the picture is reached, then the each additional row of 16 lines of the picture similarly are stored until the bottom of the picture is reached. Each 16.times.16 pixel macroblock of data is stored on a single page; preferably, two horizontally adjacent macroblocks are stored on one page of memory. Each line of the picture is stored in contiguous locations on the same row of the memory. The motion compensation logic interprets motion vectors from the incoming data and calculates addresses for a macroblock of picture data by separating read commands into separate commands where a page boundary divides the macroblock into vertically adjacent rectangles. Memory controller logic further divides such rectangles where they cross boundaries between horizontally adjacent pages of the memory. One fixed address increment of 8 hex steps from line segment to vertically adjacent line segment while another fixed address increment of 80 hex steps horizontally from one 8 pixel line segment to the next, such as across a scan line of the picture.
摘要翻译：数字视频呈现系统具有用于将图像数据映射到缓冲存储器中的硬件和软件逻辑，其方式是允许读取运动矢量补偿的数据宏块和读取具有低数量存储器的水平图像宽扫描线页面交叉。优选地，存储器是多行，例如16行宽。优选地，8×8像素块的8行（两个32像素宽列）行的16行存储在连续的存储位置中，随后是垂直相邻的线段的连续存储，直到在存储器的每个逻辑行中存储一个线段。然后类似地存储下一个水平相邻的线段组，直到图像的右边界达到，然后类似地存储图像的16行的每个附加行直到图像的底部到达。数据的每个16×16像素宏块存储在单个页面上; 优选地，两个水平相邻的宏块存储在一页存储器上。图片的每行都存储在存储器的同一行的连续位置。运动补偿逻辑解释来自输入数据的运动矢量，并通过将读取命令分离成单独的命令来计算图像数据的宏块的地址，其中页边界将宏块划分成垂直相邻的矩形。存储器控制器逻辑进一步划分这样的矩形，它们跨越存储器的水平相邻页面之间的边界。一个固定的地址增量从线段到垂直相邻的线段8个十六进制步长，而另一个固定地址增量为80个十六进制水平从一个8像素线段到下一个，例如跨越图像的扫描线。

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