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1. 发明授权

US06518985B2 Display unit architecture 失效
标题翻译：显示单元架构
公开(公告)号：US06518985B2
公开(公告)日：2003-02-11
申请号：US09283376
申请日：1999-03-31
申请人： Taner Ozcelik , Shirish Gadre , Tomonari Tohara , Prakash Bare
发明人： Taner Ozcelik , Shirish Gadre , Tomonari Tohara , Prakash Bare
IPC分类号： G09G500
CPC分类号： H04N5/44591 , G09G5/06 , G09G5/14 , G09G2340/10 , H04N5/44504 , H04N21/4316
摘要： Display hardware which manages a plurality, e.g. three, potentially overlapping display windows each having its own pixel values and potentially having its own palette, with no limitation as to the position of the windows relative to each other. This capability is provided at a reduced hardware complexity as compared to a parallel hardware approach, by arranging substantial portions of the hardware in a multiplexed fashion so that the same hardware handles the lookup of palette entries for pixel values, regardless of the currently active window. The hardware is arranged so that it may switch in real time from processing data for one window to processing data for another window, whenever the current display coordinate crosses a window boundary.
摘要翻译：显示硬件，其管理多个，例如三个可能重叠的显示窗口各自具有其自己的像素值并且潜在地具有其自己的调色板，对于窗口相对于彼此的位置没有限制。与并行硬件方法相比，通过以多路复用的方式布置硬件的大部分，使得相同的硬件处理像素值的调色板条目的查找，而不管当前活动的窗口如何，提供了这种能力。硬件被布置为使得当当前显示坐标跨越窗口边界时，它可以实时地从一个窗口的处理数据切换到另一个窗口的处理数据。

2. 发明授权

US6041400A Distributed extensible processing architecture for digital signal processing applications 失效
标题翻译：用于数字信号处理应用的分布式可扩展处理架构
公开(公告)号：US6041400A
公开(公告)日：2000-03-21
申请号：US179147
申请日：1998-10-26
申请人： Taner Ozcelik , Shirish Gadre , Yew-Koon Tan
发明人： Taner Ozcelik , Shirish Gadre , Yew-Koon Tan
IPC分类号： G06F15/16 , G06F15/173 , G06F15/80 , G06T1/20 , H04N5/14 , H04N5/44 , G06F19/00
CPC分类号： G06F15/8015
摘要： A circuit arrangement and method utilize a distributed extensible processing architecture to allocate various DSP functions or operations between multiple processing cores disposed on an integrated circuit device. Each processing core includes one or more hardwired datapaths to provide one or more DSP operations. Moreover, each processing core includes a programmable controller that controls the operation of each hardwired datapath via a local computer program executed by the controller. Furthermore, the processing cores are coupled to one another over a communications bus to permit data to be passed between the cores and thereby permit multiple DSP operations to be performed on data supplied to the device.
摘要翻译：电路布置和方法利用分布式可扩展处理架构来分配在集成电路设备上布置的多个处理核之间的各种DSP功能或操作。每个处理核心包括一个或多个硬连线数据路径，以提供一个或多个DSP操作。此外，每个处理核心包括可编程控制器，其通过由控制器执行的本地计算机程序来控制每个硬连线数据路径的操作。此外，处理核通过通信总线彼此耦合，以允许在核之间传递数据，从而允许对提供给设备的数据执行多个DSP操作。

3. 发明授权

US6128340A Decoder system with 2.53 frame display buffer 失效
标题翻译：解码器系统具有2.53帧显示缓冲区
公开(公告)号：US6128340A
公开(公告)日：2000-10-03
申请号：US818824
申请日：1997-03-14
申请人： Taner Ozcelik , Shirish Gadre
发明人： Taner Ozcelik , Shirish Gadre
IPC分类号： H04N7/26 , H04N7/32 , H04N7/50
CPC分类号： H04N19/90 , H04N19/127 , H04N19/152 , H04N19/174 , H04N19/423 , H04N19/427 , H04N19/61 , H04N19/50
摘要： A decoder system is provided for decoding an input video signal. A buffer memory hold slices of reconstructed B-pictures for display. The decoder is controlled in accordance with an amount of available memory in the buffer (the amount of available memory in the buffer depends both on how much data has been decoded and also upon how much data has been displayed). In addition, a buffer memory input controller controls into which locations of the buffer memory the slices of the reconstructed B-pictures are stored. As a result, only 2.53 frames of buffer memory are required.
摘要翻译：提供了一种用于解码输入视频信号的解码器系统。缓冲存储器保存用于显示的重构的B图像的切片。解码器根据缓冲器中的可用存储器的量来控制（缓冲器中的可用存储器量取决于已经解码了多少数据，并且还取决于显示了多少数据）。此外，缓冲存储器输入控制器控制缓冲存储器的哪些位置存储重构的B图像的切片。因此，只需要2.53帧的缓冲存储器。

4. 发明授权

US06741794B1 System and method for flexibly blending multiple image planes in a video device 失效
标题翻译：用于在视频设备中灵活混合多个图像平面的系统和方法
公开(公告)号：US06741794B1
公开(公告)日：2004-05-25
申请号：US09240098
申请日：1999-01-29
申请人： Tetsuji Sumioka , Shirish Gadre , Tomonari Tohara , Fay Massian
发明人： Tetsuji Sumioka , Shirish Gadre , Tomonari Tohara , Fay Massian
IPC分类号： H04N591
CPC分类号： H04N5/44504 , H04N5/073 , H04N5/45 , H04N5/85 , H04N5/9305 , H04N21/42653 , H04N21/4307 , H04N21/4312
摘要： A system and method for flexibly blending multiple image planes in a video device comprises a timing controller configured to generate adjusted synchronization signals for pretiming multiple video image planes. The timing controller preferably generates the adjusted synchronization signals in response to programmable delay signals and a master synchronization signal. A blender device then receives and flexibly combines the multiple video image planes to generate a synchronized composite blender output signal. The blender preferably includes a selectable pseudo-output signal that may be routed through an external processing device, and returned as a feedback loop to an external input of the blender device.
摘要翻译：用于在视频设备中灵活地混合多个图像平面的系统和方法包括定时控制器，其被配置为产生用于对多个视频图像平面进行预处理的经调整的同步信号。定时控制器优选地响应于可编程延迟信号和主同步信号产生经调整的同步信号。然后，混合器装置接收并灵活地组合多个视频图像平面以产生同步的复合搅拌器输出信号。混合器优选地包括可选择的伪输出信号，其可以通过外部处理装置路由，并作为反馈回路返回到搅拌器装置的外部输入。

5. 发明授权

US09111368B1 Pipelined L2 cache for memory transfers for a video processor 有权
标题翻译：流水线L2缓存用于视频处理器的存储器传输
公开(公告)号：US09111368B1
公开(公告)日：2015-08-18
申请号：US11267606
申请日：2005-11-04
申请人： Ashish Karandikar , Shirish Gadre , Franciscus W. Sijstermans , Zhiqiang Jonathan Su
发明人： Ashish Karandikar , Shirish Gadre , Franciscus W. Sijstermans , Zhiqiang Jonathan Su
IPC分类号： G09G5/36 , G06T1/60 , G06F12/08
CPC分类号： G06T1/60 , G06F3/14 , G06F9/3851 , G06F9/3887 , G06F12/0877 , G06T1/20 , G09G5/37 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/61 , H04N19/82 , H04N19/85 , H04N19/86
摘要： A method for using a pipelined L2 cache to implement memory transfers for a video processor. The method includes accessing a queue of read requests from a video processor. For each of the read requests, a determination is made as to whether there is a cache line hit corresponding to the request. For each cache line miss, a cache line slot is allocated to store a new cache line responsive to the cache line miss. An in-order set of cache lines is output to the video processor responsive to the queue of read requests.
摘要翻译：一种使用流水线L2高速缓存来实现视频处理器的存储器传输的方法。该方法包括从视频处理器访问读请求队列。对于每个读取请求，确定是否存在对应于该请求的高速缓存行命中。对于每个高速缓存行缺失，分配高速缓存行时隙以响应于高速缓存行缺失来存储新的高速缓存行。响应于读取请求队列，将一系列高速缓存行输出到视频处理器。

6. 发明授权

US08997103B2 N-way memory barrier operation coalescing 有权
标题翻译： N路记忆障碍操作合并
公开(公告)号：US08997103B2
公开(公告)日：2015-03-31
申请号：US13441785
申请日：2012-04-06
申请人： Shirish Gadre , Charles McCarver , Anjana Rajendran , Omkar Paranjape , Steven James Heinrich
发明人： Shirish Gadre , Charles McCarver , Anjana Rajendran , Omkar Paranjape , Steven James Heinrich
IPC分类号： G06F9/46 , G06F1/04 , G06F7/00 , G06F9/38 , G06F9/30 , G06F9/52
CPC分类号： G06F9/3834 , G06F9/3004 , G06F9/30087 , G06F9/3851 , G06F9/522
摘要： One embodiment sets forth a technique for N-way memory barrier operation coalescing. When a first memory barrier is received for a first thread group execution of subsequent memory operations for the first thread group are suspended until the first memory barrier is executed. Subsequent memory barriers for different thread groups may be coalesced with the first memory barrier to produce a coalesced memory barrier that represents memory barrier operations for multiple thread groups. When the coalesced memory barrier is being processed, execution of subsequent memory operations for the different thread groups is also suspended. However, memory operations for other thread groups that are not affected by the coalesced memory barrier may be executed.
摘要翻译：一个实施例提出了一种用于N路存储器屏障操作合并的技术。当为第一线程组接收到第一存储器障碍时，对于第一线程组的后续存储器操作的执行被暂停，直到执行第一存储器障碍。不同线程组的后续内存障碍可以与第一存储器屏障合并，以产生代表多个线程组的存储器屏障操作的聚结存储器屏障。当合并的存储器障碍被处理时，对于不同的线程组的后续存储器操作的执行也被暂停。然而，可以执行不受聚结的存储器屏障影响的其他线程组的存储器操作。

7. 发明授权

US08736623B1 Programmable DMA engine for implementing memory transfers and video processing for a video processor 有权
标题翻译：用于实现视频处理器的存储器传输和视频处理的可编程DMA引擎
公开(公告)号：US08736623B1
公开(公告)日：2014-05-27
申请号：US11267777
申请日：2005-11-04
申请人： Stephen D. Lew , Shirish Gadre , Ashish Karandikar , Franciscus W. Sijstermans
发明人： Stephen D. Lew , Shirish Gadre , Ashish Karandikar , Franciscus W. Sijstermans
IPC分类号： G06T1/00
CPC分类号： G06T1/60 , G06F3/14 , G06F9/3851 , G06F9/3887 , G06F12/0877 , G06T1/20 , G09G5/37 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/61 , H04N19/82 , H04N19/85 , H04N19/86
摘要： A method for using a programmable DMA engine to implement memory transfers and video processing for a video processor. A DMA control program is configured for controlling DMA memory transfers between a frame buffer memory and a video processor. The DMA control program is stored in the DMA engine. A DMA request can be received from the video processor. The DMA control program is executable to implement the DMA request for the video processor. The DMA engine is operable to execute low-level command for accessing the frame buffer memory to implement a high-level command.
摘要翻译：一种使用可编程DMA引擎来实现视频处理器的存储器传输和视频处理的方法。 DMA控制程序被配置用于控制帧缓冲存储器和视频处理器之间的DMA存储器传输。 DMA控制程序存储在DMA引擎中。可以从视频处理器接收DMA请求。 DMA控制程序可执行以实现视频处理器的DMA请求。 DMA引擎可操作来执行用于访问帧缓冲存储器的低级命令以实现高级命令。

8. 发明申请

US20130212364A1 PRE-SCHEDULED REPLAYS OF DIVERGENT OPERATIONS 审中-公开
标题翻译：预先安排的重复操作
公开(公告)号：US20130212364A1
公开(公告)日：2013-08-15
申请号：US13370173
申请日：2012-02-09
申请人： Michael FETTERMAN , Stewart Glenn Carlton , Jack Hilaire Choquette , Shirish Gadre , Olivier Giroux , Douglas J. Hahn , Steven James Heinrich , Eric Lyell Hill , Charles McCarver , Omkar Paranjape , Anjana Rajendran , Rajeshwaran Selvanesan
发明人： Michael FETTERMAN , Stewart Glenn Carlton , Jack Hilaire Choquette , Shirish Gadre , Olivier Giroux , Douglas J. Hahn , Steven James Heinrich , Eric Lyell Hill , Charles McCarver , Omkar Paranjape , Anjana Rajendran , Rajeshwaran Selvanesan
IPC分类号： G06F9/38 , G06F9/312
CPC分类号： G06F9/3861 , G06F9/3836 , G06F9/3851 , G06F9/3887
摘要： One embodiment of the present disclosure sets forth an optimized way to execute pre-scheduled replay operations for divergent operations in a parallel processing subsystem. Specifically, a streaming multiprocessor (SM) includes a multi-stage pipeline configured to insert pre-scheduled replay operations into a multi-stage pipeline. A pre-scheduled replay unit detects whether the operation associated with the current instruction is accessing a common resource. If the threads are accessing data which are distributed across multiple cache lines, then the pre-scheduled replay unit inserts pre-scheduled replay operations behind the current instruction. The multi-stage pipeline executes the instruction and the associated pre-scheduled replay operations sequentially. If additional threads remain unserviced after execution of the instruction and the pre-scheduled replay operations, then additional replay operations are inserted via the replay loop, until all threads are serviced. One advantage of the disclosed technique is that divergent operations requiring one or more replay operations execute with reduced latency.
摘要翻译：本公开的一个实施例阐述了在并行处理子系统中执行用于发散操作的预先安排的重播操作的优化方式。具体地，流式多处理器（SM）包括多级流水线，其被配置为将预先安排的重播操作插入到多级流水线中。预先安排的重播单元检测与当前指令相关联的操作是否正在访问公共资源。如果线程正在访问分布在多个高速缓存线上的数据，则预先安排的重播单元在当前指令后面插入预先安排的重放操作。多级流水线顺序执行指令和相关的预先安排的重播操作。如果附加线程在执行指令和预先安排的重放操作之后保持未被接受，则通过重放循环插入附加的重放操作，直到对所有线程进行服务。所公开技术的一个优点是需要一个或多个重放操作的发散操作以较低的等待时间执行。

9. 发明授权

US08493396B2 Multidimensional datapath processing in a video processor 有权
标题翻译：视频处理器中的多维数据路径处理
公开(公告)号：US08493396B2
公开(公告)日：2013-07-23
申请号：US11267638
申请日：2005-11-04
申请人： Ashish Karandikar , Shirish Gadre , Stephen D. Lew , Christopher T. Cheng
发明人： Ashish Karandikar , Shirish Gadre , Stephen D. Lew , Christopher T. Cheng
IPC分类号： G06F12/02
CPC分类号： G06T1/60 , G06F3/14 , G06F9/3851 , G06F9/3887 , G06F12/0877 , G06T1/20 , G09G5/37 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/61 , H04N19/82 , H04N19/85 , H04N19/86
摘要： A multidimensional datapath processing system for a video processor for executing video processing operations. The video processor includes a scalar execution unit configured to execute scalar video processing operations and a vector execution unit configured to execute vector video processing operations. A data store memory is included for storing data for the vector execution unit. The data store memory includes a plurality of tiles having symmetrical bank data structures arranged in an array. The bank data structures are configured to support accesses to different tiles of each bank.
摘要翻译：一种用于视频处理器执行视频处理操作的多维数据路径处理系统。视频处理器包括被配置为执行标量视频处理操作的标量执行单元和被配置为执行向量视频处理操作的向量执行单元。包括用于存储矢量执行单元的数据的数据存储器。数据存储存储器包括以阵列排列的对称库数据结构的多个瓦片。银行数据结构被配置为支持对每个银行的不同瓦片的访问。

10. 发明授权

US07099569B2 Method and apparatus for efficiently allocating memory when switching between DVD audio and DVD video 失效
公开(公告)号：US07099569B2
公开(公告)日：2006-08-29
申请号：US10074773
申请日：2002-02-11
申请人： Shirish Gadre , Fang-Chuan Wu , Elif Albuz , Raman Subramanian
发明人： Shirish Gadre , Fang-Chuan Wu , Elif Albuz , Raman Subramanian
IPC分类号： H04N5/85
CPC分类号： H04N5/9203 , G11B20/10527 , G11B27/105 , G11B2020/10537 , G11B2020/1062 , G11B2220/2562 , H04N5/85
摘要： When switching between a DVD-video mode and a DVD-audio mode in a DVD-A/V player, a current video frame is stored in a current display buffer portion of the memory during the DVD-video mode. The DVD-A/V player is paused in the DVD-video mode and set in the DVD-audio mode. If it is determined that the current display buffer portion of the memory is a reserved display buffer portion of the memory, then the current video frame is copied to a reconstructed display buffer portion of the memory. At least the current display portion of the memory is designated as an ASV buffer and a frame buffer management scheme is changed so as to preserve the ASV buffer.

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