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1. 发明授权

US6088047A Motion compensated digital video decoding with buffered picture storage memory map 失效
标题翻译：运动补偿数字视频解码与缓冲图像存储器映射
公开(公告)号：US6088047A
公开(公告)日：2000-07-11
申请号：US1129
申请日：1997-12-30
申请人： Subroto Bose , Shirish C. Gadre , Taner Ozcelik , Edward J. Paluch , Syed Reza
发明人： Subroto Bose , Shirish C. Gadre , Taner Ozcelik , Edward J. Paluch , Syed Reza
IPC分类号： H04N7/26 , H04N7/36 , H04N7/50 , G06F17/76 , H04N9/64
CPC分类号： H04N19/433 , H04N19/174 , H04N19/423 , H04N19/51 , H04N19/61
摘要： A digital video presentation system is provided with hardware and software logic for mapping the picture data into buffer memory in a way that permits both the reading of motion vector compensated macroblocks of data and the reading of horizontal picture wide scan lines with a low number of memory page crossings. Preferably, the memory is a plurality of rows, for example 16 rows, wide. Preferably, 16 lines of 8-pixel (two 32 pixel wide column) line segments of 8.times.8 pixel blocks are stored in consecutive storage locations followed by the consecutive storage vertically adjacent line segments until one line segment is stored in each logical row of the memory. Then the next horizontally adjacent set of line segments of similarly stored until the right boundary of the picture is reached, then the each additional row of 16 lines of the picture similarly are stored until the bottom of the picture is reached. Each 16.times.16 pixel macroblock of data is stored on a single page; preferably, two horizontally adjacent macroblocks are stored on one page of memory. Each line of the picture is stored in contiguous locations on the same row of the memory. The motion compensation logic interprets motion vectors from the incoming data and calculates addresses for a macroblock of picture data by separating read commands into separate commands where a page boundary divides the macroblock into vertically adjacent rectangles. Memory controller logic further divides such rectangles where they cross boundaries between horizontally adjacent pages of the memory. One fixed address increment of 8 hex steps from line segment to vertically adjacent line segment while another fixed address increment of 80 hex steps horizontally from one 8 pixel line segment to the next, such as across a scan line of the picture.
摘要翻译：数字视频呈现系统具有用于将图像数据映射到缓冲存储器中的硬件和软件逻辑，其方式是允许读取运动矢量补偿的数据宏块和读取具有低数量存储器的水平图像宽扫描线页面交叉。优选地，存储器是多行，例如16行宽。优选地，8×8像素块的8行（两个32像素宽列）行的16行存储在连续的存储位置中，随后是垂直相邻的线段的连续存储，直到在存储器的每个逻辑行中存储一个线段。然后类似地存储下一个水平相邻的线段组，直到图像的右边界达到，然后类似地存储图像的16行的每个附加行直到图像的底部到达。数据的每个16×16像素宏块存储在单个页面上; 优选地，两个水平相邻的宏块存储在一页存储器上。图片的每行都存储在存储器的同一行的连续位置。运动补偿逻辑解释来自输入数据的运动矢量，并通过将读取命令分离成单独的命令来计算图像数据的宏块的地址，其中页边界将宏块划分成垂直相邻的矩形。存储器控制器逻辑进一步划分这样的矩形，它们跨越存储器的水平相邻页面之间的边界。一个固定的地址增量从线段到垂直相邻的线段8个十六进制步长，而另一个固定地址增量为80个十六进制水平从一个8像素线段到下一个，例如跨越图像的扫描线。

2. 发明授权

US06215822B1 Motion compensated digital video decoding and buffer memory addressing therefor 失效
标题翻译：运动补偿数字视频解码和缓冲存储器寻址
公开(公告)号：US06215822B1
公开(公告)日：2001-04-10
申请号：US09001122
申请日：1997-12-30
申请人： Subroto Bose , Shirish C. Gadre , Taner Ozcelik , Syed Reza
发明人： Subroto Bose , Shirish C. Gadre , Taner Ozcelik , Syed Reza
IPC分类号： H04B166
CPC分类号： H04N19/433 , H04N19/174 , H04N19/187 , H04N19/423 , H04N19/51 , H04N19/61
摘要： A digital video presentation system is provided with hardware and software logic for mapping the picture data into buffer memory in a way that permits both the reading of motion vector compensated macroblocks of data and the reading of horizontal picture wide scan lines with a low number of memory page crossings. Preferably, the memory is a plurality of rows, for example 16 rows, wide. Preferably, 16 lines of 8-pixel (two 32 pixel wide column) line segments of 8×8 pixel blocks are stored in consecutive storage locations followed by the consecutive storage vertically adjacent line segments until one line segment is stored in each logical row of the memory. Then the next horizontally adjacent set of line segments of similarly stored until the right boundary of the picture is reached, then the each additional row of 16 lines of the picture similarly are stored until the bottom of the picture is reached. Each 16×16 pixel macroblock of data is stored on a single page; preferably, two horizontally adjacent macroblocks are stored on one page of memory. Each line of the picture is stored in contiguous locations on the same row of the memory. The motion compensation logic interprets motion vectors from the incoming data and calculates addresses for a macroblock of picture data by separating read commands into separate commands where a page boundary divides the macroblock into vertically adjacent rectangles. Memory controller logic further divides such rectangles where they cross boundaries between horizontally adjacent pages of the memory. One fixed address increment of 8 hex steps from line segment to vertically adjacent line segment while another fixed address increment of 80 hex steps horizontally from one 8 pixel line segment to the next, such as across a scan line of the picture.
摘要翻译：数字视频呈现系统具有用于将图像数据映射到缓冲存储器中的硬件和软件逻辑，其方式是允许读取运动矢量补偿的数据宏块和读取具有低数量存储器的水平图像宽扫描线页面交叉。优选地，存储器是多行，例如16行宽。优选地，8×8像素块的8行（两个32像素宽列）行的16行存储在连续的存储位置中，随后是垂直相邻的线段的连续存储，直到在存储器的每个逻辑行中存储一个线段。然后，相似地存储直到图像的右边界为止的下一个水平相邻的线段集合，则类似地存储图像的16行的每个附加行直到图像的底部到达。数据的每个16×16像素宏块存储在单个页面上; 优选地，两个水平相邻的宏块存储在一页存储器上。图片的每行都存储在存储器的同一行的连续位置。运动补偿逻辑解释来自输入数据的运动矢量，并通过将读取命令分离成单独的命令来计算图像数据的宏块的地址，其中页边界将宏块划分成垂直相邻的矩形。存储器控制器逻辑进一步划分这样的矩形，它们跨越存储器的水平相邻页面之间的边界。一个固定的地址增量从线段到垂直相邻的线段8个十六进制步长，而另一个固定地址增量为80个十六进制水平从一个8像素线段到下一个，例如跨越图像的扫描线。

3. 发明申请

US20050221288A1 Variant tat proteins and methods for use thereof 失效
标题翻译：变体tat蛋白及其使用方法
公开(公告)号：US20050221288A1
公开(公告)日：2005-10-06
申请号：US10505265
申请日：2003-02-21
申请人： Michael Mathews , Tsafi Pe'ery , Syed Reza
发明人： Michael Mathews , Tsafi Pe'ery , Syed Reza
IPC分类号： A61K38/16 , A61K39/00 , A61K39/21 , C07H21/02 , C07K14/16 , C12N15/867 , C12Q1/70
CPC分类号： C07K14/005 , A61K38/162 , A61K39/00 , A61K2039/505 , C07K2319/01 , C07K2319/71 , C12N2740/16322
摘要： Variants of the HIV-1 Tat protein exhibiting higher transcriptional activation and stronger P-TEFb binding than wild-type Tat are provided. In addition variants that can inhibit transcription activation by wild-type Tat are provided. Nucleic acid sequences encoding these variants, vectors and host cells for expression of these variants, and antibodies raised against these variants are also provided. In addition, methods for use of these variants and compositions containing these variants as research tools, as diagnostic tools and in the treatment of viral infections are provided.
摘要翻译：提供了具有比野生型Tat更高的转录激活和更强的P-TEFb结合的HIV-1 Tat蛋白的变体。此外，提供可以抑制野生型Tat的转录激活的变体。还提供了编码这些变体的核酸序列，用于表达这些变体的载体和宿主细胞，以及针对这些变体产生的抗体。此外，提供了使用这些变体的方法和含有这些变体作为研究工具的组合物，作为诊断工具和用于治疗病毒感染的方法。

4. 发明授权

US07244814B2 Variant Tat proteins and methods for use thereof 失效
标题翻译：变体Tat蛋白质及其使用方法
公开(公告)号：US07244814B2
公开(公告)日：2007-07-17
申请号：US10505265
申请日：2003-02-21
申请人： Michael B. Mathews , Tsafi Pe'ery , Syed Reza
发明人： Michael B. Mathews , Tsafi Pe'ery , Syed Reza
IPC分类号： C07K5/00 , A61K39/21
CPC分类号： C07K14/005 , A61K38/162 , A61K39/00 , A61K2039/505 , C07K2319/01 , C07K2319/71 , C12N2740/16322
摘要： Variants of the HIV-1 Tat protein exhibiting higher transcriptional activation and stronger P-TEFb binding than wild-type Tat are provided. In addition variants that can inhibit transcription activation by wild-type Tat are provided. Nucleic acid sequences encoding these variants, vectors and host cells for expression of these variants, and antibodies raised against these variants are also provided. In addition, methods for use of these variants and compositions containing these variants as research tools, as diagnostic tools and in the treatment of viral infections are provided.
摘要翻译：提供了具有比野生型Tat更高的转录激活和更强的P-TEFb结合的HIV-1 Tat蛋白的变体。此外，提供可以抑制野生型Tat的转录激活的变体。还提供了编码这些变体的核酸序列，用于表达这些变体的载体和宿主细胞，以及针对这些变体产生的抗体。此外，提供了使用这些变体的方法和含有这些变体作为研究工具的组合物，作为诊断工具和用于治疗病毒感染的方法。

5. 发明授权

US06591359B1 Speculative renaming of data-processor registers 有权
标题翻译：将虚拟寄存器规范映射到流水线处理器中的物理寄存器
公开(公告)号：US06591359B1
公开(公告)日：2003-07-08
申请号：US09223843
申请日：1998-12-31
申请人： David Hass , Michael P. Corwin , Luke E. Girard , Ken Arora , Harshvardhan Sharangpani , Syed Reza
发明人： David Hass , Michael P. Corwin , Luke E. Girard , Ken Arora , Harshvardhan Sharangpani , Syed Reza
IPC分类号： G06F934
CPC分类号： G06F9/3863 , G06F9/384 , G06F9/3842
摘要： A pipelined data processor has instructions at different stages of execution. Some of the instructions specify virtual addresses into a file of registers having physical addresses. A speculative translator maps the virtual registers of an instruction at one pipeline stage into physical registers for speculative use by the instruction at a later pipeline stage. The registers have multiple differently translated regions. Failure of speculative renaming reverts to an archive copy of renaming data.
摘要翻译：流水线数据处理器具有不同执行阶段的指令。一些指令将虚拟地址指定为具有物理地址的寄存器的文件。推测翻译器将一个流水线阶段的指令的虚拟寄存器映射到物理寄存器，以便在稍后的流水线阶段由指令进行投机使用。寄存器有多个不同的翻译区域。投机重命名失败恢复到重命名数据的归档副本。

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