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1. 发明授权

US08149904B2 Asymmetric digital subscriber line modem apparatus and methods therefor 失效
标题翻译：非对称数字用户线调制解调器及其方法
公开(公告)号：US08149904B2
公开(公告)日：2012-04-03
申请号：US10350279
申请日：2003-01-24
申请人： Gregory H. Efland , Haixiang Liang , Kevin H. Peterson , Yuanjie Chen , Alan G. Corry , Nino P. Ferrario , Jeff Z. Guan , Meera Prahlad , Ilya Stomakhin , Yongbing Wan , Larry C. Yamano , Lin Yin , Gong-San Yu , George A. Papanicolaou
发明人： Gregory H. Efland , Haixiang Liang , Kevin H. Peterson , Yuanjie Chen , Alan G. Corry , Nino P. Ferrario , Jeff Z. Guan , Meera Prahlad , Ilya Stomakhin , Yongbing Wan , Larry C. Yamano , Lin Yin , Gong-San Yu , George A. Papanicolaou
IPC分类号： H04B1/38
CPC分类号： H04L7/0012 , G06F9/52 , H03M13/2732 , H03M13/6533 , H04L1/0071 , H04L7/0029 , H04L25/03159 , H04L27/2647 , H04L45/00 , H04L49/90 , H04L2012/5681 , H04M11/062
摘要： Provided is a system and method for a modem including one or more processing paths. Also included is a number of interconnected modules sequentially arrayed along the one or more paths. Each module is configured to (i) process signals passed along the paths in accordance with the sequence and (ii) implement predetermined functions to perform the processing. Further, each of the modules has a particular degree of functional programmability and the degrees of functional programmability monotonically vary in accordance with the sequence.
摘要翻译：提供了一种用于包括一个或多个处理路径的调制解调器的系统和方法。还包括沿着一个或多个路径顺序排列的多个互连模块。每个模块被配置为（i）根据顺序处理沿着路径传递的信号，以及（ii）实现预定功能以执行处理。此外，每个模块具有特定程度的功能可编程性，并且功能可编程性的程度根据顺序单调变化。

2. 发明授权

US06449311B1 Methods and apparatus for error concealment utilizing temporal domain motion vector estimation 失效
标题翻译：利用时域运动矢量估计的误差隐藏方法和装置
公开(公告)号：US06449311B1
公开(公告)日：2002-09-10
申请号：US09546782
申请日：2000-04-11
申请人： Taner Ozcelik , Gong-san Yu , Shrish C. Gadre
发明人： Taner Ozcelik , Gong-san Yu , Shrish C. Gadre
IPC分类号： H04N712
CPC分类号： H04N19/895 , H04N5/21 , H04N19/51 , H04N19/56
摘要： A method and apparatus for concealing errors during decoding of a video bit stream utilize estimates, if possible, motion vectors in the temporal domain. If estimation in the temporal domain is not possible, motion vectors are estimated in the spatial domain. A macroblock is then estimated based upon the estimated motion vector. If estimation in the spatial domain is not possible, macroblock estimation is made without the use of an estimated motion vector.
摘要翻译：用于在视频比特流的解码期间隐藏错误的方法和装置利用估计（如果可能的话）在时域中的运动矢量。如果在时域中的估计是不可能的，则在空间域中估计运动矢量。然后基于估计的运动矢量来估计宏块。如果空间域中的估计是不可能的，则在不使用估计的运动矢量的情况下进行宏块估计。

3. 发明授权

US06285715B1 Methods and apparatus for error concealment while decoding a coded video bit stream 失效
标题翻译：解码编码视频位流时错误隐藏的方法和装置
公开(公告)号：US06285715B1
公开(公告)日：2001-09-04
申请号：US09546954
申请日：2000-04-11
申请人： Taner Ozcelik , Gong-san Yu , Shirish C. Gadre
发明人： Taner Ozcelik , Gong-san Yu , Shirish C. Gadre
IPC分类号： H04N712
CPC分类号： H04N19/895 , H04N5/21 , H04N19/51 , H04N19/56
摘要： A method and apparatus for concealing errors during decoding of a video bit stream utilize estimates, if possible, motion vectors in the temporal domain. If estimation in the temporal domain is not possible, motion vectors are estimated in the spatial domain. A macroblock is then estimated based upon the estimated motion vector. If estimation in the spatial domain is not possible, macroblock estimation is made without the use of an estimated motion vector.
摘要翻译：用于在视频比特流的解码期间隐藏错误的方法和装置利用估计（如果可能的话）在时域中的运动矢量。如果在时域中的估计是不可能的，则在空间域中估计运动矢量。然后基于估计的运动矢量来估计宏块。如果空间域中的估计是不可能的，则在不使用估计的运动矢量的情况下进行宏块估计。

4. 发明授权

US06175597B1 Methods and apparatus for error concealment 失效
标题翻译：错误隐藏的方法和设备
公开(公告)号：US06175597B1
公开(公告)日：2001-01-16
申请号：US09546955
申请日：2000-04-11
申请人： Taner Ozcelik , Gong-san Yu , Shirish C. Gadre
发明人： Taner Ozcelik , Gong-san Yu , Shirish C. Gadre
IPC分类号： H04N712
CPC分类号： H04N19/895 , H04N5/21 , H04N19/51 , H04N19/56
摘要： A method and apparatus for concealing errors during decoding of a video bit stream utilize estimates, if possible, motion vectors in the temporal domain. If estimation in the temporal domain is not possible, motion vectors are estimated in the spatial domain. A macroblock is then estimated based upon the estimated motion vector. If estimation in the spatial domain is not possible, macroblock estimation is made without the use of an estimated motion vector.
摘要翻译：用于在视频比特流的解码期间隐藏错误的方法和装置利用估计（如果可能的话）在时域中的运动矢量。如果在时域中的估计是不可能的，则在空间域中估计运动矢量。然后基于估计的运动矢量来估计宏块。如果空间域中的估计是不可能的，则在不使用估计的运动矢量的情况下进行宏块估计。

5. 发明授权

US6078616A Methods and apparatus for error concealment utilizing temporal domain motion vector estimation 失效
公开(公告)号：US6078616A
公开(公告)日：2000-06-20
申请号：US816867
申请日：1997-03-13
申请人： Taner Ozcelik , Gong-san Yu , Shirish C. Gadre
发明人： Taner Ozcelik , Gong-san Yu , Shirish C. Gadre
IPC分类号： H04N5/21 , H04N19/895 , H04N7/12
CPC分类号： H04N19/895 , H04N19/51 , H04N19/56 , H04N5/21
摘要： A method and apparatus for concealing errors during decoding of a video bit stream utilize estimates, if possible, motion vectors in the temporal domain. If estimation in the temporal domain is not possible, motion vectors are estimated in the spatial domain. A macroblock is then estimated based upon the estimated motion vector. If estimation in the spatial domain is not possible, macroblock estimation is made without the use of an estimated motion vector.

6. 发明授权

US5959684A Method and apparatus for audio-video synchronizing 失效
标题翻译：用于音频 - 视频同步的方法和装置
公开(公告)号：US5959684A
公开(公告)日：1999-09-28
申请号：US901090
申请日：1997-07-28
申请人： Yew-Koon Tan , Gong-san Yu
发明人： Yew-Koon Tan , Gong-san Yu
IPC分类号： H04N5/60 , G09G5/00 , G09G5/12 , G11B27/10 , H04N5/92 , H04N5/93 , H04N7/04 , H04N7/045 , H04N7/26 , H04N21/2368 , H04N21/434 , H04N7/62
CPC分类号： H04N21/4341 , H04N19/42 , H04N19/44 , H04N21/4307
摘要： A method and apparatus for synchronizing the playback of audio and video frames from a program source. The method associates an audio presentation time stamp ("PTS") value with an output audio frame. Selected ones of audio and video data packets include respective audio and video PTS values representing desired playback times of the respective audio and data associated therewith. The selected ones of the audio data packets further include audio frame numbers representing a number of output frames of audio to be played back between the selected ones of the audio data packets. The method comprises the steps of first storing the audio and video PTS values in respective audio and video PTS tables during an audio demultiplexing process. In addition, the audio frame numbers are stored in frame counters in association with respective PTS values during the demultiplexing process. Thereafter, the process sequentially decodes the audio and video input data to produce respective frames of audio and video which are presented to the user. With the presentation of each audio and video frame, the respective audio and video frame counters are selectively decremented. Upon detecting one of the audio frame counters having a zero value, the audio PTS value for that zero value audio frame counter is retrieved. Thereafter, the playback of the audio and video frames is selectively modified so that frames of audio and video are played back in synchronization.
摘要翻译：一种用于使来自程序源的音频和视频帧的重放同步的方法和装置。该方法将音频呈现时间戳（“PTS”）值与输出音频帧相关联。所选择的音频和视频数据分组包括表示与其相关联的相应音频和数据的期望回放时间的相应音频和视频PTS值。所选择的音频数据分组还包括表示在所选择的音频数据分组之间要播放的音频的输出帧数的音频帧号。该方法包括以下步骤：在音频解复用处理期间首先将音频和视频PTS值存储在相应的音频和视频PTS表中。此外，在解复用处理期间，音频帧号与相应的PTS值相关联地存储在帧计数器中。此后，该处理顺序解码音频和视频输入数据，以产生呈现给用户的相应的音频和视频帧。随着每个音频和视频帧的呈现，相应的音频和视频帧计数器被选择性地递减。在检测到具有零值的音频帧计数器之一时，检索该零值音频帧计数器的音频PTS值。此后，选择性地修改音频和视频帧的重放，使得音频和视频帧同步地重放。

7. 发明授权

US07203823B2 Partial and start-over threads in embedded real-time kernel 有权
标题翻译：嵌入式实时内核中的部分和启动线程
公开(公告)号：US07203823B2
公开(公告)日：2007-04-10
申请号：US10339954
申请日：2003-01-09
申请人： Elif Albuz , Gong-San Yu , Leonid Abraham Milenky
发明人： Elif Albuz , Gong-San Yu , Leonid Abraham Milenky
IPC分类号： G06F9/445
CPC分类号： G06F9/461 , G06F9/3009 , G06F9/3824 , G06F9/3851 , G06F9/4812 , G06F9/4843
摘要： Methods and apparatus for implementing partial and start-over threads in a kernel of an operating system are disclosed. In a computing system having at least one CPU, registers for executing threads, and memory, a method for executing a partial thread includes executing a first thread in the registers, initiating an interrupt event that signals the activation of another thread, saving a first portion of registers to a memory location, wherein a second portion of the registers is unsaved, the first portion including information associated with the first thread, executing in the registers, the another thread, and conducting further computing system operations. Additionally, conducting further computing system operations can include restoring the saved first portion of registers from the memory location to the registers and resuming execution of the first thread. Also, another embodiment incorporates the foregoing method into a computer device.
摘要翻译：公开了一种用于在操作系统的内核中实现部分和启动线程的方法和装置。在具有至少一个CPU，用于执行线程的寄存器和存储器的计算系统中，用于执行部分线程的方法包括执行寄存器中的第一线程，发起用于发信号通知另一线程的激活的中断事件，保存第一部分寄存器到存储器位置，其中寄存器的第二部分未保存，第一部分包括与第一线程相关联的信息，在寄存器中执行，另一线程，以及执行另外的计算系统操作。此外，执行另外的计算系统操作可以包括将保存的第一部分寄存器从存储器位置恢复到寄存器并恢复第一线程的执行。而且，另一实施例将前述方法结合到计算机设备中。

8. 发明授权

US07177988B2 Method and system for synchronizing processor and DMA using ownership flags 失效
标题翻译：使用所有权标志同步处理器和DMA的方法和系统
公开(公告)号：US07177988B2
公开(公告)日：2007-02-13
申请号：US10350287
申请日：2003-01-24
申请人： Gregory H. Efland , Jeff Z. Guan , Gong-San Yu
发明人： Gregory H. Efland , Jeff Z. Guan , Gong-San Yu
IPC分类号： G06F13/18
CPC分类号： H04L7/0012 , G06F9/52 , H03M13/2732 , H03M13/6533 , H04L1/0071 , H04L7/0029 , H04L25/03159 , H04L27/2647 , H04L45/00 , H04L49/90 , H04L2012/5681 , H04M11/062
摘要： Provided is a system and method for a modem including one or more processing paths. Also included is a number of interconnected modules sequentially arrayed along the one or more paths. Each module is configured to (i) process signals passed along the paths in accordance with the sequence and (ii) implement predetermined functions to perform the processing. Further, each of the modules has a particular degree of functional programmability and the degrees of functional programmability monotonically vary in accordance with the sequence.
摘要翻译：提供了一种用于包括一个或多个处理路径的调制解调器的系统和方法。还包括沿着一个或多个路径顺序排列的多个互连模块。每个模块被配置为（i）根据顺序处理沿着路径传递的信号，以及（ii）实现预定功能以执行处理。此外，每个模块具有特定程度的功能可编程性，并且功能可编程性的程度根据顺序单调变化。

9. 发明授权

US06363207B1 Method and apparatus for a virtual system time clock for digital audio/video processor 失效
标题翻译：用于数字音频/视频处理器的虚拟系统时钟的方法和装置
公开(公告)号：US06363207B1
公开(公告)日：2002-03-26
申请号：US09177261
申请日：1998-10-22
申请人： Cem Duruoz , Taner Ozcelik , Gong-san Yu
发明人： Cem Duruoz , Taner Ozcelik , Gong-san Yu
IPC分类号： H04N591
CPC分类号： H04N21/47217 , H04N5/04 , H04N5/4401 , H04N5/45 , H04N5/602 , H04N5/783 , H04N9/8042 , H04N9/8063 , H04N9/8227 , H04N21/4307 , H04N21/4341 , H04N21/4392 , H04N21/44004
摘要： A digital video processor and operating method for a receiving raw audio and video data representing images and sound to be played. The processor includes a demultiplexer for receiving the raw audio and video data and providing demultiplexed audio and video data to a memory. A first system time clock provides first time values in response to being continuously clocked by the demultiplexer. A CPU decodes and plays back the audio and video data as a function of the audio and video PTS values. The processor further includes a second system time clock providing second time values in response to being periodically incremented by the CPU. The CPU periodically sets the second system time clock to a second time value equal to a current first time value of the first system time clock in response to a standard play mode, and the CPU periodically sets the first system time clock to a first time value equal to a current second time value of the second system time clock in response to a trick play mode.
摘要翻译：一种用于接收表示要播放的图像和声音的原始音频和视频数据的数字视频处理器和操作方法。处理器包括用于接收原始音频和视频数据的解复用器，并将解复用的音频和视频数据提供给存储器。响应于由解复用器连续计时，第一系统时钟提供第一时间值。 CPU根据音频和视频PTS值解码和播放音频和视频数据。处理器还包括第二系统时钟响应于由CPU周期性增加的第二时间值。响应于标准播放模式，CPU周期性地将第二系统时间时钟设置为等于第一系统时钟的当前第一时间值的第二时间值，并且CPU周期性地将第一系统时间时钟设置为第一时间值等于第二系统时钟响应于特技播放模式的当前第二时间值。

10. 发明授权

US06263303B1 Simulator architecture 失效
标题翻译：模拟器架构
公开(公告)号：US06263303B1
公开(公告)日：2001-07-17
申请号：US09178676
申请日：1998-10-26
申请人： Gong-san Yu , Tilman H.S.T.M. Kolks
发明人： Gong-san Yu , Tilman H.S.T.M. Kolks
IPC分类号： G06F9455
CPC分类号： G06F17/5022 , G06F11/261
摘要： An simulator particularly suited for simulating the hardware/software behavior of embedded systems. The architecture of the simulator permits the hardware and software systems to be modeled as modules with well characterized behaviors. A concise module definition syntax is used to describe module behaviors, and a translator operates upon the module to abstract operations of module behaviors at a level which does not require cycle-based, direct interaction of each module with the underlying simulation engine.
摘要翻译：特别适用于模拟嵌入式系统的硬件/软件行为的模拟器。模拟器的架构允许将硬件和软件系统建模为具有良好表征行为的模块。简洁的模块定义语法用于描述模块行为，翻译器对模块进行操作，以模块行为抽象操作，其级别不需要基于循环的每个模块与底层仿真引擎的直接交互。

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