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1. 发明授权

US06259479B1 Letterbox filter apparatus and method 失效
标题翻译：信箱过滤装置和方法
公开(公告)号：US06259479B1
公开(公告)日：2001-07-10
申请号：US09096321
申请日：1998-06-11
申请人： Shirish C. Gadre , Taner Ozcelik
发明人： Shirish C. Gadre , Taner Ozcelik
IPC分类号： H04N701
CPC分类号： H04N7/0122 , H04N7/0135 , Y10S348/913
摘要： A method and apparatus for changing the number of scan lines in a frame of video data to produce an image represented by the video data that corresponds to a desired aspect ratio. The apparatus includes a pair of finite impulse response filters for processing the decoded chrominance and luminance pixel values stored in memory. The filters permit a plurality of scan lines of chrominance and luminance data to be read and filtered on a continuous basis with any scan line of data being read only once. Thus, the filters provide a very efficient method of providing a frame of a number of output scan lines of chrominance and luminance pixel values that are different from the number of scan lines of chrominance and luminance pixel values in a frame of video data stored in memory.
摘要翻译：一种用于改变视频数据帧中的扫描线数量以产生由对应于所需宽高比的视频数据表示的图像的方法和装置。该装置包括一对用于处理存储在存储器中的解码色度和亮度像素值的有限脉冲响应滤波器。滤波器允许在任何扫描数据线只读一次的情况下连续地读取和滤波多个色度和亮度数据扫描线。因此，滤波器提供了一种非常有效的方法，其提供与存储在存储器中的视频数据的帧中的色度和亮度像素值的扫描线的数量不同的色度和亮度像素值的多个输出扫描线的帧。

2. 发明授权

US5928321A Task and stack manager for digital video decoding 失效
标题翻译：任务和堆栈管理器用于数字视频解码
公开(公告)号：US5928321A
公开(公告)日：1999-07-27
申请号：US866419
申请日：1997-05-30
申请人： Taner Ozcelik , Shirish C. Gadre
发明人： Taner Ozcelik , Shirish C. Gadre
IPC分类号： G06F9/42 , G06F9/48 , G06F13/00
CPC分类号： G06F9/4812 , G06F9/4426 , G06F9/4881
摘要： A reduced instruction set CPU is programmed to provide software-controlled task management, a stack, and to manage virtual instruction memory. The CPU performs a task management procedure in which the CPU repeatedly checks task flags, and if a task flag is set, performs the task associated with the set task flag. If multiple task flags are set, the highest priority task of those associated with set task flags is performed. Whenever a subroutine call is needed, the subroutine call is implemented by calling a stack management routine. The stack management routine retrieves and stores a return address into a location in DRAM identified by a stack pointer, increments the stack pointer, and then executes a CALL instruction, causing program execution to sequence to the desired subroutine. At the end of each subroutine, a RETURN instruction is executed, in response to which, program execution returns to the stack management routine, and the stack management routine decrements the stack pointer, loads the previously-stored return address from a location in DRAM identified by the stack pointer register, and then causes program execution to sequence to the loaded return address. The stack management routine also provides virtual instruction memory management, by determining whether a routine is resident in the on-chip instruction memory available to the RISC CPU prior to calling or returning to the routine. If not, the virtual instruction memory management routine transfers the desired routine from off-chip DRAM into the on-chip instruction memory, and then executes the call or return.
摘要翻译：精简指令集CPU被编程为提供软件控制的任务管理，堆栈和管理虚拟指令存储器。 CPU执行任务管理过程，其中CPU重复检查任务标志，并且如果设置了任务标志，则执行与设置任务标志相关联的任务。如果设置了多个任务标志，则执行与设置任务标志相关联的最高优先级任务。每当需要子程序调用时，通过调用堆栈管理例程来实现子程序调用。堆栈管理例程检索并将返回地址存储到由堆栈指针识别的DRAM中的位置，增加堆栈指针，然后执行CALL指令，使程序执行顺序到期望的子程序。在每个子程序结束时，执行RETURN指令，响应于此程序执行返回到堆栈管理例程，并且堆栈管理例程减小堆栈指针，从DRAM中识别的位置加载先前存储的返回地址通过堆栈指针寄存器，然后使程序执行顺序到加载的返回地址。在调用或返回到例程之前，栈管理例程还提供虚拟指令存储器管理，通过确定一个例程是否驻留在可用于RISC CPU的片上指令存储器中。如果不是，虚拟指令存储器管理例程将期望的例程从片外DRAM传送到片上指令存储器，然后执行调用或返回。

3. 发明授权

US5903311A Run level pair buffering for fast variable length decoder circuit 失效
标题翻译：用于快速可变长度解码器电路的运行电平对缓冲
公开(公告)号：US5903311A
公开(公告)日：1999-05-11
申请号：US866701
申请日：1997-05-30
申请人： Taner Ozcelik , Shirish C. Gadre , Moshe Bublil , Sabyasachi Dutta , Subroto Bose
发明人： Taner Ozcelik , Shirish C. Gadre , Moshe Bublil , Sabyasachi Dutta , Subroto Bose
IPC分类号： G06T9/00 , H03M7/40 , H04N7/26 , H04N7/50 , A04N7/30
CPC分类号： H03M7/40 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/61 , H04N19/13 , H04N19/91
摘要： A decoding circuit for decoding (or decompressing) compressed video data includes an RL circuit, such as MPEG encoded video data. The RL circuit includes a buffer memory for storing run-level pairs during the decoding process. Because the buffer memory in the RL circuit can store ran-level pairs, Huffman-decoding and header decoding, performed by a variable length decoding (VLD) circuit, is decoupled from inverse discrete transform decoding, performed by an IDCT circuit. This decoupling speeds up the decoding pipeline by allowing more continuous operation by both the VLD and IDCT circuits.
摘要翻译：用于解码（或解压缩）压缩视频数据的解码电路包括诸如MPEG编码视频数据的RL电路。 RL电路包括用于在解码过程期间存储运行电平对的缓冲存储器。由于RL电路中的缓冲存储器可以存储运行电平对，由可变长度解码（VLD）电路执行的霍夫曼解码和报头解码与由IDCT电路执行的反离散变换解码分离。这种去耦通过允许VLD和IDCT电路的更连续的操作来加速解码流水线。

4. 发明授权

US6088047A Motion compensated digital video decoding with buffered picture storage memory map 失效
标题翻译：运动补偿数字视频解码与缓冲图像存储器映射
公开(公告)号：US6088047A
公开(公告)日：2000-07-11
申请号：US1129
申请日：1997-12-30
申请人： Subroto Bose , Shirish C. Gadre , Taner Ozcelik , Edward J. Paluch , Syed Reza
发明人： Subroto Bose , Shirish C. Gadre , Taner Ozcelik , Edward J. Paluch , Syed Reza
IPC分类号： H04N7/26 , H04N7/36 , H04N7/50 , G06F17/76 , H04N9/64
CPC分类号： H04N19/433 , H04N19/174 , H04N19/423 , H04N19/51 , H04N19/61
摘要： A digital video presentation system is provided with hardware and software logic for mapping the picture data into buffer memory in a way that permits both the reading of motion vector compensated macroblocks of data and the reading of horizontal picture wide scan lines with a low number of memory page crossings. Preferably, the memory is a plurality of rows, for example 16 rows, wide. Preferably, 16 lines of 8-pixel (two 32 pixel wide column) line segments of 8.times.8 pixel blocks are stored in consecutive storage locations followed by the consecutive storage vertically adjacent line segments until one line segment is stored in each logical row of the memory. Then the next horizontally adjacent set of line segments of similarly stored until the right boundary of the picture is reached, then the each additional row of 16 lines of the picture similarly are stored until the bottom of the picture is reached. Each 16.times.16 pixel macroblock of data is stored on a single page; preferably, two horizontally adjacent macroblocks are stored on one page of memory. Each line of the picture is stored in contiguous locations on the same row of the memory. The motion compensation logic interprets motion vectors from the incoming data and calculates addresses for a macroblock of picture data by separating read commands into separate commands where a page boundary divides the macroblock into vertically adjacent rectangles. Memory controller logic further divides such rectangles where they cross boundaries between horizontally adjacent pages of the memory. One fixed address increment of 8 hex steps from line segment to vertically adjacent line segment while another fixed address increment of 80 hex steps horizontally from one 8 pixel line segment to the next, such as across a scan line of the picture.
摘要翻译：数字视频呈现系统具有用于将图像数据映射到缓冲存储器中的硬件和软件逻辑，其方式是允许读取运动矢量补偿的数据宏块和读取具有低数量存储器的水平图像宽扫描线页面交叉。优选地，存储器是多行，例如16行宽。优选地，8×8像素块的8行（两个32像素宽列）行的16行存储在连续的存储位置中，随后是垂直相邻的线段的连续存储，直到在存储器的每个逻辑行中存储一个线段。然后类似地存储下一个水平相邻的线段组，直到图像的右边界达到，然后类似地存储图像的16行的每个附加行直到图像的底部到达。数据的每个16×16像素宏块存储在单个页面上; 优选地，两个水平相邻的宏块存储在一页存储器上。图片的每行都存储在存储器的同一行的连续位置。运动补偿逻辑解释来自输入数据的运动矢量，并通过将读取命令分离成单独的命令来计算图像数据的宏块的地址，其中页边界将宏块划分成垂直相邻的矩形。存储器控制器逻辑进一步划分这样的矩形，它们跨越存储器的水平相邻页面之间的边界。一个固定的地址增量从线段到垂直相邻的线段8个十六进制步长，而另一个固定地址增量为80个十六进制水平从一个8像素线段到下一个，例如跨越图像的扫描线。

5. 发明授权

US5995161A Digital video processor with subvideo processor 失效
标题翻译：具有子视频处理器的数字视频处理器
公开(公告)号：US5995161A
公开(公告)日：1999-11-30
申请号：US832378
申请日：1997-04-02
申请人： Shirish C. Gadre , Cem I. Duruoz , Taner Ozcelik
发明人： Shirish C. Gadre , Cem I. Duruoz , Taner Ozcelik
IPC分类号： H04N5/445 , H04N5/92 , H04N5/14
CPC分类号： H04N5/44504 , H04N21/4312
摘要： An improved architecture for a digital video processor that processes subvideo data to be superimposed on a main video image during a display image scanning process. The improved digital video processor divides and partitions the execution of subvideo data between a programable CPU and a dedicated hardware processor. The CPU is used to process the simpler, less time critical, nonpixel data, and the more complex, more time critical pixel data is processed in real time using a dedicated hardware processor operating under the control of the CPU. The improved digital video processor is adaptable to process subvideo data being supplied in different data formats.
摘要翻译：一种用于数字视频处理器的改进架构，其在显示图像扫描处理期间处理子视频数据以叠加在主视频图像上。改进的数字视频处理器在可编程CPU和专用硬件处理器之间划分和划分子视频数据的执行。 CPU用于处理更简单，更少时间关键的非像素数据，并且使用在CPU控制下操作的专用硬件处理器实时处理更复杂，更时间更长的像素数据。改进的数字视频处理器适用于处理以不同数据格式提供的子视频数据。

6. 发明授权

US06285715B1 Methods and apparatus for error concealment while decoding a coded video bit stream 失效
标题翻译：解码编码视频位流时错误隐藏的方法和装置
公开(公告)号：US06285715B1
公开(公告)日：2001-09-04
申请号：US09546954
申请日：2000-04-11
申请人： Taner Ozcelik , Gong-san Yu , Shirish C. Gadre
发明人： Taner Ozcelik , Gong-san Yu , Shirish C. Gadre
IPC分类号： H04N712
CPC分类号： H04N19/895 , H04N5/21 , H04N19/51 , H04N19/56
摘要： A method and apparatus for concealing errors during decoding of a video bit stream utilize estimates, if possible, motion vectors in the temporal domain. If estimation in the temporal domain is not possible, motion vectors are estimated in the spatial domain. A macroblock is then estimated based upon the estimated motion vector. If estimation in the spatial domain is not possible, macroblock estimation is made without the use of an estimated motion vector.
摘要翻译：用于在视频比特流的解码期间隐藏错误的方法和装置利用估计（如果可能的话）在时域中的运动矢量。如果在时域中的估计是不可能的，则在空间域中估计运动矢量。然后基于估计的运动矢量来估计宏块。如果空间域中的估计是不可能的，则在不使用估计的运动矢量的情况下进行宏块估计。

7. 发明授权

US06175597B1 Methods and apparatus for error concealment 失效
标题翻译：错误隐藏的方法和设备
公开(公告)号：US06175597B1
公开(公告)日：2001-01-16
申请号：US09546955
申请日：2000-04-11
申请人： Taner Ozcelik , Gong-san Yu , Shirish C. Gadre
发明人： Taner Ozcelik , Gong-san Yu , Shirish C. Gadre
IPC分类号： H04N712
CPC分类号： H04N19/895 , H04N5/21 , H04N19/51 , H04N19/56
摘要： A method and apparatus for concealing errors during decoding of a video bit stream utilize estimates, if possible, motion vectors in the temporal domain. If estimation in the temporal domain is not possible, motion vectors are estimated in the spatial domain. A macroblock is then estimated based upon the estimated motion vector. If estimation in the spatial domain is not possible, macroblock estimation is made without the use of an estimated motion vector.
摘要翻译：用于在视频比特流的解码期间隐藏错误的方法和装置利用估计（如果可能的话）在时域中的运动矢量。如果在时域中的估计是不可能的，则在空间域中估计运动矢量。然后基于估计的运动矢量来估计宏块。如果空间域中的估计是不可能的，则在不使用估计的运动矢量的情况下进行宏块估计。

8. 发明授权

US6078616A Methods and apparatus for error concealment utilizing temporal domain motion vector estimation 失效
公开(公告)号：US6078616A
公开(公告)日：2000-06-20
申请号：US816867
申请日：1997-03-13
申请人： Taner Ozcelik , Gong-san Yu , Shirish C. Gadre
发明人： Taner Ozcelik , Gong-san Yu , Shirish C. Gadre
IPC分类号： H04N5/21 , H04N19/895 , H04N7/12
CPC分类号： H04N19/895 , H04N19/51 , H04N19/56 , H04N5/21
摘要： A method and apparatus for concealing errors during decoding of a video bit stream utilize estimates, if possible, motion vectors in the temporal domain. If estimation in the temporal domain is not possible, motion vectors are estimated in the spatial domain. A macroblock is then estimated based upon the estimated motion vector. If estimation in the spatial domain is not possible, macroblock estimation is made without the use of an estimated motion vector.

9. 发明授权

US6012137A Special purpose processor for digital audio/video decoding 失效
标题翻译：专用处理器，用于数字音频/视频解码
公开(公告)号：US6012137A
公开(公告)日：2000-01-04
申请号：US865749
申请日：1997-05-30
申请人： Moshe Bublil , Subroto Bose , Shirish C. Gadre , Taner Ozcelik
发明人： Moshe Bublil , Subroto Bose , Shirish C. Gadre , Taner Ozcelik
IPC分类号： G06F9/308 , G06F9/312 , G06F9/32 , G06F9/38 , G06F15/78 , G06F15/76
CPC分类号： G06F9/30018 , G06F15/7832 , G06F9/30043 , G06F9/30101 , G06F9/30167 , G06F9/322 , G06F9/3824 , G06F9/3836
摘要： A special purpose reduced instruction set central processing unit (RISC CPU) for controlling digital audio/video decoding. The instruction set includes flow control instructions which incorporate immediate values, used to jump over a small number of instructions, and other instructions used for larger jumps. Also, instructions obtain data from the video decoder of the ASIC in a streamlined fashion, using video decoder addresses hard-coded into the RISC CPU. Further instructions perform manipulations of individual bits of registers used as state/status flags. The RISC CPU includes watchdog functions for monitoring the delivery of data to the RISC CPU from other functional units or from memory, so that the RISC CPU can execute instructions while delivery of data from memory or other functional units is pending, unless that data is necessary for program execution, in which case, program execution stalls until the data arrives. To further reduce instruction latency, if an instruction makes use of the contents of a register that is in the process of being written by an immediately preceding instruction, the RISC CPU "bypasses" the register file, using previous results directly in a subsequent instruction. For the purposes of control and debugging, the PC can be read or written by an external host, and instructions can be loaded directly from the host. Also, pages of instructions can be loaded to or from the instruction memory to allow for an unlimited virtual instruction memory space.
摘要翻译：用于控制数字音频/视频解码的特殊目的简化指令集中央处理单元（RISC CPU）。指令集包括流量控制指令，其包含用于跳过少量指令的立即值以及用于较大跳跃的其他指令。此外，指令以流线型方式从ASIC的视频解码器获取数据，使用硬编码到RISC CPU中的视频解码器地址。进一步的指令执行用作状态/状态标志的寄存器的各个位的操作。 RISC CPU包括监视功能，用于监视从其他功能单元或从存储器向RISC CPU传送数据，以便RISC CPU可以执行指令，同时从存储器或其他功能单元传输数据仍在等待，除非该数据是必要的对于程序执行，在这种情况下，程序执行停止，直到数据到达。为了进一步减少指令等待时间，如果指令利用正在前一条指令写入的寄存器的内容，RISC CPU将“暂停”寄存器文件，直接在后续指令中使用先前的结果。为了进行控制和调试，PC可以由外部主机读取或写入，并且可以直接从主机加载指令。此外，可以将指令页加载到指令存储器或从指令存储器加载，以允许无限制的虚拟指令存储器空间。

10. 发明授权

US06934338B1 Variable length decoder for decoding digitally encoded video signals 失效
标题翻译：用于解码数字编码视频信号的可变长度解码器
公开(公告)号：US06934338B1
公开(公告)日：2005-08-23
申请号：US10662645
申请日：2003-09-15
申请人： Moshe Bublil , Subroto Bose , Shirish C. Gadre , John Hong , Taner Ozcelik
发明人： Moshe Bublil , Subroto Bose , Shirish C. Gadre , John Hong , Taner Ozcelik
IPC分类号： G06T9/00 , H04N7/26 , H04N7/30 , H04N7/50 , H04N7/12
CPC分类号： H04N19/00 , H04N19/42 , H04N19/60 , H04N19/70 , H04N19/90 , H04N19/91
摘要： A variable length decoder (VLD) for decoding MPEG-1 and -2 syntax compliant video bit streams. The VLD includes a micro-sequencer and VLD command decode/execution unit for controlling the MPEG decoding process using a novel instruction set. The instruction set includes a set of commands for decoding the video data and a set of flow control instructions. A rotator/barrel shifter is provided for making a predetermined number of encoded bits from the video bit stream available to the VLD and a variable length table decoder for variable length decoding using the MPEG standard variable length code (VLC) tables. The variable length table decoder shares a prefix pattern matching scheme across all of the VLC tables and organizes the variable length codes into a series of subtables. Each subtable corresponds to one of the unique prefix patterns. Variable length codes are decoded by identifying a leading pattern in the video data bit stream and, in parallel, accessing the subtable corresponding to that leading pattern. Run-length and amplitude level DCT coefficient symbols are stored in compressed form, and decoded as needed by an inverse transform unit. Motion vectors are also stored until needed by a motion compensation unit.
摘要翻译：用于解码MPEG-1和-2语法兼容视频比特流的可变长度解码器（VLD）。 VLD包括用于使用新颖的指令集来控制MPEG解码处理的微定序器和VLD命令解码/执行单元。指令集包括用于解码视频数据的一组命令和一组流控制指令。提供一个旋转器/桶形移位器，用于从VLD可用的视频比特流和可变长度表解码器中使用MPEG标准可变长度码（VLC）表来进行可变长度解码，从而使预定数量的编码比特。可变长度表解码器在所有VLC表中共享前缀模式匹配方案，并将可变长度代码组织成一系列子表。每个子表都对应于唯一前缀模式之一。通过识别视频数据位流中的引导图案并且并行地访问与该引导图案相对应的子表，来对可变长度代码进行解码。运行长度和幅度级DCT系数符号以压缩形式存储，并根据需要由逆变换单元进行解码。运动矢量也被存储直到运动补偿单元需要。

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