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1. 发明授权

US06635938B1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06635938B1
公开(公告)日：2003-10-21
申请号：US09716219
申请日：2000-11-21
申请人： Takumi Nakahata , Shigemitsu Maruno , Taisuke Furukawa , Naruhisa Miura , Toshiyuki Oishi , Yasunori Tokuda
发明人： Takumi Nakahata , Shigemitsu Maruno , Taisuke Furukawa , Naruhisa Miura , Toshiyuki Oishi , Yasunori Tokuda
IPC分类号： H01L2994
CPC分类号： H01L29/4983 , H01L21/823418 , H01L21/823468 , H01L29/41783 , H01L29/6656 , H01L29/66575 , H01L29/66628
摘要： A polysilicon nitride film is formed to cover a polysilicon gate. By heat treatment of the silicon nitride film in an oxygen atmosphere, a silicon oxinitride film is formed. By anisotropically etching the silicon oxinitride film and the silicon nitride film, a sidewall insulating film is formed. By epitaxial growth, selective silicon films of a prescribed film thickness are formed on source and drain regions. During this period, silicon islands are not deposited on the surface of sidewall insulating film. Consequently, a semiconductor device including a transistor of a superior electrical insulation can be obtained.
摘要翻译：形成多晶硅氮化物膜以覆盖多晶硅栅极。通过在氧气氛中对氮化硅膜进行热处理，形成硅氧氮化物膜。通过各向异性蚀刻氧氮化硅膜和氮化硅膜，形成侧壁绝缘膜。通过外延生长，在源极和漏极区域上形成规定膜厚度的选择性硅膜。在此期间，硅岛不会沉积在侧壁绝缘膜的表面上。因此，可以获得包括具有优异的电绝缘的晶体管的半导体器件。

2. 发明授权

US06566734B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06566734B2
公开(公告)日：2003-05-20
申请号：US09809211
申请日：2001-03-16
申请人： Kohei Sugihara , Toshiyuki Oishi , Naruhisa Miura , Yuji Abe , Yasunori Tokuda
发明人： Kohei Sugihara , Toshiyuki Oishi , Naruhisa Miura , Yuji Abe , Yasunori Tokuda
IPC分类号： H01L29788
CPC分类号： H01L29/66651 , H01L29/1045 , H01L29/1054 , H01L29/66492 , H01L29/66545 , H01L29/66621
摘要： In making a field effect transistor, a dummy gate electrode is formed before a gate electrode is formed. Extension regions, a side wall silicon nitride film, source/drain regions, a silicon oxide film, and other elements are formed with respect to the dummy gate electrode. The dummy gate electrode is removed, and a part of the extension regions diffused into a region immediately under the dummy gate electrode is removed. The removed part is filled with silicon selection epitaxial film. Thereafter, the intended gate electrode is formed. This production method produces a field effect transistor that prevents deterioration of electrical characteristics caused by the short channel effect and parasitic resistance.
摘要翻译：在制作场效应晶体管时，在形成栅电极之前形成伪栅电极。相对于虚拟栅电极形成延伸区域，侧壁氮化硅膜，源极/漏极区域，氧化硅膜等元件。去除虚拟栅电极，并且去除扩散到虚拟栅电极正下方的区域中的一部分延伸区域。被去除的部分填充硅选择外延膜。之后，形成预定的栅电极。该制造方法产生场效应晶体管，其防止由短沟道效应和寄生电阻引起的电特性的劣化。

3. 发明授权

US06624034B2 Method of making field effect transistor in which the increase of parasitic capacitance is restrained by scale reduction 失效
标题翻译：制造场效应晶体管的方法，其中寄生电容的增加受缩小的限制
公开(公告)号：US06624034B2
公开(公告)日：2003-09-23
申请号：US10173835
申请日：2002-06-19
申请人： Yuji Abe , Naruhisa Miura , Kohei Sugihara , Toshiyuki Oishi , Yasunori Tokuda
发明人： Yuji Abe , Naruhisa Miura , Kohei Sugihara , Toshiyuki Oishi , Yasunori Tokuda
IPC分类号： H01L21336
CPC分类号： H01L29/6653 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/66628
摘要： A method of producing a semiconductor device includes forming a gate electrode on a channel region on a surface of a semiconductor region of a semiconductor substrate, the channel region having a depth in the semiconductor substrate; forming a first pair of side wall spacers on opposite sides of the gate electrode; forming elevated semiconductor layers, each elevated semiconductor layer being elevated relative to the channel region, on regions outside of the pair of side wall spacers and in which source and drain regions of a first conductivity type are to be formed; removing the pair of first side wall spacers; and forming a pair of pocket injection regions of a second conductivity type by introducing, after the side wall spacers are removed, a dopant impurity producing the second conductivity type deeper in the semiconductor substrate than a region where the side wall spacers were formed, the pair of pocket injection regions respectively covering only a neighborhood of respective side surface parts of the channel region, where the source and drain regions are to be formed, forming respective pn junctions only between the neighborhood of the side surface parts and the pocket injection regions.
摘要翻译：一种制造半导体器件的方法包括在半导体衬底的半导体区域的表面上的沟道区上形成栅电极，所述沟道区在半导体衬底中具有深度; 在栅电极的相对侧上形成第一对侧壁间隔物; 形成升高的半导体层，每个升高的半导体层相对于沟道区域升高，在一对侧壁间隔物外侧的区域上，并且将形成第一导电类型的源极和漏极区域; 移除所述一对第一侧壁间隔件; 以及形成第二导电类型的一对口袋注入区域，在除去侧壁间隔物之后，在半导体衬底中产生比形成侧壁间隔物的区域更深的第二导电类型的掺杂剂杂质，该对分别仅覆盖要形成源极和漏极区的沟道区的各个侧表面部分的附近的口腔注入区域，仅在侧表面部分的附近和口袋注入区域之间形成相应的pn结。

4. 发明授权

US06617654B2 Semiconductor device with sidewall spacers and elevated source/drain region 失效
标题翻译：具有侧壁间隔件和升高的源极/漏极区域的半导体器件
公开(公告)号：US06617654B2
公开(公告)日：2003-09-09
申请号：US09955488
申请日：2001-09-19
申请人： Toshiyuki Oishi , Kohei Sugihara , Naruhisa Miura , Yuji Abe , Yasunori Tokuda
发明人： Toshiyuki Oishi , Kohei Sugihara , Naruhisa Miura , Yuji Abe , Yasunori Tokuda
IPC分类号： H01L2976
CPC分类号： H01L29/66628 , H01L29/665 , H01L29/6656 , H01L29/7834
摘要： Source and drain regions include regions of an epitaxial silicon film on the surface of the substrate and regions in the substrate. The depth of junctions of the source and drain regions is identical to or shallower than the depth of junctions of extension regions. As a result, even if the thickness of the side wall layer is reduced, since the depletion layer of the extension regions with lower impurity concentration compared with the source and drain regions is predominant, the short channel effect has a smaller effect.
摘要翻译：源区和漏区包括在衬底的表面上的外延硅膜的区域和衬底中的区域。源极和漏极区域的结的深度与延伸区域的接合点的深度相同或更浅。结果，即使侧壁层的厚度减小，由于与源极和漏极区域相比，杂质浓度较低的延伸区域的耗尽层是主要的，所以短沟道效应具有较小的效果。

5. 发明授权

US06633070B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06633070B2
公开(公告)日：2003-10-14
申请号：US09953960
申请日：2001-09-18
申请人： Naruhisa Miura , Toshiyuki Oishi , Yuji Abe , Kohei Sugihara
发明人： Naruhisa Miura , Toshiyuki Oishi , Yuji Abe , Kohei Sugihara
IPC分类号： H01L2976
CPC分类号： H01L29/4991 , H01L21/2257 , H01L21/28114 , H01L21/82385 , H01L21/823864 , H01L29/41783 , H01L29/42376 , H01L29/4983 , H01L29/66545
摘要： A field-effect transistor including a gate electrode, silicon layers, and source and drain regions at a surface of a silicon substrate. Sidewall insulating films on the opposite side surfaces of the gate electrode are located between the gate electrode and the silicon layers and contain respective voids.
摘要翻译：场效应晶体管，其包括在硅衬底的表面处的栅电极，硅层以及源极和漏极区。栅电极的相对侧表面上的侧壁绝缘膜位于栅电极和硅层之间，并且包含相应的空隙。

6. 发明授权

US09324782B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09324782B2
公开(公告)日：2016-04-26
申请号：US14344195
申请日：2012-11-09
申请人： Naruhisa Miura , Shiro Hino , Kenichi Ohtsuka
发明人： Naruhisa Miura , Shiro Hino , Kenichi Ohtsuka
IPC分类号： H01L29/06 , H01L29/12 , H01L29/66 , H01L29/78 , H01L29/10 , H01L29/16 , H01L29/20
CPC分类号： H01L29/66712 , H01L29/0615 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L29/66045 , H01L29/66068 , H01L29/7811
摘要： A semiconductor layer, a well region, and a source region form a unit cell. The unit cell is defined into a certain shape in plan view at a main surface of the semiconductor layer, and a plurality of the unit cells is coupled in a chain manner to form a unit chain structure with a constriction. The certain shape of the unit cell is defined by an outer edge of a virtual region of the semiconductor layer defined so as to include the source region and the well region inside and by respective outer edges of the source region and the well region at a joint with a different unit cell. An active region is composed of a plurality of the unit chain structures. The unit chain structures are arranged so as to avoid generation of a gap between the unit cells of adjacent ones of the unit chain structures.
摘要翻译：半导体层，阱区和源极区形成单元。单元电池在半导体层的主表面的平面图中被限定为一定的形状，并且多个单元电池以链状的方式耦合以形成具有缩小的单位链结构。单元电池的特定形状由半导体层的虚拟区域的外边缘限定，以便包括源极区域和阱区域以及源极区域和在接合处的阱区域的相应外边缘与不同的单元格。有源区域由多个单位链结构组成。单元链结构被布置为避免在相邻单元链结构的单元电池之间产生间隙。

7. 发明授权

US08969960B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08969960B2
公开(公告)日：2015-03-03
申请号：US14346466
申请日：2012-06-07
申请人： Akihiko Furukawa , Yasuhiro Kagawa , Naruhisa Miura , Masayuki Imaizumi , Kazuyasu Nishikawa
发明人： Akihiko Furukawa , Yasuhiro Kagawa , Naruhisa Miura , Masayuki Imaizumi , Kazuyasu Nishikawa
IPC分类号： H01L29/76 , H01L29/94 , H01L23/60 , H01L29/66 , H01L29/78 , H01L27/02 , H01L29/06 , H01L29/16
CPC分类号： H01L23/60 , H01L27/0296 , H01L29/0696 , H01L29/1608 , H01L29/66068 , H01L29/7803 , H01L29/7804 , H01L29/7811 , H01L29/7815 , H01L2924/0002 , H01L2924/00
摘要： A power semiconductor device includes a second conductive type sense outer-peripheral well formed to surround a plurality of sense wells on the surface of a drift layer, a first conductive type main-cell source region selectively formed on the surface of the main cell well, a first conductive type sense source region selectively formed on the surface of the sense well, a first conductive type capacitor lower electrode region selectively formed on the surface of the sense outer-peripheral well, a gate insulation film formed on the channel regions and on the sense outer-peripheral well, a gate electrode formed on the gate insulation film, and a sense pad electrically connected to the sense well and the sense source region as well as on the sense outer-peripheral well and the capacitor lower electrode region.
摘要翻译：功率半导体器件包括形成为围绕漂移层表面上的多个感测阱的第二导电型感测外周阱，选择性地形成在主电池阱的表面上的第一导电型主电池源区，选择性地形成在感测阱的表面上的第一导电型感测源极区，选择性地形成在感测外周阱的表面上的第一导电型电容器下电极区域，形成在沟道区域上的栅极绝缘膜形成在栅极绝缘膜上的栅电极，以及与感测阱和感测源区以及感应外周阱和电容器下电极区电连接的检测焊盘。

8. 发明申请

US20140299891A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20140299891A1
公开(公告)日：2014-10-09
申请号：US14355737
申请日：2012-09-24
申请人： Shiro Hino , Naruhisa Miura , Akihiko Furukawa , Tomokatsu Watanabe , Kenichi Ohtsuka , Hiroshi Watanabe , Yuji Ebiike
发明人： Shiro Hino , Naruhisa Miura , Akihiko Furukawa , Tomokatsu Watanabe , Kenichi Ohtsuka , Hiroshi Watanabe , Yuji Ebiike
IPC分类号： H01L29/06 , H01L29/10 , H01L29/16
CPC分类号： H01L29/0619 , H01L29/0688 , H01L29/0692 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/7396 , H01L29/7802 , H01L29/808
摘要： A semiconductor device that can improve reliability while suppressing increase of a conduction loss or a switching loss. In the semiconductor device, when a two-dimensional shape on a main surface of the semiconductor substrate is an unit cell, the shape being a repeating unit of a plurality of well regions periodically disposed in a surface layer of a drift layer, one unit cell and another unit cell adjacent in an x-axis direction are disposed misaligned in a y-axis direction, and one unit cell and another unit cell adjacent in the y-axis direction are disposed misaligned in the x-axis direction.
摘要翻译：一种半导体器件，其可以在抑制导通损耗的增加或开关损耗的同时提高可靠性。在半导体装置中，当在半导体基板的主表面上的二维形状是单位电池时，形状是周期性地设置在漂移层的表面层中的多个阱区域的重复单元，一个单元电池并且在x轴方向上相邻的另一个单元单元在y轴方向上不对准地设置，并且在y轴方向上相邻的一个单位单元和另一个单位单元在x轴方向上不对准地设置。

9. 发明申请

US20140191251A1 SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：US20140191251A1
公开(公告)日：2014-07-10
申请号：US14240017
申请日：2011-09-21
申请人： Yoichiro Tarui , Eisuke Suekawa , Naoki Yutani , Shiro Hino , Naruhisa Miura , Masayuki Imaizumi
发明人： Yoichiro Tarui , Eisuke Suekawa , Naoki Yutani , Shiro Hino , Naruhisa Miura , Masayuki Imaizumi
IPC分类号： H01L29/78 , H01L29/16 , H01L21/02 , H01L29/66
CPC分类号： H01L29/78 , H01L21/02529 , H01L21/046 , H01L21/0485 , H01L29/086 , H01L29/1608 , H01L29/66068 , H01L29/66477 , H01L29/7802
摘要： It is expected that both reduction of the resistance of a source region and reduction of a leakage current in a gate oxide film be achieved in an MOSFET in a silicon carbide semiconductor device. A leakage current to occur in a gate oxide film of the MOSFET is suppressed by reducing roughness at an interface between a source region and the gate oxide film. If an impurity concentration is to become high at a surface portion of the source region, the gate oxide film is formed by dry oxidation or CVD process. If the gate oxide film is formed by wet oxidation, the impurity concentration at the surface portion of the source region is controlled at a low level.
摘要翻译：期望在碳化硅半导体器件中的MOSFET中实现源极区域的电阻降低和栅极氧化膜中的漏电流的减小。通过减少源极区域和栅极氧化物膜之间的界面处的粗糙度来抑制在MOSFET的栅极氧化膜中发生的漏电流。如果杂质浓度在源极区的表面部分变高，则通过干法氧化或CVD法形成栅极氧化膜。如果通过湿式氧化形成栅极氧化膜，则源极区域的表面部分处的杂质浓度被控制在低水平。

10. 发明授权

US08492836B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08492836B2
公开(公告)日：2013-07-23
申请号：US13500659
申请日：2009-10-14
申请人： Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Shiro Hino , Akihiko Furukawa
发明人： Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Shiro Hino , Akihiko Furukawa
IPC分类号： H01L29/66
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/42368 , H01L29/42372 , H01L29/66068
摘要： In a semiconductor device according to the present invention, a p-type well region disposed in an outer peripheral portion of the power semiconductor device is divided into two parts, that is, an inside and an outside, and a field oxide film having a greater film thickness than the gate insulating film is provided on a well region at the outside to an inside of an inner periphery of the well region. Therefore, it is possible to prevent, in the gate insulating film, a dielectric breakdown due to the voltage generated by the flow of the displacement current in switching.
摘要翻译：在根据本发明的半导体器件中，设置在功率半导体器件的外周部分中的p型阱区被分成两部分，即内部和外部，并且具有更大的场氧化物膜膜厚比栅极绝缘膜设置在外部的阱区域到阱区的内周的内侧。因此，可以防止在栅极绝缘膜中由于切换中的位移电流的流动而产生的电压引起的电介质击穿。

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