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1. 发明授权

US09076761B2 Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US09076761B2
公开(公告)日：2015-07-07
申请号：US14116259
申请日：2012-05-31
申请人： Tomokatsu Watanabe , Naruhisa Miura , Masayuki Furuhashi , Shiro Hino , Toshikazu Tanioka
发明人： Tomokatsu Watanabe , Naruhisa Miura , Masayuki Furuhashi , Shiro Hino , Toshikazu Tanioka
IPC分类号： H01L29/417 , H01L29/10 , H01L29/78 , H01L29/66 , H01L29/08 , H01L29/16
CPC分类号： H01L29/41741 , H01L29/086 , H01L29/105 , H01L29/1608 , H01L29/41725 , H01L29/41766 , H01L29/66068 , H01L29/7802 , H01L29/7827
摘要： A silicon carbide semiconductor device that is able to increase the gate reliability, and to provide a method for manufacturing the silicon carbide semiconductor device, and that includes: a source electrode selectively formed on a source region; a gate insulating film formed so as to extend over the source region; and a gate electrode formed on the gate insulating film. The source region includes a first source region located below the source electrode, and a second source region surrounding the first source region. The doping concentration in a superficial layer of the second source region is lower than the doping concentration in a superficial layer of the first source region. The doping concentration in the second source region is higher in a deep portion than in a superficial portion thereof.
摘要翻译：一种能够提高栅极可靠性并提供一种制造碳化硅半导体器件的方法的碳化硅半导体器件，其包括：源极选择性地形成在源极区上; 形成为在源极区域上延伸的栅极绝缘膜; 以及形成在栅极绝缘膜上的栅电极。源极区包括位于源电极下方的第一源极区域和围绕第一源极区域的第二源极区域。第二源极区的表面层中的掺杂浓度低于第一源区的表面层中的掺杂浓度。第二源极区域中的掺杂浓度在深部比在其表面部分高。

2. 发明授权

US08716717B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08716717B2
公开(公告)日：2014-05-06
申请号：US13816511
申请日：2011-04-15
申请人： Tsuyoshi Kawakami , Akihiko Furukawa , Naruhisa Miura , Yasuhiro Kagawa , Kenji Hamada , Yoshiyuki Nakaki
发明人： Tsuyoshi Kawakami , Akihiko Furukawa , Naruhisa Miura , Yasuhiro Kagawa , Kenji Hamada , Yoshiyuki Nakaki
IPC分类号： H01L29/12
CPC分类号： H01L29/12 , H01L21/0465 , H01L21/265 , H01L21/266 , H01L29/0615 , H01L29/0619 , H01L29/063 , H01L29/0634 , H01L29/0692 , H01L29/0878 , H01L29/1608 , H01L29/6606 , H01L29/66068 , H01L29/66128 , H01L29/66143 , H01L29/66659 , H01L29/7835 , H01L29/8611 , H01L29/872
摘要： A RESURF layer including a plurality of P-type implantation layers having a low concentration of P-type impurity is formed adjacent to an active region. The RESURF layer includes a first RESURF layer, a second RESURF layer, a third RESURF layer, a fourth RESURF layer, and a fifth RESURF layer that are arranged sequentially from the P-type base side so as to surround the P-type base. The second RESURF layer is configured with small regions having an implantation amount equal to that of the first RESURF layer and small regions having an implantation amount equal to that of the third RESURF layer being alternately arranged in multiple. The fourth RESURF layer is configured with small regions having an implantation amount equal to that of the third RESURF layer and small regions having an implantation amount equal to that of the fifth RESURF layer being alternately arranged in multiple.
摘要翻译：在活性区域附近形成包括具有低浓度P型杂质的多个P型注入层的RESURF层。 RESURF层包括从P型基底侧依次布置以围绕P型基底的第一RESURF层，第二RESURF层，第三RESURF层，第四RESURF层和第五RESURF层。第二RESURF层配置有具有等于第一RESURF层的注入量的小区域，并且具有与第三RESURF层的注入量相等的注入量的小区域被交替排列成多个。第四RESURF层配置有具有等于第三RESURF层的注入量的小区域，并且具有与第五RESURF层的注入量相等的注入量的小区域被交替排列成多个。

3. 发明授权

US08680538B2 Silicon carbide semiconductor device 失效
标题翻译：碳化硅半导体器件
公开(公告)号：US08680538B2
公开(公告)日：2014-03-25
申请号：US12867061
申请日：2008-02-12
申请人： Yoichiro Tarui , Kenichi Ohtsuka , Naruhisa Miura , Yoshinori Matsuno , Masayuki Imaizumi
发明人： Yoichiro Tarui , Kenichi Ohtsuka , Naruhisa Miura , Yoshinori Matsuno , Masayuki Imaizumi
IPC分类号： H01L29/15
CPC分类号： H01L29/66068 , H01L23/3171 , H01L23/3192 , H01L29/0615 , H01L29/0619 , H01L29/0638 , H01L29/0661 , H01L29/0692 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/6606 , H01L29/7811 , H01L29/8611 , H01L29/8613 , H01L29/872 , H01L2924/0002 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
摘要： In order to obtain a silicon carbide semiconductor device that ensures both stability of withstand voltage and reliability in high-temperature operations in its termination end-portion provided for electric-field relaxation in the perimeter of a cell portion driven as a semiconductor element, the termination end-portion is provided with an inorganic protection film having high heat resistance that is formed on an exposed surface of a well region as a first region formed on a side of the cell portion, and an organic protection film having a high electrical insulation capability with a little influence by electric charges that is formed on a surface of an electric-field relaxation region formed in contact relation to an outer lateral surface of the well region and apart from the cell portion, and on an exposed surface of the silicon carbide layer.
摘要翻译：为了获得在作为半导体元件驱动的单元部分的周边中提供用于电场弛豫的其终端部分中的高温操作中的耐受电压的稳定性和可靠性的确保的碳化硅半导体器件，端部设有具有高耐热性的无机保护膜，所述无机保护膜形成在作为形成在电池单元侧的第一区域的阱区的暴露表面上，以及具有高电绝缘能力的有机保护膜，在形成于与阱区的外侧表面形成并且与电池部分隔开的电场弛豫区域的表面上以及在碳化硅层的暴露表面上的电荷的一点影响。

4. 发明申请

US20140001472A1 SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：US20140001472A1
公开(公告)日：2014-01-02
申请号：US13995993
申请日：2011-05-18
申请人： Akihiko Furukawa , Yasuhiro Kagawa , Naruhisa Miura , Masayuki Imaizumi
发明人： Akihiko Furukawa , Yasuhiro Kagawa , Naruhisa Miura , Masayuki Imaizumi
IPC分类号： H01L29/16 , H01L21/02
CPC分类号： H01L21/02529 , H01L21/8213 , H01L27/0629 , H01L29/0619 , H01L29/0692 , H01L29/1608 , H01L29/45 , H01L29/47 , H01L29/6606 , H01L29/66068 , H01L29/7802 , H01L29/7828 , H01L29/872
摘要： A silicon carbide semiconductor device including an SBD measuring a temperature of a silicon carbide semiconductor element. The silicon carbide semiconductor device includes a MOSFET formed on a silicon carbide epitaxial substrate, and an SBD section measuring a temperature of the MOSFET. The SBD section includes an n-type cathode region in a surface portion of a silicon carbide drift layer; an anode titanium electrode formed on the cathode region, the electrode serving as a Schottky electrode; an n-type cathode contact region of a higher concentration than that of the cathode region, formed in the surface portion of the silicon carbide drift layer to make contact with the cathode region; a cathode ohmic electrode formed on the cathode contact region; and a first p-type well region formed within the silicon carbide drift layer to surround peripheries of the cathode region and the cathode contact region.
摘要翻译：一种碳化硅半导体器件，包括测量碳化硅半导体元件的温度的SBD。碳化硅半导体器件包括形成在碳化硅外延衬底上的MOSFET和测量MOSFET的温度的SBD部分。 SBD部分包括在碳化硅漂移层的表面部分中的n型阴极区域; 在阴极区域形成的阳极钛电极，用作肖特基电极的电极; 形成在碳化硅漂移层的表面部分中以与阴极区接触的n型阴极接触区域，其浓度高于阴极区域; 形成在阴极接触区域上的阴极欧姆电极; 以及形成在碳化硅漂移层内以围绕阴极区域和阴极接触区域的周边的第一p型阱区域。

5. 发明授权

US08367536B2 Method for manufacturing silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件的制造方法
公开(公告)号：US08367536B2
公开(公告)日：2013-02-05
申请号：US13319739
申请日：2010-07-16
申请人： Hiroshi Watanabe , Naruhisa Miura
发明人： Hiroshi Watanabe , Naruhisa Miura
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/7802 , H01L29/0696 , H01L29/1608 , H01L29/66068
摘要： The present invention includes steps below: (a) forming, on a drift layer, a first ion implantation mask and a second ion implantation mask individually by photolithography to form a third ion implantation mask, the first ion implantation mask having a mask region corresponding to a channel region and having a first opening corresponding to a source region, the second ion implantation mask being positioned in contact with an outer edge of the first ion implantation mask and configured to form a base region; (b) implanting impurities of a first conductivity type from the first opening with an ion beam using the third ion implantation mask to form a source region in an upper layer part of the silicon carbide drift layer; (c) removing the first ion implantation mask after the formation of the source region; and (d) implanting impurities of a second conductivity type with an ion beam from a second opening formed in the second ion implantation mask after the removal of the first ion implantation mask to form a base region deeper than the source region in the upper layer part of the drift layer.
摘要翻译：本发明包括以下步骤：（a）通过光刻法分别在漂移层上形成第一离子注入掩模和第二离子注入掩模，以形成第三离子注入掩模，第一离子注入掩模具有对应于沟道区，具有对应于源极区的第一开口，所述第二离子注入掩模定位成与所述第一离子注入掩模的外边缘接触并且被配置为形成基区; （b）使用第三离子注入掩模，用离子束从第一开口注入第一导电类型的杂质，以在碳化硅漂移层的上层部分中形成源极区; （c）在形成源极区域之后去除第一离子注入掩模; 以及（d）在除去第一离子注入掩模之后，从形成在第二离子注入掩模中的第二开口用离子束注入第二导电类型的杂质以形成比上层部分中的源极区更深的基极区的漂移层。

6. 发明授权

US08222649B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08222649B2
公开(公告)日：2012-07-17
申请号：US12161592
申请日：2006-11-17
申请人： Naruhisa Miura , Keiko Fujihira , Kenichi Otsuka , Masayuki Imaizumi
发明人： Naruhisa Miura , Keiko Fujihira , Kenichi Otsuka , Masayuki Imaizumi
IPC分类号： H01L29/161 , H01L29/167 , H01L21/36
CPC分类号： H01L29/0661 , H01L29/0615 , H01L29/0878 , H01L29/1608 , H01L29/7811
摘要： A semiconductor device and a method of manufacturing the same, to appropriately determine an impurity concentration distribution of a field relieving region and reduce an ON-resistance. The semiconductor device includes a substrate, a first drift layer, a second drift layer, a first well region, a second well region, a current control region, and a field relieving region. The first well region is disposed continuously from an end portion adjacent to the vicinity of outer peripheral portion of the second drift layer to a portion of the first drift layer below the vicinity of outer peripheral portion. The field relieving region is so disposed in the first drift layer as to be adjacent to the first well region.
摘要翻译：一种半导体器件及其制造方法，用于适当地确定场释放区域的杂质浓度分布并降低导通电阻。半导体器件包括衬底，第一漂移层，第二漂移层，第一阱区，第二阱区，电流控制区和场释放区。第一阱区从与第二漂移层的外周部附近相邻的端部连续配置到第一漂移层的位于外周部附近的部分。场解除区域被布置在第一漂移层中以与第一阱区域相邻。

7. 发明申请

US20120074508A1 POWER SEMICONDUCTOR DEVICE 审中-公开
标题翻译：功率半导体器件
公开(公告)号：US20120074508A1
公开(公告)日：2012-03-29
申请号：US13309305
申请日：2011-12-01
申请人： Kenichi OHTSUKA , Naruhisa Miura , Masayuki Imaizumi , Tatsuo Oomori
发明人： Kenichi OHTSUKA , Naruhisa Miura , Masayuki Imaizumi , Tatsuo Oomori
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/45 , H01L29/4925 , H01L29/4941 , H01L29/66068 , H01L29/7828
摘要： A power semiconductor device less prone to cause a reaction between a metal material for interconnection and an electrode or the like connected to a semiconductor region during the high-temperature operation thereof and less prone to be strained during the high-temperature operation thereof. The power semiconductor device can be an SiC power device or the like in which a first metal layer containing at least one selected from the group consisting of Pt, Ti, Mo, W and Ta is formed on a source electrode formed on the semiconductor region, such as a source region or the like. A second metal layer containing at least one selected from the group consisting of Mo, W and Cu is formed on the first metal layer. A third metal layer containing at least one selected from the group consisting of Pt, Mo and W is formed on the second metal layer.
摘要翻译：功率半导体器件在其高温操作期间不容易引起用于互连的金属材料与连接到半导体区域的电极等之间的反应，并且在其高温操作期间不易于变形。功率半导体器件可以是在形成在半导体区域上的源电极上形成含有选自Pt，Ti，Mo，W和Ta中的至少一种的第一金属层的SiC功率器件等，例如源区域等。在第一金属层上形成含有选自Mo，W和Cu中的至少一种的第二金属层。在第二金属层上形成含有选自Pt，Mo和W中的至少一种的第三金属层。

8. 发明申请

US20110278599A1 SILICON CARBIDE SEMICONDUCTOR DEVICE 有权
标题翻译：硅碳化硅半导体器件
公开(公告)号：US20110278599A1
公开(公告)日：2011-11-17
申请号：US13146812
申请日：2010-02-23
申请人： Yukiyasu Nakao , Masayuki Imaizumi , Shuhei Nakata , Naruhisa Miura
发明人： Yukiyasu Nakao , Masayuki Imaizumi , Shuhei Nakata , Naruhisa Miura
IPC分类号： H01L29/161
CPC分类号： H01L29/1608 , H01L21/0465 , H01L29/0615 , H01L29/0657 , H01L29/0696 , H01L29/1095 , H01L29/42372 , H01L29/45 , H01L29/66068 , H01L29/7396 , H01L29/7811 , H01L29/7816
摘要： A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery immediately below a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer.
摘要翻译：一种能够提高开关速度而不破坏栅极绝缘膜的SiC半导体器件。此外，在由SiC构成的n型半导体基板的SiC-MOSFET中，p型半导体层全部或部分设置在p型阱层的上表面上，该p型阱层的横面为最大面积在设置在n型漂移层中的多个p型阱层之中，并且布置在栅电极焊盘正下方的最外周。 p型半导体层中含有的杂质的浓度优选大于p型阱层的浓度。

9. 发明授权

US06566734B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06566734B2
公开(公告)日：2003-05-20
申请号：US09809211
申请日：2001-03-16
申请人： Kohei Sugihara , Toshiyuki Oishi , Naruhisa Miura , Yuji Abe , Yasunori Tokuda
发明人： Kohei Sugihara , Toshiyuki Oishi , Naruhisa Miura , Yuji Abe , Yasunori Tokuda
IPC分类号： H01L29788
CPC分类号： H01L29/66651 , H01L29/1045 , H01L29/1054 , H01L29/66492 , H01L29/66545 , H01L29/66621
摘要： In making a field effect transistor, a dummy gate electrode is formed before a gate electrode is formed. Extension regions, a side wall silicon nitride film, source/drain regions, a silicon oxide film, and other elements are formed with respect to the dummy gate electrode. The dummy gate electrode is removed, and a part of the extension regions diffused into a region immediately under the dummy gate electrode is removed. The removed part is filled with silicon selection epitaxial film. Thereafter, the intended gate electrode is formed. This production method produces a field effect transistor that prevents deterioration of electrical characteristics caused by the short channel effect and parasitic resistance.
摘要翻译：在制作场效应晶体管时，在形成栅电极之前形成伪栅电极。相对于虚拟栅电极形成延伸区域，侧壁氮化硅膜，源极/漏极区域，氧化硅膜等元件。去除虚拟栅电极，并且去除扩散到虚拟栅电极正下方的区域中的一部分延伸区域。被去除的部分填充硅选择外延膜。之后，形成预定的栅电极。该制造方法产生场效应晶体管，其防止由短沟道效应和寄生电阻引起的电特性的劣化。

10. 发明申请

US20150108564A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150108564A1
公开(公告)日：2015-04-23
申请号：US14400025
申请日：2013-03-12
申请人： Naruhisa Miura , Shiro Hino , Akihiko Furukawa , Yuji Abe , Shuhei Nakata , Masayuki Imaizumi , Yasuhiro Kagawa
发明人： Naruhisa Miura , Shiro Hino , Akihiko Furukawa , Yuji Abe , Shuhei Nakata , Masayuki Imaizumi , Yasuhiro Kagawa
IPC分类号： H01L29/78 , H01L29/16 , H01L29/423 , H01L29/10 , H01L29/08
CPC分类号： H01L29/7802 , H01L21/046 , H01L29/0615 , H01L29/0619 , H01L29/086 , H01L29/1033 , H01L29/1095 , H01L29/1608 , H01L29/42356 , H01L29/66068 , H01L29/66893 , H01L29/7813 , H01L29/7827 , H01L29/7836 , H01L29/8083
摘要： A source region of a MOSFET includes: a source contact region connected to a source pad; a source extension region adjacent to a channel region in a well region; and a source resistance control region arranged between the source extension region and the source contact region. The source resistance control region is different in an impurity concentration from the source extension region and the source contact region. These three regions are connected in series between the source pad and the channel region in the well region.
摘要翻译： MOSFET的源极区域包括：源极接触区域，连接到源极焊盘; 源极延伸区域，其邻近阱区域中的沟道区域; 以及源极电阻控制区域，其布置在源极延伸区域和源极接触区域之间。源极电阻控制区域与源极延伸区域和源极接触区域的杂质浓度不同。这三个区域串联连接在源极区和阱区中的沟道区之间。

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