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1. 发明授权

US08624214B2 Semiconductor device having a resistance variable element and a manufacturing method thereof 有权
标题翻译：具有电阻可变元件的半导体器件及其制造方法
公开(公告)号：US08624214B2
公开(公告)日：2014-01-07
申请号：US12866359
申请日：2009-06-08
申请人： Takumi Mikawa , Kazuhiko Shimakawa
发明人： Takumi Mikawa , Kazuhiko Shimakawa
IPC分类号： H01L29/02 , H01L47/00 , H01L21/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/32 , G11C2213/34 , H01L27/24
摘要： A semiconductor device (100) of the present invention has a structure in which an interlayer insulating layer (115) is formed on an uppermost wire (114), contacts (116, 117) penetrate the interlayer insulating layer (115), a lower electrode (118a) of the resistance variable element is formed on the interlayer insulating layer (115) to cover the contact (116), and resistance variable layer (119) is formed on the interlayer insulating layer (115) to cover the lower electrode (118a) and the contact (117). The contact (116) and the lower electrode (118a) serve as a first terminal, while the contact (117) serves as a second terminal.
摘要翻译：本发明的半导体器件（100）具有层间绝缘层（115）形成在最上层导线（114）上的结构，触点（116,117）穿过层间绝缘层（115），下电极在层间绝缘层（115）上形成电阻可变元件（118a）以覆盖触点（116），并且在层间绝缘层（115）上形成电阻变化层（119）以覆盖下电极（118a））和触点（117）。触点（116）和下电极（118a）用作第一端子，而触头（117）用作第二端子。

2. 发明授权

US08384061B2 Nonvolatile memory device and manufacturing method 有权
标题翻译：非易失存储器件及其制造方法
公开(公告)号：US08384061B2
公开(公告)日：2013-02-26
申请号：US12745190
申请日：2008-11-06
申请人： Takumi Mikawa , Kenji Tominaga , Kazuhiko Shimakawa , Ryotaro Azuma
发明人： Takumi Mikawa , Kenji Tominaga , Kazuhiko Shimakawa , Ryotaro Azuma
IPC分类号： H01L27/26 , H01L29/8605 , H01L21/02
CPC分类号： H01L27/2409 , G11C13/0002 , G11C2213/71 , G11C2213/72 , H01L27/101 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1683
摘要： A nonvolatile memory device of the present invention includes a substrate (1), first wires (3), first resistance variable elements (5) and lower electrodes (6) of first diode elements which are filled in first through-holes (4), respectively, second wires (11) which cross the first wires 3 perpendicularly to the first wires 3, respectively, and each of which includes a semiconductor layer (7) of a first diode elements, a conductive layer (8) and a semiconductor layer (10) of a second diode elements which are stacked together in this order, second resistance variable elements (16) and upper electrodes (14) of second diode elements which are filled into second through holes (13), respectively, and third wires (17), and the conductive layer (8) of each second wires (11) also serves as the upper electrode of the first diode elements (9) and the lower electrode of the second diode elements (15).
摘要翻译：本发明的非易失性存储器件包括填充在第一通孔（4）中的基片（1），第一布线（3），第一电阻可变元件（5）和第一二极管元件的下电极（6）分别与第一布线3分别垂直于第一布线3交叉的第二布线（11），每条布线包括第一二极管元件的半导体层（7），导电层（8）和半导体层（ 10）分别被填充到第二通孔（13）中的第二电阻可变元件（16）和第二二极管元件的上电极（14）以及第三电线（17）），并且每个第二布线（11）的导电层（8）也用作第一二极管元件（9）的上电极和第二二极管元件（15）的下电极。

3. 发明申请

US20100264393A1 NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20100264393A1
公开(公告)日：2010-10-21
申请号：US12747060
申请日：2008-12-02
申请人： Takumi Mikawa , Kenji Tominaga , Kazuhiko Shimakawa , Ryotaro Azuma
发明人： Takumi Mikawa , Kenji Tominaga , Kazuhiko Shimakawa , Ryotaro Azuma
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L27/101 , H01L27/2409 , H01L27/2472 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： A nonvolatile memory device of the present invention comprises a substrate (1), first wires (3), first filling constituents (5) filled into first through-holes (4), respectively, second wires (11) which cross the first wires (3) perpendicularly to the first wires (3), respectively, each of the second wires (11) including a plurality of layers including a resistance variable layer (6) of each of first resistance variable elements, a conductive layer (7) and a resistance variable layer (8) of each of second resistance variable elements which are stacked together in this order, second filling constituents (14) filled into second through-holes (13), respectively, and third wires (15), and the conductive layer (7) of the second wires (11) serves as the electrodes of the first resistance variable elements (9) and the electrodes of the second resistance variable elements (10).
摘要翻译：本发明的非易失性存储装置包括基板（1），第一布线（3），分别填充到第一通孔（4）中的第一填充构件（5），分别穿过第一布线 3）分别垂直于第一导线（3），每个第二导线（11）包括多个层，包括第一电阻可变元件中的每一个的电阻变化层（6），导电层（7）和按顺序堆叠在一起的第二电阻可变元件的电阻变化层（8），分别填充到第二通孔（13）中的第二填充组分（14）和第三导线（15），以及导电层第二电线（11）的电极（7）用作第一电阻可变元件（9）的电极和第二电阻可变元件（10）的电极。

4. 发明授权

US08198618B2 Nonvolatile memory device and manufacturing method thereof 有权
标题翻译：非易失存储器件及其制造方法
公开(公告)号：US08198618B2
公开(公告)日：2012-06-12
申请号：US12747060
申请日：2008-12-02
申请人： Takumi Mikawa , Kenji Tominaga , Kazuhiko Shimakawa , Ryotaro Azuma
发明人： Takumi Mikawa , Kenji Tominaga , Kazuhiko Shimakawa , Ryotaro Azuma
IPC分类号： H01L29/02
CPC分类号： H01L27/101 , H01L27/2409 , H01L27/2472 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： A nonvolatile memory device of the present invention comprises a substrate (1), first wires (3), first filling constituents (5) filled into first through-holes (4), respectively, second wires (11) which cross the first wires (3) perpendicularly to the first wires (3), respectively, each of the second wires (11) including a plurality of layers including a resistance variable layer (6) of each of first resistance variable elements, a conductive layer (7) and a resistance variable layer (8) of each of second resistance variable elements which are stacked together in this order, second filling constituents (14) filled into second through-holes (13), respectively, and third wires (15), and the conductive layer (7) of the second wires (11) serves as the electrodes of the first resistance variable elements (9) and the electrodes of the second resistance variable elements (10).
摘要翻译：本发明的非易失性存储装置包括基板（1），第一布线（3），分别填充到第一通孔（4）中的第一填充构件（5），分别穿过第一布线 3）分别垂直于第一导线（3），每个第二导线（11）包括多个层，包括第一电阻可变元件中的每一个的电阻变化层（6），导电层（7）和按顺序堆叠在一起的第二电阻可变元件的电阻变化层（8），分别填充到第二通孔（13）中的第二填充组分（14）和第三导线（15），以及导电层第二电线（11）的电极（7）用作第一电阻可变元件（9）的电极和第二电阻可变元件（10）的电极。

5. 发明申请

US20100321095A1 SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, SEMICONDUCTOR CHIP AND SYSTEM 有权
标题翻译：半导体器件，半导体器件的制造方法，半导体芯片和系统
公开(公告)号：US20100321095A1
公开(公告)日：2010-12-23
申请号：US12866359
申请日：2009-06-08
申请人： Takumi Mikawa , Kazuhiko Shimakawa
发明人： Takumi Mikawa , Kazuhiko Shimakawa
IPC分类号： H01H85/00 , H01L45/00 , H01L21/02
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/32 , G11C2213/34 , H01L27/24
摘要： A semiconductor device (100) of the present invention has a structure in which an interlayer insulating layer (115) is formed on an uppermost wire (114), contacts (116, 117) penetrate the interlayer insulating layer (115), a lower electrode (118a) of the resistance variable element is formed on the interlayer insulating layer (115) to cover the contact (116), and resistance variable layer (119) is formed on the interlayer insulating layer (115) to cover the lower electrode (118a) and the contact (117). The contact (116) and the lower electrode (118a) serve as a first terminal, while the contact (117) serves as a second terminal.
摘要翻译：本发明的半导体器件（100）具有层间绝缘层（115）形成在最上层导线（114）上的结构，触点（116,117）穿过层间绝缘层（115），下电极在层间绝缘层（115）上形成电阻可变元件（118a）以覆盖触点（116），并且在层间绝缘层（115）上形成电阻变化层（119）以覆盖下电极（118a））和触点（117）。触点（116）和下电极（118a）用作第一端子，而触头（117）用作第二端子。

6. 发明申请

US20100258779A1 NONVOLATILE MEMORY DEVICE AND MANUFACTURING MEHTOD THEREOF 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20100258779A1
公开(公告)日：2010-10-14
申请号：US12745190
申请日：2008-11-06
申请人： Takumi Mikawa , Kenji Tominaga , Kazuhiko Shimakawa , Ryotaro Azuma
发明人： Takumi Mikawa , Kenji Tominaga , Kazuhiko Shimakawa , Ryotaro Azuma
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L27/2409 , G11C13/0002 , G11C2213/71 , G11C2213/72 , H01L27/101 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1683
摘要： A nonvolatile memory device of the present invention includes a substrate (1), first wires (3), first resistance variable elements (5) and lower electrodes (6) of first diode elements which are filled in first through-holes (4), respectively, second wires (11) which cross the first wires 3 perpendicularly to the first wires 3, respectively, and each of which includes a semiconductor layer (7) of a first diode elements, a conductive layer (8) and a semiconductor layer (10) of a second diode elements which are stacked together in this order, second resistance variable elements (16) and upper electrodes (14) of second diode elements which are filled into second through holes (13), respectively, and third wires (17), and the conductive layer (8) of each second wires (11) also serves as the upper electrode of the first diode elements (9) and the lower electrode of the second diode elements (15).
摘要翻译：本发明的非易失性存储器件包括填充在第一通孔（4）中的基片（1），第一布线（3），第一电阻可变元件（5）和第一二极管元件的下电极（6）分别与第一布线3分别垂直于第一布线3交叉的第二布线（11），每条布线包括第一二极管元件的半导体层（7），导电层（8）和半导体层（ 10）分别被填充到第二通孔（13）中的第二电阻可变元件（16）和第二二极管元件的上电极（14）以及第三电线（17）），并且每个第二布线（11）的导电层（8）也用作第一二极管元件（9）的上电极和第二二极管元件（15）的下电极。

7. 发明授权

US08902629B2 Forming method of performing forming on variable resistance nonvolatile memory element, and variable resistance nonvolatile memory device 有权
标题翻译：在可变电阻非易失性存储元件上形成的形成方法以及可变电阻非易失性存储器件
公开(公告)号：US08902629B2
公开(公告)日：2014-12-02
申请号：US13511275
申请日：2011-09-28
申请人： Ken Kawai , Kazuhiko Shimakawa , Koji Katayama , Shunsaku Muraoka
发明人： Ken Kawai , Kazuhiko Shimakawa , Koji Katayama , Shunsaku Muraoka
IPC分类号： G11C11/00 , H01L45/00 , H01L27/10 , H01L27/24 , G11C13/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2213/32 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： In forming, an automatic forming circuit (210) included in a nonvolatile memory device (200) causes a constant current IL to flow in a selected memory cell having a considerably high initial resistance. When the forming generates a filament path in the memory cell and thereby a resistance value is decreased, a potential of a node NBL and a potential of a node Nin are also decreased. If the potentials become lower than that of a reference voltage Vref, an output NO of a difference amplifier (303) for detecting forming success is activated, and a forming success signal Vfp is activated after a delay time depending on the number n of flip flops FF1 to FFn and a clock signal CLK. Thereby, a switch transistor (301) is in a non-conducting state and the forming on a variable resistance element is automatically terminated.
摘要翻译：在形成时，包括在非易失性存储器件（200）中的自动形成电路（210）使得恒定电流IL流过具有相当高的初始电阻的所选择的存储单元。当形成在存储单元中产生细丝通路并由此电阻值减小时，节点NBL的电位和节点Nin的电位也减小。如果电位变得低于参考电压Vref的电位，则激活用于检测成形成功的差分放大器（303）的输出NO，并且根据触发器的数量n在延迟时间之后激活形成成功信号Vfp FF1〜FFn和时钟信号CLK。由此，开关晶体管（301）处于非导通状态，可变电阻元件上的形成自动终止。

8. 发明授权

US08848421B2 Forming method of performing forming on variable resistance nonvolatile memory element, and variable resistance nonvolatile memory device 有权
标题翻译：在可变电阻非易失性存储元件上形成的形成方法以及可变电阻非易失性存储器件
公开(公告)号：US08848421B2
公开(公告)日：2014-09-30
申请号：US13634161
申请日：2011-03-28
申请人： Ken Kawai , Kazuhiko Shimakawa , Koji Katayama
发明人： Ken Kawai , Kazuhiko Shimakawa , Koji Katayama
IPC分类号： G11C11/00 , H01L45/00 , H01L27/10 , G11C13/00 , H01L27/24
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2213/32 , G11C2213/79 , H01L27/101 , H01L27/2436 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/16
摘要： A forming method of a variable resistance nonvolatile memory element capable of lowering a forming voltage and preventing variations of the forming voltage depending on variable resistance elements. The forming method is for initializing a variable resistance element, including a step (S24) of determining whether or not a current flowing in a 1T1R memory cell is greater than a reference current; a step (S22) of applying a forming positive voltage pulse having a pulse width (Tp(n)) is gradually increased when it is determined that the current is not greater than the reference current; and a step (S23) of applying a negative voltage pulse having a pulse width Tn equal to or shorter than a pulse width Tp(n). The determining step (S24), the application step (S22), and the application step (S23) are repeated until the forming becomes successful.
摘要翻译：一种可变电阻非易失性存储元件的形成方法，其能够降低形成电压并防止取决于可变电阻元件的形成电压的变化。该形成方法用于初始化可变电阻元件，包括确定在1T1R存储单元中流动的电流是否大于参考电流的步骤（S24）; 当确定电流不大于参考电流时，施加具有脉冲宽度（Tp（n））的形成正电压脉冲的步骤（S22）逐渐增加; 以及施加脉冲宽度Tn等于或短于脉冲宽度Tp（n）的负电压脉冲的步骤（S23）。重复确定步骤（S24），应用步骤（S22）和应用步骤（S23），直到形成成功。

9. 发明授权

US08687409B2 Variable resistance nonvolatile memory device 有权
标题翻译：可变电阻非易失性存储器件
公开(公告)号：US08687409B2
公开(公告)日：2014-04-01
申请号：US13639120
申请日：2012-05-30
申请人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma , Ken Kawai
发明人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma , Ken Kawai
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C2013/0083 , G11C2213/32 , G11C2213/72
摘要： A variable resistance nonvolatile memory device including memory cells provided at cross-points of first signal lines and second signal lines, each memory cell including a variable resistance element and a current steering element connected to the variable resistance element in series, the variable resistance nonvolatile memory device including a write circuit, a row selection circuit, and a column selection circuit, wherein the write circuit: sequentially selects blocks in an order starting from a block farthest from at least one of the row selection circuit and the column selection circuit and finishing with a block closest to the at least one of the row selection circuit and the column selection circuit; and performs, for each of the selected blocks, initial breakdown on each memory cell included in the selected block.
摘要翻译：一种可变电阻非易失性存储器件，包括设置在第一信号线和第二信号线的交叉点处的存储单元，每个存储单元包括可变电阻元件和连接到可变电阻元件串联的电流操舵元件，可变电阻非易失性存储器包括写入电路，行选择电路和列选择电路的装置，其中写入电路：从与行选择电路和列选择电路中的至少一个最远的块开始的顺序顺序地选择块，并且以最靠近行选择电路和列选择电路中的至少一个的块; 并且对于每个所选择的块，对包括在所选择的块中的每个存储器单元执行初始故障。

10. 发明申请

US20130077384A1 CROSS POINT VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE AND METHOD OF READING THEREBY 有权
标题翻译：交叉点可变电阻非易失性存储器件及其读取方法
公开(公告)号：US20130077384A1
公开(公告)日：2013-03-28
申请号：US13636169
申请日：2012-04-27
申请人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
发明人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
IPC分类号： G11C11/21
CPC分类号： G11C11/21 , G11C8/08 , G11C13/00 , G11C13/0007 , G11C13/0023 , G11C13/0028 , G11C13/004 , G11C2213/15 , G11C2213/71
摘要： A cross point variable resistance nonvolatile memory device including: a cross point memory cell array having memory cells each of which is placed at a different one of cross points of bit lines and word lines; a word line decoder circuit that selects at least one of the memory cells from the memory cell array; a read circuit that reads data from the selected memory cell; an unselected word line current source that supplies a first constant current; and a control circuit that controls the reading of the data from the selected memory cell, wherein the control circuit controls the word line decoder circuit, the read circuit, and the unselected word line current source so that when the read circuit reads data, the first constant current is supplied to an unselected word line.
摘要翻译：一种交叉点可变电阻非易失性存储器件，包括：具有存储单元的交叉点存储单元阵列，每个存储单元位于位线和字线的交叉点的不同位置; 字线解码器电路，从存储单元阵列中选择至少一个存储单元; 从所选择的存储单元读取数据的读取电路; 提供第一恒定电流的未选字线电流源; 以及控制电路，其控制来自所选择的存储单元的数据的读取，其中所述控制电路控制所述字线解码器电路，所述读取电路和所述未选字线电流源，使得当所述读取电路读取数据时，所述第一恒定电流被提供给未选择的字线。

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