专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US11742022B2 Semiconductor memory having both volatile and non-volatile functionality comprising resistive change material and method of operating 有权
公开(公告)号：US11742022B2
公开(公告)日：2023-08-29
申请号：US17540694
申请日：2021-12-02
申请人： Zeno Semiconductor, Inc.
发明人： Yuniarto Widjaja
IPC分类号： G11C11/00 , G11C14/00 , G11C11/404 , H01L29/78 , G11C11/4072 , G11C13/00 , H10B12/00 , H10B63/00 , H10N70/00 , H10N70/20 , G11C11/21 , G11C11/407
CPC分类号： G11C14/0045 , G11C11/21 , G11C11/404 , G11C11/407 , G11C11/4072 , G11C13/00 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C14/00 , G11C14/009 , G11C14/0027 , G11C14/0036 , H01L29/7841 , H10B12/056 , H10B12/20 , H10B63/30 , H10N70/00 , H10N70/231 , H10N70/826 , H10N70/8828 , H10N70/8833 , H10N70/8836 , G11C2013/0073 , H10B12/03 , H10N70/20
摘要： A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.

2. 发明申请

US20190103161A1 ACCESS SIGNAL ADJUSTMENT CIRCUITS AND METHODS FOR MEMORY CELLS IN A CROSS-POINT ARRAY 审中-公开
公开(公告)号：US20190103161A1
公开(公告)日：2019-04-04
申请号：US16126101
申请日：2018-09-10
申请人： Unity Semiconductor Corporation
发明人： Christophe Chevallier , Chang Hua Siau
IPC分类号： G11C13/00 , G11C11/21
CPC分类号： G11C13/0033 , G11C11/21 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0069
摘要： Systems, integrated circuits, and methods to utilize access signals to facilitate memory operations in scaled arrays of memory elements are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and line driver. The line driver can be configured to access a resistive memory element in the cross-point array.

3. 发明申请

US20180182460A1 Semiconductor Memory Having Both Volatile and Non-Volatile Functionality Comprising Resistive Change Material and Method of Operating 审中-公开
公开(公告)号：US20180182460A1
公开(公告)日：2018-06-28
申请号：US15893623
申请日：2018-02-10
申请人： Zeno Semiconductor, Inc.
发明人： Yuniarto Widjaja
IPC分类号： G11C14/00 , H01L45/00 , H01L29/78 , H01L27/24 , G11C13/00 , H01L27/108
CPC分类号： G11C14/0045 , G11C11/21 , G11C11/404 , G11C11/407 , G11C11/4072 , G11C13/00 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C14/00 , G11C14/0027 , G11C14/0036 , G11C14/009 , G11C2013/0073 , H01L27/10802 , H01L27/1085 , H01L27/10879 , H01L27/2436 , H01L29/7841 , H01L45/00 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147
摘要： A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.

4. 发明申请

US20170229178A1 A Semiconductor Memory Having Both Volatile and Non-Volatile Functionality Comprising Resistive Change Material and Method of Operating 有权
公开(公告)号：US20170229178A1
公开(公告)日：2017-08-10
申请号：US15499519
申请日：2017-04-27
申请人： Zeno Semiconductor, Inc.
发明人： Yuniarto Widjaja
IPC分类号： G11C14/00 , H01L45/00 , H01L27/24 , H01L29/78 , G11C13/00 , H01L27/108
CPC分类号： G11C14/0045 , G11C11/21 , G11C11/404 , G11C11/407 , G11C11/4072 , G11C13/00 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C14/00 , G11C14/0027 , G11C14/0036 , G11C14/009 , G11C2013/0073 , H01L27/10802 , H01L27/1085 , H01L27/10879 , H01L27/2436 , H01L29/7841 , H01L45/00 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147
摘要： A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.

5. 发明授权

US09679944B2 Electronic device and method for fabricating the same 有权
公开(公告)号：US09679944B2
公开(公告)日：2017-06-13
申请号：US14684039
申请日：2015-04-10
申请人： SK hynix Inc.
发明人： Jung-Nam Kim
IPC分类号： G11C11/21 , H01L27/24 , H01L43/02 , H01L43/08 , H01L45/00 , H01L27/22 , G06F13/16
CPC分类号： H01L27/2463 , G06F13/1673 , G11C11/21 , H01L27/228 , H01L27/2436 , H01L43/02 , H01L43/08 , H01L45/06 , H01L45/08 , H01L45/1233 , Y02D10/14
摘要： An electronic device is provided. An electronic device according to an example of the disclosed technology includes a semiconductor memory, the semiconductor memory including: a substrate including a recess formed in the substrate; a gate including at least a portion that is buried in the substrate; a junction formed at both sides of the gate in the substrate; and a memory element electrically connected to the junction at one side of the gate, wherein the junction includes: a barrier layer formed over the recess such that a thickness of the barrier layer formed over a bottom surface of the recess is different from that of the barrier layer formed over a side surface of the recess; a contact pad formed over the barrier layer so as to fill the recess; and an impurity region formed in the substrate and located under the contact pad.

6. 发明申请

US20160300613A1 Semiconductor Memory Having Both Volatile and Non-Volatile Functionality Comprising Resistive Change Material and Method of Operating 有权
公开(公告)号：US20160300613A1
公开(公告)日：2016-10-13
申请号：US15191137
申请日：2016-06-23
申请人： Zeno Semiconductor, Inc.
发明人： Yuniarto Widjaja
IPC分类号： G11C14/00 , H01L27/24 , G11C13/00 , H01L45/00 , G11C11/407 , H01L27/108 , H01L29/78
CPC分类号： G11C14/0045 , G11C11/21 , G11C11/404 , G11C11/407 , G11C11/4072 , G11C13/00 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C14/00 , G11C14/0027 , G11C14/0036 , G11C14/009 , G11C2013/0073 , H01L27/10802 , H01L27/1085 , H01L27/10879 , H01L27/2436 , H01L29/7841 , H01L45/00 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147
摘要： A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.

7. 发明授权

US09165979B2 Resistive memory 有权
标题翻译：电阻记忆
公开(公告)号：US09165979B2
公开(公告)日：2015-10-20
申请号：US14150654
申请日：2014-01-08
申请人： Bao Tran
发明人： Bao Tran
IPC分类号： H01L45/00 , H01L27/24 , G11C11/21 , B82Y10/00 , G11B9/14 , G11C11/54 , G11C13/02 , G11C13/04 , H01L51/42 , G11C13/00
CPC分类号： G01N33/0034 , B82Y10/00 , B82Y15/00 , B82Y40/00 , G01N27/122 , G01N27/128 , G01N27/4146 , G01N27/4148 , G11B9/14 , G11C11/21 , G11C11/54 , G11C13/0023 , G11C13/004 , G11C13/02 , G11C13/04 , H01L27/2463 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/16 , H01L51/4226 , H01L51/4253 , Y02E10/549 , Y10S977/762 , Y10S977/775 , Y10S977/938 , Y10S977/957
摘要： A memory device includes an upper conductive layer, a lower layer, and a resistive, optical or magnetic matrix positioned between the upper and lower layers.
摘要翻译：存储器件包括位于上层和下层之间的上导电层，下层和电阻式，光学或磁性矩阵。

8. 发明授权

US09076512B2 Synchronous nonvolatile memory device and memory system supporting consecutive division addressing DRAM protocol 有权
标题翻译：同步非易失性存储器件和支持连续划分寻址DRAM协议的存储器系统
公开(公告)号：US09076512B2
公开(公告)日：2015-07-07
申请号：US13724835
申请日：2012-12-21
申请人： Jin-Hyun Kim
发明人： Jin-Hyun Kim
IPC分类号： G11C11/22 , G11C8/18 , G11C11/21 , G11C7/10 , G11C13/00 , G11C7/22 , G11C11/16
CPC分类号： G11C8/18 , G11C7/10 , G11C7/22 , G11C11/16 , G11C11/21 , G11C11/22 , G11C13/0023
摘要： A nonvolatile memory device and system having a nonvolatile memory device accessible with a DRAM protocol for generating a first command signal and a second command signal based on a row address strobe signal and a column address strobe signal and storing an n-bit row address signal based on the first command signal, an n-bit column address signal based on the second command signal, and decoding the n-bit row address signal and the n-bit column address signal to synchronously provide a row selection signal and a column selection signal to a memory cell array.
摘要翻译：一种非易失性存储器件和系统，具有可通过用于产生第一命令信号的DRAM协议访问的非易失性存储器件和基于行地址选通信号和列地址选通信号的第二命令信号，并且存储基于n位行地址信号在第一命令信号上，基于第二命令信号的n位列地址信号，并且对n位行地址信号和n位列地址信号进行解码，以同步地提供行选择信号和列选择信号存储单元阵列。

9. 发明申请

US20150179250A1 ACCESS SIGNAL ADJUSTMENT CIRCUITS AND METHODS FOR MEMORY CELLS IN A CROSS-POINT ARRAY 有权
标题翻译：交叉点信息调整电路和存储单元的方法
公开(公告)号：US20150179250A1
公开(公告)日：2015-06-25
申请号：US14624891
申请日：2015-02-18
申请人： Unity Semiconductor Corporation
发明人： Christophe J. Chevallier , Chang Hua Siau
IPC分类号： G11C13/00
CPC分类号： G11C13/0033 , G11C11/21 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0069
摘要： Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, such as memory implemented in third dimensional memory technology formed BEOL directly on top of a FEOL substrate that includes data access circuitry. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements disposed among word lines and subsets of bit lines, and an access signal generator. The access signal generator can be configured to modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. The modified magnitude can be a function of the position of the resistive memory element in the cross-point array.
摘要翻译：本发明的实施例一般涉及半导体和存储器技术，更具体地涉及系统，集成电路和方法，用于产生存取信号以促进存储器元件的按比例排列的存储器操作，诸如在形成的第三维存储器技术中实现的存储器直接位于包含数据访问电路的FEOL基板之上。在至少一些实施例中，非易失性存储器件可以包括具有布置在字线和位线子集之间的电阻性存储器元件的交叉点阵列和存取信号发生器。访问信号发生器可被配置为修改信号的大小以产生用于信号访问与字线和位线子集相关联的电阻性存储器元件的修改幅度。修改的幅度可以是交叉点阵列中的电阻性存储元件的位置的函数。

10. 发明授权

US09025358B2 Semiconductor memory having both volatile and non-volatile functionality comprising resistive change material and method of operating 有权
标题翻译：具有挥发性和非挥发性功能的半导体存储器包括电阻变化材料和操作方法
公开(公告)号：US09025358B2
公开(公告)日：2015-05-05
申请号：US13652457
申请日：2012-10-15
申请人： Yuniarto Widjaja
发明人： Yuniarto Widjaja
IPC分类号： G11C11/00 , G11C11/21 , G11C11/404 , G11C13/00 , H01L29/78 , H01L45/00 , H01L27/108 , G11C11/4072 , G11C14/00 , H01L27/24
CPC分类号： G11C14/0045 , G11C11/21 , G11C11/404 , G11C11/407 , G11C11/4072 , G11C13/00 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C14/00 , G11C14/0027 , G11C14/0036 , G11C14/009 , G11C2013/0073 , H01L27/10802 , H01L27/1085 , H01L27/10879 , H01L27/2436 , H01L29/7841 , H01L45/00 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147
摘要： A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory including a bipolar resistive change element, and methods of operating.
摘要翻译：一种半导体存储单元，包括具有浮动体的电容器晶体管，其被配置为当向单元施加功率时将数据作为电荷存储在其中;以及非易失性存储器，包括双极性电阻变化元件，以及操作方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式