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1. 发明申请

US20130077384A1 CROSS POINT VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE AND METHOD OF READING THEREBY 有权
标题翻译：交叉点可变电阻非易失性存储器件及其读取方法
公开(公告)号：US20130077384A1
公开(公告)日：2013-03-28
申请号：US13636169
申请日：2012-04-27
申请人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
发明人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
IPC分类号： G11C11/21
CPC分类号： G11C11/21 , G11C8/08 , G11C13/00 , G11C13/0007 , G11C13/0023 , G11C13/0028 , G11C13/004 , G11C2213/15 , G11C2213/71
摘要： A cross point variable resistance nonvolatile memory device including: a cross point memory cell array having memory cells each of which is placed at a different one of cross points of bit lines and word lines; a word line decoder circuit that selects at least one of the memory cells from the memory cell array; a read circuit that reads data from the selected memory cell; an unselected word line current source that supplies a first constant current; and a control circuit that controls the reading of the data from the selected memory cell, wherein the control circuit controls the word line decoder circuit, the read circuit, and the unselected word line current source so that when the read circuit reads data, the first constant current is supplied to an unselected word line.
摘要翻译：一种交叉点可变电阻非易失性存储器件，包括：具有存储单元的交叉点存储单元阵列，每个存储单元位于位线和字线的交叉点的不同位置; 字线解码器电路，从存储单元阵列中选择至少一个存储单元; 从所选择的存储单元读取数据的读取电路; 提供第一恒定电流的未选字线电流源; 以及控制电路，其控制来自所选择的存储单元的数据的读取，其中所述控制电路控制所述字线解码器电路，所述读取电路和所述未选字线电流源，使得当所述读取电路读取数据时，所述第一恒定电流被提供给未选择的字线。

2. 发明授权

US08982603B2 Cross point variable resistance nonvolatile memory device and method of reading thereby 有权
标题翻译：交叉点可变电阻非易失性存储器件及其读取方法
公开(公告)号：US08982603B2
公开(公告)日：2015-03-17
申请号：US13636169
申请日：2012-04-27
申请人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
发明人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
IPC分类号： G11C11/00 , G11C11/21 , G11C13/00
CPC分类号： G11C11/21 , G11C8/08 , G11C13/00 , G11C13/0007 , G11C13/0023 , G11C13/0028 , G11C13/004 , G11C2213/15 , G11C2213/71
摘要： A cross point variable resistance nonvolatile memory device including: a cross point memory cell array having memory cells each of which is placed at a different one of cross points of bit lines and word lines; a word line decoder circuit that selects at least one of the memory cells from the memory cell array; a read circuit that reads data from the selected memory cell; an unselected word line current source that supplies a first constant current; and a control circuit that controls the reading of the data from the selected memory cell, wherein the control circuit controls the word line decoder circuit, the read circuit, and the unselected word line current source so that when the read circuit reads data, the first constant current is supplied to an unselected word line.
摘要翻译：一种交叉点可变电阻非易失性存储器件，包括：具有存储单元的交叉点存储单元阵列，每个存储单元位于位线和字线的交叉点的不同位置; 字线解码器电路，从存储单元阵列中选择至少一个存储单元; 从所选择的存储单元读取数据的读取电路; 提供第一恒定电流的未选字线电流源; 以及控制电路，其控制来自所选择的存储单元的数据的读取，其中所述控制电路控制所述字线解码器电路，所述读取电路和所述未选字线电流源，使得当所述读取电路读取数据时，所述第一恒定电流被提供给未选择的字线。

3. 发明授权

US08942050B2 Method of inspecting variable resistance nonvolatile memory device and variable resistance nonvolatile memory device 有权
标题翻译：检查可变电阻非易失性存储器件和可变电阻非易失性存储器件的方法
公开(公告)号：US08942050B2
公开(公告)日：2015-01-27
申请号：US13637428
申请日：2011-09-07
申请人： Hiroshi Tomotani , Kazuhiko Shimakawa , Ryotaro Azuma , Yoshikazu Katoh , Yuichiro Ikeda
发明人： Hiroshi Tomotani , Kazuhiko Shimakawa , Ryotaro Azuma , Yoshikazu Katoh , Yuichiro Ikeda
IPC分类号： G11C7/06 , G11C13/00 , G11C29/50
CPC分类号： G11C13/0007 , G11C13/00 , G11C13/003 , G11C29/50008 , G11C2213/15
摘要： A method of inspecting a variable resistance nonvolatile memory device detecting a faulty memory cell of a memory cell array employing a current steering element, and a variable resistance nonvolatile memory device are provided. The method of inspecting a variable resistance nonvolatile memory device having a memory cell array, a memory cell selection circuit, and a read circuit includes: determining that a current steering element has a short-circuit fault when a variable resistance element is in a low resistance state and a current higher than or equal to a predetermined current passes through the current steering element, when the resistance state of the memory cell is read using a second voltage; and determining whether the variable resistance element is in the low or high resistance state, when the resistance state of the memory cell is read using a first voltage.
摘要翻译：提供了检测使用电流导向元件的存储单元阵列的故障存储单元的可变电阻非易失性存储器件和可变电阻非易失性存储器件的方法。检查具有存储单元阵列的可变电阻非易失性存储器件，存储单元选择电路和读取电路的方法包括：当可变电阻元件处于低电阻时，确定当前的导向元件具有短路故障当使用第二电压读取存储单元的电阻状态时，高于或等于预定电流的电流通过电流导向元件; 以及当使用第一电压读取存储单元的电阻状态时，确定可变电阻元件是处于低电阻还是高电阻状态。

4. 发明申请

US20130223133A1 CROSS POINT VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE AND METHOD OF WRITING THEREBY 有权
标题翻译：交叉点可变电阻非易失性存储器件及其写入方法
公开(公告)号：US20130223133A1
公开(公告)日：2013-08-29
申请号：US13883785
申请日：2012-09-06
申请人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
发明人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C11/5685 , G11C13/0007 , G11C13/0023 , G11C2013/0073 , G11C2013/0088
摘要： A cross point variable nonvolatile memory device includes a memory cell array including: first memory cells (e.g., part of a memory cell array) having a common word line; and second memory cells (e.g., another part of the memory cell array or a compensation cell unit). When a predetermined memory cell among the first memory cells is written to by changing the predetermined memory cell to a first resistance state, a word line write circuit supplies a first voltage or a first current to a selected word line, a first bit line write circuit supplies a third voltage or a third current to one bit line of the first memory cells, and a second bit line write circuit supplies the third voltage or the third current to A bit line or lines of the second memory cells.
摘要翻译：交叉点可变非易失性存储器件包括存储单元阵列，其包括：具有公共字线的第一存储器单元（例如，存储单元阵列的一部分）; 和第二存储单元（例如，存储单元阵列的另一部分或补偿单元单元）。当通过将预定存储单元改变为第一电阻状态来将第一存储单元中的预定存储单元写入时，字线写入电路向所选字线提供第一电压或第一电流，第一位线写入电路向第一存储器单元的一个位线提供第三电压或第三电流，并且第二位线写入电路将第三电压或第三电流提供给第二存储器单元的A位线或第二行。

5. 发明授权

US09087581B2 Cross point variable resistance nonvolatile memory device and method of writing thereby 有权
标题翻译：交叉点可变电阻非易失性存储器件及其写入方法
公开(公告)号：US09087581B2
公开(公告)日：2015-07-21
申请号：US13883785
申请日：2012-09-06
申请人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
发明人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
IPC分类号： G11C11/00 , G11C13/00 , G11C11/56
CPC分类号： G11C13/0069 , G11C11/5685 , G11C13/0007 , G11C13/0023 , G11C2013/0073 , G11C2013/0088
摘要： A cross point variable nonvolatile memory device includes a memory cell array including: first memory cells (e.g., part of a memory cell array) having a common word line; and second memory cells (e.g., another part of the memory cell array or a compensation cell unit). When a predetermined memory cell among the first memory cells is written to by changing the predetermined memory cell to a first resistance state, a word line write circuit supplies a first voltage or a first current to a selected word line, a first bit line write circuit supplies a third voltage or a third current to one bit line of the first memory cells, and a second bit line write circuit supplies the third voltage or the third current to A bit line or lines of the second memory cells.
摘要翻译：交叉点可变非易失性存储器件包括存储单元阵列，其包括：具有公共字线的第一存储器单元（例如，存储单元阵列的一部分）; 和第二存储单元（例如，存储单元阵列的另一部分或补偿单元单元）。当通过将预定存储单元改变为第一电阻状态来将第一存储单元中的预定存储单元写入时，字线写入电路向所选字线提供第一电压或第一电流，第一位线写入电路向第一存储器单元的一个位线提供第三电压或第三电流，并且第二位线写入电路将第三电压或第三电流提供给第二存储器单元的A位线或第二行。

6. 发明申请

US20130021838A1 METHOD OF INSPECTING VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE AND VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE 有权
标题翻译：检测可变电阻非易失性存储器件和可变电阻非易失性存储器件的方法
公开(公告)号：US20130021838A1
公开(公告)日：2013-01-24
申请号：US13637428
申请日：2011-09-07
申请人： Hiroshi Tomotani , Kazuhiko Shimakawa , Ryotaro Azuma , Yoshikazu Katoh , Yuichiro Ikeda
发明人： Hiroshi Tomotani , Kazuhiko Shimakawa , Ryotaro Azuma , Yoshikazu Katoh , Yuichiro Ikeda
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/00 , G11C13/003 , G11C29/50008 , G11C2213/15
摘要： A method of inspecting a variable resistance nonvolatile memory device detecting a faulty memory cell of a memory cell array employing a current steering element, and a variable resistance nonvolatile memory device are provided. The method of inspecting a variable resistance nonvolatile memory device having a memory cell array, a memory cell selection circuit, and a read circuit includes: determining that a current steering element has a short-circuit fault when a variable resistance element is in a low resistance state and a current higher than or equal to a predetermined current passes through the current steering element, when the resistance state of the memory cell is read using a second voltage; and determining whether the variable resistance element is in the low or high resistance state, when the resistance state of the memory cell is read using a first voltage.
摘要翻译：提供了检测使用电流导向元件的存储单元阵列的故障存储单元的可变电阻非易失性存储器件和可变电阻非易失性存储器件的方法。检查具有存储单元阵列的可变电阻非易失性存储器件，存储单元选择电路和读取电路的方法包括：当可变电阻元件处于低电阻时，确定当前的导向元件具有短路故障当使用第二电压读取存储单元的电阻状态时，高于或等于预定电流的电流通过电流导向元件; 以及当使用第一电压读取存储单元的电阻状态时，确定可变电阻元件是处于低电阻还是高电阻状态。

7. 发明授权

US08687409B2 Variable resistance nonvolatile memory device 有权
标题翻译：可变电阻非易失性存储器件
公开(公告)号：US08687409B2
公开(公告)日：2014-04-01
申请号：US13639120
申请日：2012-05-30
申请人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma , Ken Kawai
发明人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma , Ken Kawai
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C2013/0083 , G11C2213/32 , G11C2213/72
摘要： A variable resistance nonvolatile memory device including memory cells provided at cross-points of first signal lines and second signal lines, each memory cell including a variable resistance element and a current steering element connected to the variable resistance element in series, the variable resistance nonvolatile memory device including a write circuit, a row selection circuit, and a column selection circuit, wherein the write circuit: sequentially selects blocks in an order starting from a block farthest from at least one of the row selection circuit and the column selection circuit and finishing with a block closest to the at least one of the row selection circuit and the column selection circuit; and performs, for each of the selected blocks, initial breakdown on each memory cell included in the selected block.
摘要翻译：一种可变电阻非易失性存储器件，包括设置在第一信号线和第二信号线的交叉点处的存储单元，每个存储单元包括可变电阻元件和连接到可变电阻元件串联的电流操舵元件，可变电阻非易失性存储器包括写入电路，行选择电路和列选择电路的装置，其中写入电路：从与行选择电路和列选择电路中的至少一个最远的块开始的顺序顺序地选择块，并且以最靠近行选择电路和列选择电路中的至少一个的块; 并且对于每个所选择的块，对包括在所选择的块中的每个存储器单元执行初始故障。

8. 发明授权

US08305795B2 Nonvolatile variable resistance memory element writing method, and nonvolatile variable resistance memory device 有权
标题翻译：非易失性可变电阻存储元件写入方法和非易失性可变电阻存储器件
公开(公告)号：US08305795B2
公开(公告)日：2012-11-06
申请号：US12999019
申请日：2010-04-27
申请人： Ryotaro Azuma , Kazuhiko Shimakawa , Shunsaku Muraoka , Ken Kawai
发明人： Ryotaro Azuma , Kazuhiko Shimakawa , Shunsaku Muraoka , Ken Kawai
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0054 , G11C2013/0073 , G11C2013/0083 , G11C2013/009 , G11C2013/0092 , G11C2213/15 , G11C2213/32 , G11C2213/56 , G11C2213/79
摘要： To provide a variable resistance element writing method that, even when a variable resistance element has a possibility of becoming a half LR state, can ensure a maximum resistance change window by correcting the variable resistance element to a normal low resistance state. In a method of writing data to a variable resistance element (10a) that reversibly changes between a high resistance state and a low resistance state according to a polarity of an applied voltage, as a voltage applied to an upper electrode (11) with respect to a lower electrode (14t): a positive voltage is applied in a high resistance writing step (405) to set the variable resistance element (10a) to a high resistance state (401); a negative voltage is applied in a low resistance writing step (406, 408) to set the variable resistance element (10a) to a low resistance state (403, 402); and a positive voltage is applied in a low resistance stabilization writing step (404) after the negative voltage is applied in the low resistance writing step (408), thereby setting the variable resistance element (10a) through the low resistance state to the high resistance state (401).
摘要翻译：为了提供可变电阻元件写入方法，即使当可变电阻元件具有成为半LR状态的可能性时，通过将可变电阻元件校正为正常的低电阻状态来确保最大电阻变化窗口。在根据施加电压的极性将数据写入到可变电阻元件（10a）的方法中，可变电阻元件（10a）根据施加电压的极性在高电阻状态和低电阻状态之间可逆地变化，作为施加到上电极（11）的电压相对于下电极（14t）：在高电阻写入步骤（405）中施加正电压以将可变电阻元件（10a）设置为高电阻状态（401）; 在低电阻写入步骤（406,408）中施加负电压以将可变电阻元件（10a）设置为低电阻状态（403,402）; 并且在低电阻写入步骤（408）中施加负电压之后，在低电阻稳定写入步骤（404）中施加正电压，从而将可变电阻元件（10a）设置为低电阻状态为高电阻州（401）。

9. 发明申请

US20110122680A1 VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE 有权
标题翻译：可变电阻非易失性存储器件
公开(公告)号：US20110122680A1
公开(公告)日：2011-05-26
申请号：US13054312
申请日：2010-04-14
申请人： Yuuichirou Ikeda , Kazuhiko Shimakawa , Yoshihiko Kanzawa , Shunsaku Muraoka , Ryotaro Azuma
发明人： Yuuichirou Ikeda , Kazuhiko Shimakawa , Yoshihiko Kanzawa , Shunsaku Muraoka , Ryotaro Azuma
IPC分类号： G11C11/21
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/12 , G11C2213/15 , G11C2213/34 , G11C2213/72 , H01L27/24
摘要： A nonvolatile resistance variable memory device (100) includes memory cells (M11, M12, . . . ) in each of which a variable resistance element (R11, R12, . . . ) including a variable resistance layer placed between and in contact with a first electrode and a second electrode, and a current steering element (D11, D12, . . . ) including a current steering layer placed between and in contact with a third electrode and a fourth electrode, are connected in series, and the device is driven by a first LR drive circuit (105a1) via a current limit circuit (105b) to decrease resistance of the variable resistance element while the device is driven by a second HR drive circuit (105a2) to increase resistance of the variable resistance element, thus using the current limit circuit (105b) to make a current for decreasing resistance of the variable resistance element lower than a current for increasing resistance of the variable resistance element.
摘要翻译：一种非易失性电阻可变存储器件（100）包括存储单元（M11，M12 ...），每个存储单元包括可变电阻元件（R11，R12 ...），该可变电阻元件（R11，R12 ...）第一电极和第二电极，以及包括放置在第三电极和第四电极之间并与第三电极和第四电极接触的电流导向层的电流导向元件（D11，D12 ...）串联连接，并且驱动该装置通过第一LR驱动电路（105a1）经由限流电路（105b），以在器件被第二HR驱动电路（105a2）驱动时降低可变电阻元件的电阻，以增加可变电阻元件的电阻，从而使用电流限制电路（105b），用于使可变电阻元件的电阻降低的电流低于用于增加可变电阻元件的电阻的电流。

10. 发明申请

US20130148406A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND READ METHOD FOR THE SAME 有权
标题翻译：非易失性半导体存储器件及其读取方法
公开(公告)号：US20130148406A1
公开(公告)日：2013-06-13
申请号：US13700329
申请日：2012-07-11
申请人： Kazuhiko Shimakawa , Kiyotaka Tsuji , Ryotaro Azuma
发明人： Kazuhiko Shimakawa , Kiyotaka Tsuji , Ryotaro Azuma
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C7/14 , G11C11/1673 , G11C13/0004 , G11C2013/0054 , G11C2213/71 , G11C2213/72 , G11C2213/73 , G11C2213/77
摘要： A cross point nonvolatile memory device capable of suppressing sneak-current-caused reduction in sensitivity of detection of a resistance value of a memory element is provided. The device includes perpendicular bit and word lines; a cross-point cell array including memory cells each having a resistance value reversibly changing between at least two resistance states according to electrical signals, arranged on cross-points of the word and bit lines; an offset detection cell array including an offset detection cell having a resistance higher than that of the memory cell in a high resistance state, the word lines being shared by the offset detection cell array; a read circuit (a sense amplifier) that determines a resistance state of a selected memory cell based on a current through the selected bit line; and a current source which supplies current to the offset detection cell array in a read operation period.
摘要翻译：提供一种能够抑制潜流引起的对存储元件的电阻值的检测灵敏度的降低的交叉点非易失性存储装置。该设备包括垂直位和字线; 交叉点单元阵列，其包括存储单元，每个存储单元具有电阻值，该电阻值根据电信号在至少两个电阻状态之间可逆地改变;布置在字和位线的交叉点上; 偏移检测单元阵列，包括在高电阻状态下具有高于存储单元的电阻的偏移检测单元，所述字线由偏移检测单元阵列共享; 读取电路（读出放大器），其基于通过所选位线的电流确定所选存储单元的电阻状态; 以及在读取操作时段中向偏移检测单元阵列提供电流的电流源。

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