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1. 发明授权

US08687409B2 Variable resistance nonvolatile memory device 有权
标题翻译：可变电阻非易失性存储器件
公开(公告)号：US08687409B2
公开(公告)日：2014-04-01
申请号：US13639120
申请日：2012-05-30
申请人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma , Ken Kawai
发明人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma , Ken Kawai
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C2013/0083 , G11C2213/32 , G11C2213/72
摘要： A variable resistance nonvolatile memory device including memory cells provided at cross-points of first signal lines and second signal lines, each memory cell including a variable resistance element and a current steering element connected to the variable resistance element in series, the variable resistance nonvolatile memory device including a write circuit, a row selection circuit, and a column selection circuit, wherein the write circuit: sequentially selects blocks in an order starting from a block farthest from at least one of the row selection circuit and the column selection circuit and finishing with a block closest to the at least one of the row selection circuit and the column selection circuit; and performs, for each of the selected blocks, initial breakdown on each memory cell included in the selected block.
摘要翻译：一种可变电阻非易失性存储器件，包括设置在第一信号线和第二信号线的交叉点处的存储单元，每个存储单元包括可变电阻元件和连接到可变电阻元件串联的电流操舵元件，可变电阻非易失性存储器包括写入电路，行选择电路和列选择电路的装置，其中写入电路：从与行选择电路和列选择电路中的至少一个最远的块开始的顺序顺序地选择块，并且以最靠近行选择电路和列选择电路中的至少一个的块; 并且对于每个所选择的块，对包括在所选择的块中的每个存储器单元执行初始故障。

2. 发明申请

US20130114327A1 VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE 有权
标题翻译：可变电阻非易失性存储器件
公开(公告)号：US20130114327A1
公开(公告)日：2013-05-09
申请号：US13639120
申请日：2012-05-30
申请人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma , Ken Kawai
发明人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma , Ken Kawai
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C2013/0083 , G11C2213/32 , G11C2213/72
摘要： A variable resistance nonvolatile memory device including memory cells provided at cross-points of first signal lines and second signal lines, each memory cell including a variable resistance element and a current steering element connected to the variable resistance element in series, the variable resistance nonvolatile memory device including a write circuit, a row selection circuit, and a column selection circuit, wherein the write circuit: sequentially selects blocks in an order starting from a block farthest from at least one of the row selection circuit and the column selection circuit and finishing with a block closest to the at least one of the row selection circuit and the column selection circuit; and performs, for each of the selected blocks, initial breakdown on each memory cell included in the selected block.
摘要翻译：一种可变电阻非易失性存储器件，包括设置在第一信号线和第二信号线的交叉点处的存储单元，每个存储单元包括可变电阻元件和连接到可变电阻元件串联的电流操舵元件，可变电阻非易失性存储器包括写入电路，行选择电路和列选择电路的装置，其中写入电路：从与行选择电路和列选择电路中的至少一个最远的块开始的顺序顺序地选择块，并且用最靠近行选择电路和列选择电路中的至少一个的块; 并且对于每个所选择的块，对包括在所选择的块中的每个存储器单元执行初始故障。

3. 发明授权

US08942050B2 Method of inspecting variable resistance nonvolatile memory device and variable resistance nonvolatile memory device 有权
标题翻译：检查可变电阻非易失性存储器件和可变电阻非易失性存储器件的方法
公开(公告)号：US08942050B2
公开(公告)日：2015-01-27
申请号：US13637428
申请日：2011-09-07
申请人： Hiroshi Tomotani , Kazuhiko Shimakawa , Ryotaro Azuma , Yoshikazu Katoh , Yuichiro Ikeda
发明人： Hiroshi Tomotani , Kazuhiko Shimakawa , Ryotaro Azuma , Yoshikazu Katoh , Yuichiro Ikeda
IPC分类号： G11C7/06 , G11C13/00 , G11C29/50
CPC分类号： G11C13/0007 , G11C13/00 , G11C13/003 , G11C29/50008 , G11C2213/15
摘要： A method of inspecting a variable resistance nonvolatile memory device detecting a faulty memory cell of a memory cell array employing a current steering element, and a variable resistance nonvolatile memory device are provided. The method of inspecting a variable resistance nonvolatile memory device having a memory cell array, a memory cell selection circuit, and a read circuit includes: determining that a current steering element has a short-circuit fault when a variable resistance element is in a low resistance state and a current higher than or equal to a predetermined current passes through the current steering element, when the resistance state of the memory cell is read using a second voltage; and determining whether the variable resistance element is in the low or high resistance state, when the resistance state of the memory cell is read using a first voltage.
摘要翻译：提供了检测使用电流导向元件的存储单元阵列的故障存储单元的可变电阻非易失性存储器件和可变电阻非易失性存储器件的方法。检查具有存储单元阵列的可变电阻非易失性存储器件，存储单元选择电路和读取电路的方法包括：当可变电阻元件处于低电阻时，确定当前的导向元件具有短路故障当使用第二电压读取存储单元的电阻状态时，高于或等于预定电流的电流通过电流导向元件; 以及当使用第一电压读取存储单元的电阻状态时，确定可变电阻元件是处于低电阻还是高电阻状态。

4. 发明授权

US08467228B2 Variable resistance nonvolatile memory device 有权
标题翻译：可变电阻非易失性存储器件
公开(公告)号：US08467228B2
公开(公告)日：2013-06-18
申请号：US13496895
申请日：2011-08-10
申请人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma
发明人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/004 , G11C2213/71 , G11C2213/72 , H01L27/0688 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： Each of basic array planes has a first via group that interconnects only even-layer bit lines in the basic array plane, and a second via group that interconnects only odd-layer bit lines in the basic array plane, the first via group in a first basic array plane and the second via group in a second basic array plane adjacent to the first basic array in a Y direction are adjacent to each other in the Y direction, and the second via group in the first basic array plane and the first via group in the second basic array plane are adjacent to each other in the Y direction, and the second via group in the second basic array plane is disconnected from a second global line when connecting the first via group in the first basic array plane to a first global line.
摘要翻译：每个基本阵列平面具有仅在基本阵列平面中互连偶数位线的第一通孔组和仅在基本阵列平面中互连奇数位线的第二通孔组，第一通孔组在第一通孔组在Y方向上与第一基本阵列相邻的第二基本阵列平面中的基本阵列平面和第二通孔组在Y方向上彼此相邻，并且第一基本阵列平面中的第二通孔组和第一通孔组在第二基本阵列平面中在Y方向上彼此相邻，并且当将第一基本阵列平面中的第一通孔组连接到第一全局线阵列时，第二基本阵列平面中的第二通孔组与第二全局线断开连接线。

5. 发明授权

US08305795B2 Nonvolatile variable resistance memory element writing method, and nonvolatile variable resistance memory device 有权
标题翻译：非易失性可变电阻存储元件写入方法和非易失性可变电阻存储器件
公开(公告)号：US08305795B2
公开(公告)日：2012-11-06
申请号：US12999019
申请日：2010-04-27
申请人： Ryotaro Azuma , Kazuhiko Shimakawa , Shunsaku Muraoka , Ken Kawai
发明人： Ryotaro Azuma , Kazuhiko Shimakawa , Shunsaku Muraoka , Ken Kawai
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0054 , G11C2013/0073 , G11C2013/0083 , G11C2013/009 , G11C2013/0092 , G11C2213/15 , G11C2213/32 , G11C2213/56 , G11C2213/79
摘要： To provide a variable resistance element writing method that, even when a variable resistance element has a possibility of becoming a half LR state, can ensure a maximum resistance change window by correcting the variable resistance element to a normal low resistance state. In a method of writing data to a variable resistance element (10a) that reversibly changes between a high resistance state and a low resistance state according to a polarity of an applied voltage, as a voltage applied to an upper electrode (11) with respect to a lower electrode (14t): a positive voltage is applied in a high resistance writing step (405) to set the variable resistance element (10a) to a high resistance state (401); a negative voltage is applied in a low resistance writing step (406, 408) to set the variable resistance element (10a) to a low resistance state (403, 402); and a positive voltage is applied in a low resistance stabilization writing step (404) after the negative voltage is applied in the low resistance writing step (408), thereby setting the variable resistance element (10a) through the low resistance state to the high resistance state (401).
摘要翻译：为了提供可变电阻元件写入方法，即使当可变电阻元件具有成为半LR状态的可能性时，通过将可变电阻元件校正为正常的低电阻状态来确保最大电阻变化窗口。在根据施加电压的极性将数据写入到可变电阻元件（10a）的方法中，可变电阻元件（10a）根据施加电压的极性在高电阻状态和低电阻状态之间可逆地变化，作为施加到上电极（11）的电压相对于下电极（14t）：在高电阻写入步骤（405）中施加正电压以将可变电阻元件（10a）设置为高电阻状态（401）; 在低电阻写入步骤（406,408）中施加负电压以将可变电阻元件（10a）设置为低电阻状态（403,402）; 并且在低电阻写入步骤（408）中施加负电压之后，在低电阻稳定写入步骤（404）中施加正电压，从而将可变电阻元件（10a）设置为低电阻状态为高电阻州（401）。

6. 发明授权

US08325508B2 Writing method for variable resistance nonvolatile memory element, and variable resistance nonvolatile memory device 有权
标题翻译：可变电阻非易失性存储元件和可变电阻非易失性存储器件的写入方法
公开(公告)号：US08325508B2
公开(公告)日：2012-12-04
申请号：US13001905
申请日：2010-06-08
申请人： Ken Kawai , Kazuhiko Shimakawa , Shunsaku Muraoka , Ryotaro Azuma
发明人： Ken Kawai , Kazuhiko Shimakawa , Shunsaku Muraoka , Ryotaro Azuma
IPC分类号： G11C11/00
CPC分类号： G11C11/5685 , G11C13/0007 , G11C13/0038 , G11C13/0064 , G11C13/0069 , G11C2013/0071 , G11C2013/0073 , G11C2013/0083 , G11C2213/56 , G11C2213/79
摘要： A writing method optimum for a variable resistance element which can maximize an operation window of the variable resistance element is provided. The writing method is performed for a variable resistance element that reversibly changes between a high resistance state and a low resistance state depending on a polarity of an applied voltage pulse. The writing method includes a preparation step (S50) and a writing step (S51, S51a, S51b). At the preparation step (S50), resistance values of the variable resistance element are measured by applying voltage pulses of voltages that are gradually increased to the variable resistance element, thereby determining the first voltage V1 for starting high resistance writing and the second voltage V2 having a maximum resistance value. At the HR writing step (S51a), a voltage pulse having a voltage Vp that is equal to or higher than the first voltage V1 and equal to or lower than the second voltage V2 is applied to the variable resistance element, thereby changing the variable resistance element from the low resistance state (S52) to the high resistance state (S53).
摘要翻译：提供了一种最佳可变电阻元件的写入方法，其可以使可变电阻元件的操作窗口最大化。对于根据施加的电压脉冲的极性在高电阻状态和低电阻状态之间可逆地变化的可变电阻元件执行写入方法。写入方法包括准备步骤（S50）和写入步骤（S51，S51a，S51b）。在准备步骤（S50）中，通过向可变电阻元件施加逐渐增加的电压的电压脉冲来测量可变电阻元件的电阻值，从而确定用于开始高电阻写入的第一电压V1和具有最大电阻值。在HR写入步骤（S51a）中，将具有等于或高于第一电压V1并且等于或低于第二电压V2的电压Vp的电压脉冲施加到可变电阻元件，从而改变可变电阻元件从低电阻状态（S52）到高电阻状态（S53）。

7. 发明授权

US08467229B2 Variable resistance nonvolatile memory device 有权
标题翻译：可变电阻非易失性存储器件
公开(公告)号：US08467229B2
公开(公告)日：2013-06-18
申请号：US13511787
申请日：2011-11-24
申请人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma
发明人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0026 , G11C13/004 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： In a nonvolatile memory device, basic array planes (0 to 3) have respective first via groups (121 to 124) that interconnect only even-layer bit lines in the basic array planes, and respective second via groups (131 to 134) that interconnect only odd-layer bit lines in the basic array planes, the first via group in a first basic array plane and the second via group in a second basic array plane adjacent to the first basic array plane in a Y direction are adjacent to each other in the Y direction, and the first via group in the second basic array plane is connected to an unselected-bit-line dedicated global bit line (GBL_NS) having a fixed potential when the first via group in the first basic array plane is connected to a first global bit line related to the first basic array plane.
摘要翻译：在非易失性存储器件中，基本阵列平面（0至3）具有各自的第一通孔组（121至124），其仅互连基本阵列平面中的偶数位线，以及相互连接的相应的第二通孔组（131至134）在基本阵列平面中只有奇数位线，在第一基本阵列平面中的第一通孔组和与Y方向上与第一基本阵列平面相邻的第二基本阵列平面中的第二通孔组彼此相邻， Y方向和第二基本阵列平面中的第一通孔组连接到具有固定电位的未选择位线专用全局位线（GBL_NS），当第一基本阵列平面中的第一通孔组连接到与第一个基本阵列平面相关的第一个全局位线。

8. 发明申请

US20130021838A1 METHOD OF INSPECTING VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE AND VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE 有权
标题翻译：检测可变电阻非易失性存储器件和可变电阻非易失性存储器件的方法
公开(公告)号：US20130021838A1
公开(公告)日：2013-01-24
申请号：US13637428
申请日：2011-09-07
申请人： Hiroshi Tomotani , Kazuhiko Shimakawa , Ryotaro Azuma , Yoshikazu Katoh , Yuichiro Ikeda
发明人： Hiroshi Tomotani , Kazuhiko Shimakawa , Ryotaro Azuma , Yoshikazu Katoh , Yuichiro Ikeda
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/00 , G11C13/003 , G11C29/50008 , G11C2213/15
摘要： A method of inspecting a variable resistance nonvolatile memory device detecting a faulty memory cell of a memory cell array employing a current steering element, and a variable resistance nonvolatile memory device are provided. The method of inspecting a variable resistance nonvolatile memory device having a memory cell array, a memory cell selection circuit, and a read circuit includes: determining that a current steering element has a short-circuit fault when a variable resistance element is in a low resistance state and a current higher than or equal to a predetermined current passes through the current steering element, when the resistance state of the memory cell is read using a second voltage; and determining whether the variable resistance element is in the low or high resistance state, when the resistance state of the memory cell is read using a first voltage.
摘要翻译：提供了检测使用电流导向元件的存储单元阵列的故障存储单元的可变电阻非易失性存储器件和可变电阻非易失性存储器件的方法。检查具有存储单元阵列的可变电阻非易失性存储器件，存储单元选择电路和读取电路的方法包括：当可变电阻元件处于低电阻时，确定当前的导向元件具有短路故障当使用第二电压读取存储单元的电阻状态时，高于或等于预定电流的电流通过电流导向元件; 以及当使用第一电压读取存储单元的电阻状态时，确定可变电阻元件是处于低电阻还是高电阻状态。

9. 发明申请

US20120236628A1 VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE 有权
标题翻译：可变电阻非易失性存储器件
公开(公告)号：US20120236628A1
公开(公告)日：2012-09-20
申请号：US13511787
申请日：2011-11-24
申请人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma
发明人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0026 , G11C13/004 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： In a nonvolatile memory device, basic array planes (0 to 3) have respective first via groups (121 to 124) that interconnect only even-layer bit lines in the basic array planes, and respective second via groups (131 to 134) that interconnect only odd-layer bit lines in the basic array planes, the first via group in a first basic array plane and the second via group in a second basic array plane adjacent to the first basic array plane in a Y direction are adjacent to each other in the Y direction, and the first via group in the second basic array plane is connected to an unselected-bit-line dedicated global bit line (GBL_NS) having a fixed potential when the first via group in the first basic array plane is connected to a first global bit line related to the first basic array plane.
摘要翻译：在非易失性存储器件中，基本阵列平面（0至3）具有各自的第一通孔组（121至124），其仅互连基本阵列平面中的偶数位线，以及相互连接的相应的第二通孔组（131至134）在基本阵列平面中只有奇数位线，在第一基本阵列平面中的第一通孔组和与Y方向上与第一基本阵列平面相邻的第二基本阵列平面中的第二通孔组彼此相邻， Y方向和第二基本阵列平面中的第一通孔组连接到具有固定电位的未选择位线专用全局位线（GBL_NS），当第一基本阵列平面中的第一通孔组连接到与第一个基本阵列平面相关的第一个全局位线。

10. 发明申请

US20120176834A1 VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE 有权
标题翻译：可变电阻非易失性存储器件
公开(公告)号：US20120176834A1
公开(公告)日：2012-07-12
申请号：US13496895
申请日：2011-08-10
申请人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma
发明人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma
IPC分类号： G11C11/21
CPC分类号： H01L27/101 , G11C13/004 , G11C2213/71 , G11C2213/72 , H01L27/0688 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： Each of basic array planes has a first via group that interconnects only even-layer bit lines in the basic array plane, and a second via group that interconnects only odd-layer bit lines in the basic array plane, the first via group in a first basic array plane and the second via group in a second basic array plane adjacent to the first basic array in a Y direction are adjacent to each other in the Y direction, and the second via group in the first basic array plane and the first via group in the second basic array plane are adjacent to each other in the Y direction, and the second via group in the second basic array plane is disconnected from a second global line when connecting the first via group in the first basic array plane to a first global line.
摘要翻译：每个基本阵列平面具有仅在基本阵列平面中互连偶数位线的第一通孔组和仅在基本阵列平面中互连奇数位线的第二通孔组，第一通孔组在第一通孔组在Y方向上与第一基本阵列相邻的第二基本阵列平面中的基本阵列平面和第二通孔组在Y方向上彼此相邻，并且第一基本阵列平面中的第二通孔组和第一通孔组在第二基本阵列平面中在Y方向上彼此相邻，并且当将第一基本阵列平面中的第一通孔组连接到第一全局线阵列时，第二基本阵列平面中的第二通孔组与第二全局线断开连接线。

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