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    • 10. 发明授权
    • Multi-processor system
    • 多处理器系统
    • US07320056B2
    • 2008-01-15
    • US11285184
    • 2005-11-23
    • Takeshi ShimadaTatsuru NakagakiAkihiro Kobayashi
    • Takeshi ShimadaTatsuru NakagakiAkihiro Kobayashi
    • G06F13/16
    • G06F12/0831G06F12/0813G06F13/1663
    • Data transmission for writing data into a shared memory is performed by a high-speed dedicated line provided between each processor and the shared memory. When a processor performs writing to a shared memory space, the processor notifies an update notification bus corresponding to the conventional global bus, to which address the update is to be performed. The other processors which have detected this notification inhibit access to that address and wait for the write data to be sent to the address via the dedicated line. When the data has arrived, the data is written into the corresponding address. Here, the data is also written into the corresponding address, thereby maintaining the cache coherency. Moreover, when transmitting a write address, it is necessary to acquire the bus use right while data transmission is performed by using the dedicated line, which significantly reduces the time required for acquiring the bus use right.
    • 通过设置在每个处理器和共享存储器之间的高速专用线来执行用于将数据写入共享存储器的数据传输。 当处理器对共享存储器空间进行写入时,处理器通知对应于常规全局总线的更新通知总线,该更新将被执行到该地址。 检测到该通知的其他处理器禁止访问该地址,并等待通过专用线将写入数据发送到地址。 数据到达时,数据写入相应的地址。 这里,数据也被写入相应的地址,从而保持高速缓存一致性。 此外,当发送写入地址时,需要通过使用专用线来执行数据传输时获取总线使用权,这大大减少了获取总线使用权所需的时间。