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1. 发明授权

US06753720B2 Internal high voltage generation circuit capable of stably generating internal high voltage and circuit element therefor 失效
标题翻译：能够稳定地产生内部高电压的内部高压发生电路及其电路元件
公开(公告)号：US06753720B2
公开(公告)日：2004-06-22
申请号：US10302849
申请日：2002-11-25
申请人： Takashi Kono , Katsuyoshi Mitsui , Kiyohiro Furutani
发明人： Takashi Kono , Katsuyoshi Mitsui , Kiyohiro Furutani
IPC分类号： G05F110
CPC分类号： G05F1/465 , G11C5/143 , G11C5/145
摘要： In order to stably generate a high voltage of a prescribed level, a Vpp detection circuit which is activated in response to an activation signal for comparing the high voltage with a reference voltage is forcibly brought into an active state for a prescribed period under control of an initial control circuit.
摘要翻译：为了稳定地产生规定电平的高电压，响应用于将高电压与基准电压进行比较的激活信号而被激活的Vpp检测电路在控制下被强制地进入活动状态初始控制电路。

2. 发明授权

US06297624B1 Semiconductor device having an internal voltage generating circuit 失效
标题翻译：具有内部电压产生电路的半导体器件
公开(公告)号：US06297624B1
公开(公告)日：2001-10-02
申请号：US09258159
申请日：1999-02-26
申请人： Katsuyoshi Mitsui , Kiyohiro Furutani , Takashi Kono
发明人： Katsuyoshi Mitsui , Kiyohiro Furutani , Takashi Kono
IPC分类号： G05F316
CPC分类号： G05F1/465
摘要： An internal power supply circuit produces an internal power supply voltage from an external power supply voltage. A voltage level control circuit controls a voltage level and a temperature characteristic of the internal power supply voltage generated by the internal power supply circuit. The internal power supply circuit produces the internal power supply voltage having a negative or zero temperature characteristic in a low temperature region and a positive temperature characteristic in a high temperature region. The voltage level control circuit includes a structure optimizing a capacitance value of a sense power supply line stabilizing capacitance for driving a sense amplifier circuit, a level converting circuit determining the lowest operable region of the external power supply voltage of the internal power supply circuit, or a structure forcedly operating the internal voltage down converter upon power-on. The internal power supply voltage at a desired level is stably produced with a small occupied area and a low current consumption.
摘要翻译：内部电源电路从外部电源电压产生内部电源电压。电压电平控制电路控制由内部电源电路产生的内部电源电压的电压电平和温度特性。内部电源电路在低温区域产生具有负温度或零温度特性的内部电源电压，在高温区域产生正温度特性。电压电平控制电路包括优化用于驱动读出放大器电路的感测电源线稳定电容的电容值的结构，确定内部电源电路的外部电源电压的最低可操作区域的电平转换电路，或一个在上电时强制运行内部降压转换器的结构。以小的占用面积和低的电流消耗稳定地产生期望的内部电源电压。

3. 发明授权

US06717887B1 Semiconductor memory device having configuration for selecting desired delay locked loop clock 有权
标题翻译：具有用于选择期望的延迟锁定环时钟的配置的半导体存储器件
公开(公告)号：US06717887B1
公开(公告)日：2004-04-06
申请号：US10438928
申请日：2003-05-16
申请人： Takashi Kono , Kiyohiro Furutani
发明人： Takashi Kono , Kiyohiro Furutani
IPC分类号： G11C800
CPC分类号： H03L7/0805 , G11C7/22 , G11C7/222 , H03L7/0812
摘要： A frequency divider divides a frequency of a DLL clock CLK_P into two, to generate ZCLK_PD0 and ZCLK_PD1. A delay circuit generates ZCLK_PDD0, ZCLK_PDD1 obtained by delaying ZCLK_PD0, ZCLK_PD1 respectively by Tc (=a backward amount of CLK_P with respect to an external clock+a delay amount of an internal clock with respect to the external clock). A frequency division select instruction circuit generates ZSEL0, ZSEL1 based on an internal clock CLK, and ZCLK_PDD0, PDD1. A ZSEL0 shifter circuit generates ZSEL1_D2 including a clock pulse of ZSEL1. A ZCLK_P #2 select circuit selects a clock pulse of ZCLK_PD0 using ZSEL1_D2.
摘要翻译：分频器将DLL时钟CLK_P的频率分成两个，以产生ZCLK_PD0和ZCLK_PD1。延迟电路通过将ZCLK_PD0，ZCLK_PD1分别延迟Tc（=相对于外部时钟的相对于外部时钟的内部时钟的延迟量的相对于外部时钟的反向量）而获得的ZCLK_PDD0，ZCLK_PDD1）。分频选择指令电路基于内部时钟CLK和ZCLK_PDD0，PDD1生成ZSEL0，ZSEL1。 ZSEL0移位器电路产生包含ZSEL1的时钟脉冲的ZSEL1_D2。 ZCLK_P＃2选择电路使用ZSEL1_D2选择ZCLK_PD0的时钟脉冲。

4. 发明授权

US06201437B1 Internal high voltage generation circuit capable of stably generating internal high voltage and circuit element therefor 失效
标题翻译：能够稳定地产生内部高电压的内部高压发生电路及其电路元件
公开(公告)号：US06201437B1
公开(公告)日：2001-03-13
申请号：US09166171
申请日：1998-10-05
申请人： Takashi Kono , Katsuyoshi Mitsui , Kiyohiro Furutani
发明人： Takashi Kono , Katsuyoshi Mitsui , Kiyohiro Furutani
IPC分类号： G05F110
CPC分类号： G05F1/465 , G11C5/143 , G11C5/145
摘要： In order to stably generate a high voltage of a prescribed level, a Vpp detection circuit which is activated in response to an activation signal for comparing the high voltage with a reference voltage is forcibly brought into an active state for a prescribed period under control of an initial control circuit.
摘要翻译：为了稳定地产生规定电平的高电压，响应用于将高电压与基准电压进行比较的激活信号而被激活的Vpp检测电路在控制下被强制地进入活动状态初始控制电路。

5. 发明授权

US6055199A Test circuit for a semiconductor memory device and method for burn-in test 有权
标题翻译：一种用于半导体存储器件的测试电路和用于老化测试的方法
公开(公告)号：US6055199A
公开(公告)日：2000-04-25
申请号：US176880
申请日：1998-10-21
申请人： Kei Hamade , Kiyohiro Furutani , Takashi Kono , Mikio Asakura
发明人： Kei Hamade , Kiyohiro Furutani , Takashi Kono , Mikio Asakura
IPC分类号： G11C29/50 , G11C7/00
CPC分类号： G11C29/50 , G11C11/401
摘要： A circuit for supplying a stress to memory cells of a semiconductor memory device having the plurality of the memory cells respectively connected to a word line and a bit line comprises a circuit for generating precharge voltage for bit line, a bit line precharging and equalizing circuit which is connected between said circuit for generating precharge voltage for bit line and said memory cells, a pad connected to the bit line precharging and equalizing circuit for applying a desirable voltage to said memory cells through the corresponding bit lines, and a circuit connected to the circuit for generating precharge voltage for bit line for generating a signal for stopping the operation of said circuit for generating precharge voltage for bit line, whereby cell checker patterns can easily be realized in order to screen out possible failures not only in gate oxide films but also in capacitor dielectrics, storage node junctions or the like by applying an arbitrary stress voltage from the outside of the device.
摘要翻译：用于向具有分别连接到字线和位线的多个存储单元的半导体存储器件的存储单元提供应力的电路包括用于产生位线的预充电电压的电路，位线预充电和均衡电路，连接在所述用于产生位线的预充电电压的电路和所述存储单元之间，连接到位线预充电和均衡电路的焊盘，用于通过相应的位线向所述存储器单元施加期望的电压，以及连接到电路的电路用于产生用于产生用于产生用于产生用于产生位线的预充电电压的所述电路的操作的信号的位线的预充电电压，从而可以容易地实现电池检查器图案，以便不仅在栅极氧化膜中屏蔽可能的故障，电容器电介质，存储节点结等，从外部施加任意的应力电压设备侧。

6. 发明授权

US06492863B2 Internal high voltage generation circuit capable of stably generating internal high voltage and circuit element therefor 失效
标题翻译：能够稳定地产生内部高电压的内部高压发生电路及其电路元件
公开(公告)号：US06492863B2
公开(公告)日：2002-12-10
申请号：US09759331
申请日：2001-01-16
申请人： Takashi Kono , Katsuyoshi Mitsui , Kiyohiro Furutani
发明人： Takashi Kono , Katsuyoshi Mitsui , Kiyohiro Furutani
IPC分类号： G05F110
CPC分类号： G05F1/465 , G11C5/143 , G11C5/145
摘要： In order to stably generate a high voltage of a prescribed level, a Vpp detection circuit which is activated in response to an activation signal for comparing the high voltage with a reference voltage is forcibly brought into an active state for a prescribed period under control of an initial control circuit.
摘要翻译：为了稳定地产生规定电平的高电压，响应用于将高电压与基准电压进行比较的激活信号而被激活的Vpp检测电路在控制下被强制地进入活动状态初始控制电路。

7. 发明授权

US06816422B2 Semiconductor memory device having multi-bit testing function 失效
标题翻译：具有多位测试功能的半导体存储器件
公开(公告)号：US06816422B2
公开(公告)日：2004-11-09
申请号：US10291776
申请日：2002-11-12
申请人： Kei Hamade , Takashi Kono , Kiyohiro Furutani
发明人： Kei Hamade , Takashi Kono , Kiyohiro Furutani
IPC分类号： G11C700
CPC分类号： G11C29/40 , G11C29/34 , G11C2029/0405 , G11C2029/2602
摘要： In a multi-bit test, an I/O combiner degenerates data of a plurality of bits read from a memory cell array to first to fourth data bus pairs in parallel and outputs the degenerated data to a fifth data bus. A read amplifier compares a logic level of the degenerated data received from the I/O combiner with a logic level of expected value data. If the logic level of the degenerated data coincides with the logic level of the expected value data, the read amplifier determines that data write and read to and from the plurality of bits have been normally performed. As a result, a semiconductor memory device can detect a word line defect in the multi-bit test.
摘要翻译：在多位测试中，I / O组合器并行地将从存储单元阵列读取的多个位的数据退格为第一至第四数据总线对，并将退化的数据输出到第五数据总线。读取放大器将从I / O组合器接收的退化数据的逻辑电平与期望值数据的逻辑电平进行比较。如果退化数据的逻辑电平与期望值数据的逻辑电平一致，则读取放大器确定对多个位的数据写入和读取已经被正常地执行。结果，半导体存储器件可以检测多位测试中的字线缺陷。

8. 发明授权

US06262931B1 Semiconductor memory device having voltage down convertor reducing current consumption 有权
标题翻译：具有降压转换器的半导体存储器件减少电流消耗
公开(公告)号：US06262931B1
公开(公告)日：2001-07-17
申请号：US09539893
申请日：2000-03-31
申请人： Takashi Kono , Kiyohiro Furutani , Takeshi Hamamoto , Katsuyoshi Mitsui
发明人： Takashi Kono , Kiyohiro Furutani , Takeshi Hamamoto , Katsuyoshi Mitsui
IPC分类号： G11C800
CPC分类号： G11C8/18 , G11C5/147
摘要： A control circuit & mode register outputs a signal responsive to each command to a VDC control circuit. The VDC control circuit outputs a signal PWRUP changing the quantity of a through current Ic of a comparator stored in a VDC in response to the command. The VDC control circuit internally generates a signal of which pulse width corresponds to a prescribed delay time, in response to input of the command. Therefore, activation of each bank may not be monitored but current consumption can be reduced by preferably controlling a power supply current while minimizing the number of delay circuits and wires.
摘要翻译：控制电路和模式寄存器将响应于每个命令的信号输出到VDC控制电路。 VDC控制电路响应于该命令输出改变存储在VDC中的比较器的直流电流Ic的信号PWRUP。 VDC控制电路根据命令的输入内部产生脉冲宽度对应于规定的延迟时间的信号。因此，通过优选地控制电源电流同时最小化延迟电路和电线的数量，可以不监视每个组的激活，而可以减少电流消耗。

9. 发明授权

US06962827B1 Semiconductor device capable of shortening test time and suppressing increase in chip area, and method of manufacturing semiconductor integrated circuit device 失效
标题翻译：能够缩短测试时间并抑制芯片面积增加的半导体器件，以及半导体集成电路器件的制造方法
公开(公告)号：US06962827B1
公开(公告)日：2005-11-08
申请号：US10640322
申请日：2003-08-14
申请人： Katsuya Furue , Shigeru Kikuda , Kiyohiro Furutani , Tetsushi Tanizaki , Shigehiro Kuge , Takashi Kono
发明人： Katsuya Furue , Shigeru Kikuda , Kiyohiro Furutani , Tetsushi Tanizaki , Shigehiro Kuge , Takashi Kono
IPC分类号： G01R31/28 , G01R31/3185 , G11C29/00 , G11C29/12 , G11C29/56 , H01L21/66 , H01L23/544
CPC分类号： H01L22/34 , G11C29/006 , G11C29/12 , G11C2029/0403 , H01L2924/0002 , H01L2924/00
摘要： A plurality of semiconductor integrated circuits and a plurality of TEG circuits are aligned and provided on a substrate. In the TEG circuit, a built-in test circuit is provided in a region which faces a semiconductor integrated circuit across a dicing line region. The built-in test circuit and the semiconductor integrated circuit are connected by an interconnection which is provided on the dicing line region. The interconnection is cut for isolation into chips.
摘要翻译：多个半导体集成电路和多个TEG电路对准并设置在基板上。在TEG电路中，在穿过切割线区域的面向半导体集成电路的区域中提供内置测试电路。内置测试电路和半导体集成电路通过设置在切割线区域上的互连来连接。互连被切割以分离成芯片。

10. 发明授权

US5652730A Semiconductor memory device having hierarchical boosted power-line scheme 失效
标题翻译：具有分层升压电力线方案的半导体存储器件
公开(公告)号：US5652730A
公开(公告)日：1997-07-29
申请号：US648607
申请日：1996-05-15
申请人： Takashi Kono , Kiyohiro Furutani , Mikio Asakura , Hideto Hidaka
发明人： Takashi Kono , Kiyohiro Furutani , Mikio Asakura , Hideto Hidaka
IPC分类号： G11C11/407 , G11C8/12 , G11C11/4074 , G11C11/408 , G11C11/409 , G11C13/00
CPC分类号： G11C11/4085 , G11C11/4074 , G11C8/12
摘要： A DRAM includes an internal boosting circuit, a global power-line, a plurality of blocks, a row decoder, and a POR generating circuit. Each block includes word lines, local power-lines, AND gates, drive transistors, and word line drivers. The AND gate turns a corresponding drive transistor on/off in response to a power on reset signal /POR and a corresponding block select signal. Therefore, all the local boosted power-lines are connected to the global boosted power-line during a power on reset period, whereby all the local boosted power-lines are initially charged up to boosted power supply potential Vpp.
摘要翻译： DRAM包括内部升压电路，全局电源线，多个块，行解码器和POR发生电路。每个块包括字线，本地电源线，与门，驱动晶体管和字线驱动器。 AND门响应于上电复位信号/ POR和相应的块选择信号而使相应的驱动晶体管导通/截止。因此，所有本地升压电源线在上电复位期间连接到全局升压电源线，由此所有本地升压电源线最初都被充电至提升电源电位Vpp。

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