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    • 1. 发明授权
    • Test circuit for a semiconductor memory device and method for burn-in
test
    • 一种用于半导体存储器件的测试电路和用于老化测试的方法
    • US6055199A
    • 2000-04-25
    • US176880
    • 1998-10-21
    • Kei HamadeKiyohiro FurutaniTakashi KonoMikio Asakura
    • Kei HamadeKiyohiro FurutaniTakashi KonoMikio Asakura
    • G11C29/50G11C7/00
    • G11C29/50G11C11/401
    • A circuit for supplying a stress to memory cells of a semiconductor memory device having the plurality of the memory cells respectively connected to a word line and a bit line comprises a circuit for generating precharge voltage for bit line, a bit line precharging and equalizing circuit which is connected between said circuit for generating precharge voltage for bit line and said memory cells, a pad connected to the bit line precharging and equalizing circuit for applying a desirable voltage to said memory cells through the corresponding bit lines, and a circuit connected to the circuit for generating precharge voltage for bit line for generating a signal for stopping the operation of said circuit for generating precharge voltage for bit line, whereby cell checker patterns can easily be realized in order to screen out possible failures not only in gate oxide films but also in capacitor dielectrics, storage node junctions or the like by applying an arbitrary stress voltage from the outside of the device.
    • 用于向具有分别连接到字线和位线的多个存储单元的半导体存储器件的存储单元提供应力的电路包括用于产生位线的预充电电压的电路,位线预充电和均衡电路, 连接在所述用于产生位线的预充电电压的电路和所述存储单元之间,连接到位线预充电和均衡电路的焊盘,用于通过相应的位线向所述存储器单元施加期望的电压,以及连接到电路的电路 用于产生用于产生用于产生用于产生用于产生位线的预充电电压的所述电路的操作的信号的位线的预充电电压,从而可以容易地实现电池检查器图案,以便不仅在栅极氧化膜中屏蔽可能的故障, 电容器电介质,存储节点结等,从外部施加任意的应力电压 设备侧。
    • 4. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US5710737A
    • 1998-01-20
    • US652035
    • 1996-05-23
    • Yuichiro KomiyaKiyohiro FurutaniTsukasa OoishiKei Hamade
    • Yuichiro KomiyaKiyohiro FurutaniTsukasa OoishiKei Hamade
    • G01R31/26G01R31/28G01R31/3185G11C8/00G11C11/401G11C11/404G11C29/00G11C29/06G11C29/18G11C7/00
    • G11C29/18G11C8/00
    • A sense amplifier (2) is connected to an input/output circuit (7), transmitting input/output data therebetween. The input/output circuit (7) is connected to an address scramble circuit (8). Furthermore, the input/output circuit (7) is connected to a data input/output terminal (DIO), externally transmitting data. The address scramble circuit (8) receives input data (INTDQ) from the data input/output terminal (DIO) and converts the input data (INTDQ) into write data (WD) in accordance with the layout of memory cells in a memory array (1) in response to a burn-in mode signal (BIT) outputted from an address key circuit (9) and a row address first signal RAF outputted from a row address buffer (6). Having the above configuration, a semiconductor memory device can be provided, which permits a prescribed stress to be imposed on its internal circuit only by inputting simple data even in a burn-in test. Moreover, a semiconductor memory device can be provided, which allows an external verification as to whether the device itself enters a burn-in mode or not.
    • 读出放大器(2)连接到输入/输出电路(7),在它们之间传输输入/输出数据。 输入/输出电路(7)连接到地址加扰电路(8)。 此外,输入/输出电路(7)连接到数据输入/输出端(DIO),外部发送数据。 地址扰频电路(8)从数据输入/输出端(DIO)接收输入数据(INTDQ),并根据存储器阵列中存储单元的布局将输入数据(INTDQ)转换为写入数据(WD) 1)响应于从地址键电路(9)输出的老化模式信号(BIT)和从行地址缓冲器(6)输出的行地址第一信号RAF。 具有上述结构,可以提供一种半导体存储器件,即使在老化测试中也能通过输入简单的数据来对其内部电路施加规定的应力。 此外,可以提供半导体存储器件,其允许对器件本身是否进入老化模式进行外部验证。
    • 7. 发明授权
    • Semiconductor device having an internal voltage generating circuit
    • 具有内部电压产生电路的半导体器件
    • US06297624B1
    • 2001-10-02
    • US09258159
    • 1999-02-26
    • Katsuyoshi MitsuiKiyohiro FurutaniTakashi Kono
    • Katsuyoshi MitsuiKiyohiro FurutaniTakashi Kono
    • G05F316
    • G05F1/465
    • An internal power supply circuit produces an internal power supply voltage from an external power supply voltage. A voltage level control circuit controls a voltage level and a temperature characteristic of the internal power supply voltage generated by the internal power supply circuit. The internal power supply circuit produces the internal power supply voltage having a negative or zero temperature characteristic in a low temperature region and a positive temperature characteristic in a high temperature region. The voltage level control circuit includes a structure optimizing a capacitance value of a sense power supply line stabilizing capacitance for driving a sense amplifier circuit, a level converting circuit determining the lowest operable region of the external power supply voltage of the internal power supply circuit, or a structure forcedly operating the internal voltage down converter upon power-on. The internal power supply voltage at a desired level is stably produced with a small occupied area and a low current consumption.
    • 内部电源电路从外部电源电压产生内部电源电压。 电压电平控制电路控制由内部电源电路产生的内部电源电压的电压电平和温度特性。 内部电源电路在低温区域产生具有负温度或零温度特性的内部电源电压,在高温区域产生正温度特性。 电压电平控制电路包括优化用于驱动读出放大器电路的感测电源线稳定电容的电容值的结构,确定内部电源电路的外部电源电压的最低可操作区域的电平转换电路,或 一个在上电时强制运行内部降压转换器的结构。 以小的占用面积和低的电流消耗稳定地产生期望的内部电源电压。