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1. 发明授权

US6055199A Test circuit for a semiconductor memory device and method for burn-in test 有权
标题翻译：一种用于半导体存储器件的测试电路和用于老化测试的方法
公开(公告)号：US6055199A
公开(公告)日：2000-04-25
申请号：US176880
申请日：1998-10-21
申请人： Kei Hamade , Kiyohiro Furutani , Takashi Kono , Mikio Asakura
发明人： Kei Hamade , Kiyohiro Furutani , Takashi Kono , Mikio Asakura
IPC分类号： G11C29/50 , G11C7/00
CPC分类号： G11C29/50 , G11C11/401
摘要： A circuit for supplying a stress to memory cells of a semiconductor memory device having the plurality of the memory cells respectively connected to a word line and a bit line comprises a circuit for generating precharge voltage for bit line, a bit line precharging and equalizing circuit which is connected between said circuit for generating precharge voltage for bit line and said memory cells, a pad connected to the bit line precharging and equalizing circuit for applying a desirable voltage to said memory cells through the corresponding bit lines, and a circuit connected to the circuit for generating precharge voltage for bit line for generating a signal for stopping the operation of said circuit for generating precharge voltage for bit line, whereby cell checker patterns can easily be realized in order to screen out possible failures not only in gate oxide films but also in capacitor dielectrics, storage node junctions or the like by applying an arbitrary stress voltage from the outside of the device.
摘要翻译：用于向具有分别连接到字线和位线的多个存储单元的半导体存储器件的存储单元提供应力的电路包括用于产生位线的预充电电压的电路，位线预充电和均衡电路，连接在所述用于产生位线的预充电电压的电路和所述存储单元之间，连接到位线预充电和均衡电路的焊盘，用于通过相应的位线向所述存储器单元施加期望的电压，以及连接到电路的电路用于产生用于产生用于产生用于产生用于产生位线的预充电电压的所述电路的操作的信号的位线的预充电电压，从而可以容易地实现电池检查器图案，以便不仅在栅极氧化膜中屏蔽可能的故障，电容器电介质，存储节点结等，从外部施加任意的应力电压设备侧。

2. 发明授权

US5793686A Semiconductor memory device having data input/output circuit of small occupied area capable of high-speed data input/output 失效
公开(公告)号：US5793686A
公开(公告)日：1998-08-11
申请号：US755930
申请日：1996-11-25
申请人： Kiyohiro Furutani , Tsukasa Ooishi , Mikio Asakura , Hideto Hidaka , Kei Hamade , Yoshito Nakaoka
发明人： Kiyohiro Furutani , Tsukasa Ooishi , Mikio Asakura , Hideto Hidaka , Kei Hamade , Yoshito Nakaoka
IPC分类号： G11C11/41 , G11C7/10 , G11C11/401 , G11C29/00 , G11C29/14 , G11C29/34 , G11C29/38 , G11C7/00
CPC分类号： G11C29/38 , G11C29/34 , G11C7/1051 , G11C7/1078
摘要： Read drivers which are provided in correspondence to simultaneously selected plural bits of memory cells are wired-OR connected to internal read data buses which in turn are provided in correspondence to a plurality of memory cell arrays respectively. A test mode circuit is provided for the internal read data buses for detecting coincidence/incoincidence of logics of signal potentials on these internal read data bus lines. In a test operation, all read drivers are activated to read selected memory cell data on the corresponding internal read data bus lines.

3. 发明授权

US5953261A Semiconductor memory device having data input/output circuit of small occupied area capable of high-speed data input/output 失效
标题翻译：具有能够进行高速数据输入/输出的占用面积小的数据输入/输出电路的半导体存储器件
公开(公告)号：US5953261A
公开(公告)日：1999-09-14
申请号：US76887
申请日：1998-05-13
申请人： Kiyohiro Furutani , Tsukasa Ooishi , Mikio Asakura , Hideto Hidaka , Kei Hamade , Yoshito Nakaoka
发明人： Kiyohiro Furutani , Tsukasa Ooishi , Mikio Asakura , Hideto Hidaka , Kei Hamade , Yoshito Nakaoka
IPC分类号： G11C11/41 , G11C7/10 , G11C11/401 , G11C29/00 , G11C29/14 , G11C29/34 , G11C29/38 , G11C7/00
CPC分类号： G11C29/38 , G11C29/34 , G11C7/1051 , G11C7/1078
摘要： Read drivers which are provided in correspondence to simultaneously selected plural bits of memory cells are wired-OR connected to internal read data buses which in turn are provided in correspondence to a plurality of memory cell arrays respectively. A test mode circuit is provided for the internal read data buses for detecting coincidence/incoincidence of logics of signal potentials on these internal read data bus lines. In a test operation, all read drivers are activated to read selected memory cell data on the corresponding internal read data bus lines.
摘要翻译：与同时选择的多个存储单元相对应地提供的读驱动器被配线或连接到内部读数据总线，内部读数据总线又分别对应于多个存储单元阵列提供。为内部读取数据总线提供测试模式电路，用于检测这些内部读取数据总线上信号电位逻辑的一致/不一致。在测试操作中，所有读取驱动器都被激活以读取相应的内部读取数据总线上的选定存储单元数据。

4. 发明授权

US5652730A Semiconductor memory device having hierarchical boosted power-line scheme 失效
标题翻译：具有分层升压电力线方案的半导体存储器件
公开(公告)号：US5652730A
公开(公告)日：1997-07-29
申请号：US648607
申请日：1996-05-15
申请人： Takashi Kono , Kiyohiro Furutani , Mikio Asakura , Hideto Hidaka
发明人： Takashi Kono , Kiyohiro Furutani , Mikio Asakura , Hideto Hidaka
IPC分类号： G11C11/407 , G11C8/12 , G11C11/4074 , G11C11/408 , G11C11/409 , G11C13/00
CPC分类号： G11C11/4085 , G11C11/4074 , G11C8/12
摘要： A DRAM includes an internal boosting circuit, a global power-line, a plurality of blocks, a row decoder, and a POR generating circuit. Each block includes word lines, local power-lines, AND gates, drive transistors, and word line drivers. The AND gate turns a corresponding drive transistor on/off in response to a power on reset signal /POR and a corresponding block select signal. Therefore, all the local boosted power-lines are connected to the global boosted power-line during a power on reset period, whereby all the local boosted power-lines are initially charged up to boosted power supply potential Vpp.
摘要翻译： DRAM包括内部升压电路，全局电源线，多个块，行解码器和POR发生电路。每个块包括字线，本地电源线，与门，驱动晶体管和字线驱动器。 AND门响应于上电复位信号/ POR和相应的块选择信号而使相应的驱动晶体管导通/截止。因此，所有本地升压电源线在上电复位期间连接到全局升压电源线，由此所有本地升压电源线最初都被充电至提升电源电位Vpp。

5. 发明授权

US6157588A Semiconductor memory device having hierarchical word line structure 失效
标题翻译：具有分层字线结构的半导体存储器件
公开(公告)号：US6157588A
公开(公告)日：2000-12-05
申请号：US229343
申请日：1999-01-13
申请人： Yasuhiro Matsumoto , Mikio Asakura , Takeshi Hamamoto , Kei Hamade
发明人： Yasuhiro Matsumoto , Mikio Asakura , Takeshi Hamamoto , Kei Hamade
IPC分类号： G11C11/407 , G11C7/18 , G11C11/401 , G11C11/409 , G11C11/4097 , H01L21/8242 , H01L27/108 , G11C7/02
CPC分类号： G11C7/18 , G11C11/4097
摘要： First and second global input/output lines are twisted between first and second main blocks. First and second SD signal lines in the first main block are respectively arranged adjacent to first and second global input/output lines. First and second SD signal lines in the second main block are respectively arranged adjacent to the second and first global input/output lines. An SD signal supplied for the first or second SD signal line makes noises applied to the first and second global input/output lines identical, so that an influence by the noises is substantially eliminated between the first and second global input/output lines. As a result, the global input/output line is provided with higher resistance to noise without any increase in a layout area.
摘要翻译：第一和第二全局输入/输出线在第一和第二主块之间扭转。第一主块中的第一和第二SD信号线分别布置成与第一和第二全局输入/输出线相邻。第二主块中的第一和第二SD信号线分别布置成与第二和第一全局输入/输出线相邻。为第一或第二SD信号线提供的SD信号对第一和第二全局输入/输出线施加相同的噪声，使得在第一和第二全局输入/输出线之间基本上消除了噪声的影响。因此，全球输入/输出线路具有更高的抗噪声能力，而不会增加布局面积。

6. 发明授权

US5650975A Semiconductor memory device having improved hierarchical I/O line pair structure 失效
标题翻译：具有改进的分级I / O线对结构的半导体存储器件
公开(公告)号：US5650975A
公开(公告)日：1997-07-22
申请号：US710109
申请日：1996-09-12
申请人： Kei Hamade , Kenichi Yasuda , Mikio Asakura , Hideto Hidaka
发明人： Kei Hamade , Kenichi Yasuda , Mikio Asakura , Hideto Hidaka
IPC分类号： G11C11/401 , G11C7/10 , H01L21/8242 , H01L27/108 , G11C13/00
CPC分类号： G11C7/10 , G11C7/1048
摘要： In a memory plane of a semiconductor memory device, transmission gate circuits for transferring data between local I/O line pair and global I/O line pair, and equalizing circuits for equalizing the local I/O line pair are arranged alternately on both sides of a shunt region. All the global I/O line pairs extend entirely over the memory plane. One and the other global I/O lines are arranged in symmetry, with a line for transmitting bit line precharge voltage, cell plate voltage or local input/output line equalizing signal being the center.
摘要翻译：在半导体存储器件的存储器平面中，用于在本地I / O线对和全局I / O线对之间传输数据的传输门电路以及用于均衡本地I / O线对的均衡电路交替布置在一个分流区域。所有全局I / O线对完全延伸到存储器平面上。一个和另一个全局I / O线对称布置，用于传输位线预充电电压，单元板电压或本地输入/输出线均衡信号为中心的线。

7. 发明授权

US06469327B1 Semiconductor device with efficiently arranged pads 失效
标题翻译：半导体器件具有高效布置的焊盘
公开(公告)号：US06469327B1
公开(公告)日：2002-10-22
申请号：US08900515
申请日：1997-07-25
申请人： Kenichi Yasuda , Hideto Hidaka , Mikio Asakura , Tsukasa Ooishi , Kei Hamade
发明人： Kenichi Yasuda , Hideto Hidaka , Mikio Asakura , Tsukasa Ooishi , Kei Hamade
IPC分类号： H01L2710
CPC分类号： H01L23/50 , H01L24/06 , H01L24/48 , H01L27/0207 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/06136 , H01L2224/48091 , H01L2224/4826 , H01L2224/73215 , H01L2924/00014 , H01L2924/01005 , H01L2924/01024 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3011 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099 , H01L2224/05599 , H01L2224/85399
摘要： Pads are alignedly arranged in a central region of a semiconductor chip and are also arranged at an outer peripheral portion of the central portion of the chip. A pad at the outer peripheral portion is electrically connected to a die pad mounting the chip thereon with an insulative material interposed therebetween. A potential supplied to the pad positioned at the outer peripheral portion can be stabilized by parasitic capacitance of the die pad, and a potential of the die pad can be externally monitored easily by removing away a portion of mold resin after resin sealing. Further, due to a cress shaped arrangement of the pads, a voltage down converter can be arranged in line with the pads and at outer periphery of the chip without area penalty. In testing operation, a switching circuit switches a function of a pad to another pad so that cross-shapedly arranged pads are equivalently arranged in a line.
摘要翻译：垫片排列在半导体芯片的中心区域中，并且还布置在芯片的中心部分的外周部分。外周部分的焊盘与安装芯片的芯片焊盘电连接，绝缘材料插入其间。通过芯片焊盘的寄生电容可以使供给位于外周部的焊盘的电位稳定，并且能够通过在树脂密封后除去一部分模制树脂来容易地外部监视焊盘的电位。此外，由于焊盘的水平排列，可以将电压降压转换器布置成与焊盘和芯片的外周边一致，而不会造成区域损失。在测试操作中，切换电路将焊盘的功能切换到另一焊盘，使得十字形布置的焊盘等价地布置成一行。

8. 发明授权

US06301163B1 Semiconductor memory device and method of checking same for defect 有权
标题翻译：半导体存储器件及其检查方法为缺陷
公开(公告)号：US06301163B1
公开(公告)日：2001-10-09
申请号：US09385582
申请日：1999-08-27
申请人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
发明人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
IPC分类号： G11C2900
CPC分类号： G11C29/24
摘要： A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.
摘要翻译：一种半导体存储器件，包括用于在测试模式下选择正常行中的存储单元的第一测试行解码器（9a），用于选择备用存储单元行的第二测试行解码器（9b），用于选择的第一测试列解码器正常列中的存储单元，以及用于选择备用存储单元列的第二测试列解码器（10b）。控制电路（11）可以通过使用控制信号（SRT）和控制信号（SCT）来执行行和列解码器的四个组合之间的切换。所有备用存储器单元在修补缺陷存储器单元以进行产量增强之前被测试。

9. 发明授权

US5764576A Semiconductor memory device and method of checking same for defect 失效
公开(公告)号：US5764576A
公开(公告)日：1998-06-09
申请号：US752419
申请日：1996-11-19
申请人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
发明人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04 , G11C29/14 , G11C29/24
CPC分类号： G11C29/24
摘要： A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.

10. 发明授权

US5740119A Semiconductor memory device having internal address converting function, whose test and layout are conducted easily 失效
公开(公告)号：US5740119A
公开(公告)日：1998-04-14
申请号：US756505
申请日：1996-11-26
申请人： Mikio Asakura , Hideto Hidaka , Kiyohiro Furutani , Kenichi Yasuda
发明人： Mikio Asakura , Hideto Hidaka , Kiyohiro Furutani , Kenichi Yasuda
IPC分类号： G11C8/12 , G11C11/401 , G11C11/406 , G11C29/00 , G11C29/14 , G11C29/28 , G11C29/56 , G11C7/00
CPC分类号： G11C11/406 , G11C29/28 , G11C8/12
摘要： In a semiconductor memory device selectively implementing one of a 4K refresh cycle and a 8K refresh cycle, the positions of externally applied address signal bits are switched internally by address switching circuits such that memory cells at the same positions are selected regardless of whether the 4K refresh cycle or the 8K refresh cycle is specified according to a refresh cycle mode specify signal. As a result, by testing the device in one refresh cycle mode, the device can be checked in both refresh cycle operations, reducing the test time and making the test easier.

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