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    • 2. 发明授权
    • Method of manufacturing a semiconductor device
    • 制造半导体器件的方法
    • US08440521B2
    • 2013-05-14
    • US13067788
    • 2011-06-27
    • Naomi FukumakiEiji HasegawaToshihiro IizukaIchiro Yamamoto
    • Naomi FukumakiEiji HasegawaToshihiro IizukaIchiro Yamamoto
    • H01L21/3105
    • H01L21/823857H01L21/823842
    • A method of manufacturing a semiconductor device having a p-type field effect transistor and an n-type field effect transistor includes the steps of: forming an interface insulating layer and a high-permittivity layer on a substrate in the stated order; forming a pattern of a sacrifice layer on the high-permittivity layer; forming a metal-containing film containing metal elements therein on the high-permittivity layer in a first region where the sacrifice layer is formed and a second region where no sacrifice layer is formed; introducing the metal elements into an interface between the interface insulating layer and the high-permittivity layer in the second region by conducting a heat treatment; and removing the sacrifice layer by wet etching, wherein in the removing step, the sacrifice layer is etched easily more than the high-permittivity layer. With this configuration, the semiconductor device excellent in reliability is obtained.
    • 制造具有p型场效应晶体管和n型场效应晶体管的半导体器件的方法包括以下步骤:按照所述顺序在衬底上形成界面绝缘层和高电容率层; 在高电介质层上形成牺牲层的图案; 在形成有牺牲层的第一区域和形成牺牲层的第二区域的高介电常数层上形成含有金属元素的含金属膜; 通过进行热处理,将金属元素引入第二区域中的界面绝缘层与高电容率层之间的界面; 并且通过湿法蚀刻去除牺牲层,其中在去除步骤中,牺牲层比高介电常数层容易蚀刻。 由此,能够获得可靠性优异的半导体装置。
    • 10. 发明授权
    • Semiconductor device with improved peripheral resistance element and method for fabricating same
    • 具有改进的外围电阻元件的半导体器件及其制造方法
    • US06696719B2
    • 2004-02-24
    • US09729803
    • 2000-12-06
    • Ichiro Yamamoto
    • Ichiro Yamamoto
    • H01L2976
    • H01L27/10894H01L27/10852H01L28/20H01L28/40H01L29/94
    • A semiconductor device in which a cell capacitor with an MIM or MIS structure is formed using a conductive material with a low resistivity for the upper electrode and a resistance element is formed using a conductive material with high resistance without increasing the complexity of the fabrication process. A plate electrode used for the upper electrode of the cell capacitor and for the resistance element is made by forming a three-layer structure including a low resistance conductive material layer, an insulating film layer on the low resistance conductive material layer, and a high resistance conductive material layer on the insulating film layer, patterning the three-layer structure in the same shape, and using the low resistance conductive material layer as the upper electrode of the cell capacitor and the high resistance conductive material layer as the resistance element.
    • 使用具有低电阻率的导电材料形成具有MIM或MIS结构的电池电容器的半导体器件,并且电阻元件使用具有高电阻的导电材料形成,而不增加制造工艺的复杂性。 用于电池电容器和电阻元件的上电极的平板电极是通过在低电阻导电材料层上形成包括低电阻导电材料层,绝缘膜层和高电阻的三层结构制成的 在绝缘膜层上形成导电材料层,对相同形状的三层结构进行构图,并使用低电阻导电材料层作为电池电容器和高电阻导电材料层的上电极作为电阻元件。