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1. 发明申请

US20060147813A1 Mask and method to pattern chromeless phase lithography contact hole 有权
标题翻译：掩模和方法来绘制无铬相光刻接触孔
公开(公告)号：US20060147813A1
公开(公告)日：2006-07-06
申请号：US11028421
申请日：2005-01-03
申请人： Sya Tan , Soon Tan , Qun Lin , Hury Chong , Liang Hsia
发明人： Sya Tan , Soon Tan , Qun Lin , Hury Chong , Liang Hsia
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： G03F1/34
摘要： A chromeless phase shift mask and Method for making and using. The A chromeless phase shift mask is used to pattern contact holes. The chromeless phase shift mask preferably comprises: a first phase shift region and a second phase shfit region; the first region is comprised of a unit cell which is comprised of a rectangular center section and at least three rectangular sections (legs) outwards extending from the rectangular center section. The second region is adjacent to said first region. The interference between the first and second phase shift regions creates a contact hole pattern.
摘要翻译：无色相移掩模和制造和使用方法。 A无铬相移掩模用于对接触孔进行图案化。无铬相移掩模优选地包括：第一相移区域和第二相位区域; 第一区域包括由矩形中心部分和从矩形中心部分向外延伸的至少三个矩形部分（腿）的单元电池。第二区域与所述第一区域相邻。第一和第二相移区域之间的干涉产生接触孔图案。

2. 发明申请

US20060105520A1 Structure and method to fabricate a protective sidewall liner for an optical mask 审中-公开
标题翻译：用于制造光学掩模的保护侧壁衬里的结构和方法
公开(公告)号：US20060105520A1
公开(公告)日：2006-05-18
申请号：US10992447
申请日：2004-11-18
申请人： Sia Tan , Qun Lin , Liang Hsia
发明人： Sia Tan , Qun Lin , Liang Hsia
IPC分类号： H01L21/8242
CPC分类号： G03F1/30
摘要： Methods and structures for optical masks that have a liner on the trench sidewalls. An example embodiment comprises a mask structure for use with light at a wavelength comprising: a substrate having a first region, a second region and a third region; a first trench in the first region; a first region having a first thickness of a first material, the first material having a first amount of transmission of light at the wavelength, the second region having a second thickness of the first material, such that the second thickness is greater than the first thickness by a first difference, the first difference being equivalent to a phase shift of 180 degrees at the wavelength, and a third region located on the substrate, the third region having a third thickness of the first material, such that the third thickness is equal to or greater than the second thickness; a liner on the sidewalls of the trench. The liner reduces the reflections from the trench sidewall. The embodiments can be used with single and double phase shift masks and with chromeless phase lithography masks.
摘要翻译：在沟槽侧壁上具有衬垫的光学掩模的方法和结构。示例性实施例包括用于波长为的光的掩模结构，包括：具有第一区域，第二区域和第三区域的衬底; 第一个区域的第一个沟槽; 具有第一材料的第一厚度的第一区域，所述第一材料具有在所述波长处的第一光透射量，所述第二区域具有所述第一材料的第二厚度，使得所述第二厚度大于所述第一厚度通过第一差异，第一差异等于在波长处180度的相移，以及位于基板上的第三区域，第三区域具有第一材料的第三厚度，使得第三厚度等于或大于第二厚度; 在沟槽的侧壁上的衬垫。衬垫减少了从沟槽侧壁的反射。这些实施例可以用于单相和双相位掩模和无铬相光刻掩模。

3. 发明申请

US20060234479A1 Implantation-less approach to fabricating strained semiconductor on isolation wafers 有权
标题翻译：无离子方法在隔离晶圆上制造应变半导体
公开(公告)号：US20060234479A1
公开(公告)日：2006-10-19
申请号：US11107712
申请日：2005-04-15
申请人： Jinping Liu , Dong Sohn , Liang Hsia
发明人： Jinping Liu , Dong Sohn , Liang Hsia
IPC分类号： H01L21/20 , H01L21/265 , H01L21/36 , H01L31/20
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/02395 , H01L21/02447 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/0251 , H01L21/02532 , H01L21/02664 , H01L21/76262 , H01L29/78 , Y10S438/933
摘要： A method of fabrication of semiconductor substrate structure comprising the following. A buffer layer is formed on the Si Substrate. We form a SiGe layer on the novel buffer layer. The buffer layer has defects therein so that the buffer layer is oxidized to form a buried isolation layer comprised of silicon oxide and an oxide layer and oxidize the SiGe layer for form a oxide layer. The oxide layer is then removed. An upper semiconductor layer (e.g., Si, SiGe or Ge layer) is epitaxially formed on the SiGe layer. Devices are formed on said an upper semiconductor layer. The buffer layer can be formed by several aspects.
摘要翻译：一种制造半导体衬底结构的方法，包括以下步骤。在Si基板上形成缓冲层。我们在新型缓冲层上形成SiGe层。缓冲层在其中具有缺陷，使得缓冲层被氧化以形成由氧化硅和氧化物层组成的掩埋隔离层，并氧化SiGe层以形成氧化物层。然后除去氧化物层。在SiGe层上外延形成上半导体层（例如Si，SiGe或Ge层）。器件形成在所述上半导体层上。缓冲层可以由几个方面形成。

4. 发明申请

US20060105533A1 Method for engineering hybrid orientation/material semiconductor substrate 审中-公开
标题翻译：工程混合取向/材料半导体衬底的方法
公开(公告)号：US20060105533A1
公开(公告)日：2006-05-18
申请号：US10990180
申请日：2004-11-16
申请人： Yung Chong , Liang Hsia , Chew Ang
发明人： Yung Chong , Liang Hsia , Chew Ang
IPC分类号： H01L21/8228
CPC分类号： H01L21/823807
摘要： The embodiments provide a structure and a method of manufacturing a semiconductor structure that has a different material in the area where PMOS devices will be formed than in the area where NMOS devices will be formed which is characterized as follows. An embodiment comprises the following steps. A substrate is provided. The substrate has a NMOS area and a PMOS area. We form a NMOS mask over the NMOS area. We form a first semiconductor layer over the PMOS area. We remove the mask. We form a second semiconductor layer over the NMOS area. Then we form an isolation region in the substrate between at least portions of the NMOS and the PMOS areas. We form PMOS devices in the PMOS area and form NMOS devices in the NMOS area.
摘要翻译：实施例提供一种制造半导体结构的结构和方法，该半导体结构在将要形成PMOS器件的区域中将具有不同于在其上将形成NMOS器件的区域中的材料，其特征如下。实施例包括以下步骤。提供基板。衬底具有NMOS区域和PMOS区域。我们在NMOS区域上形成NMOS掩模。我们在PMOS区域上形成第一半导体层。我们删除面具。我们在NMOS区域上形成第二个半导体层。然后，在NMOS和PMOS区域的至少一部分之间，在衬底中形成隔离区。我们在PMOS区域中形成PMOS器件，并在NMOS区域中形成NMOS器件。

5. 发明申请

US20050164473A1 Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch 有权
标题翻译：在具有大晶格失配的衬底上形成松散半导体缓冲层的方法
公开(公告)号：US20050164473A1
公开(公告)日：2005-07-28
申请号：US10763305
申请日：2004-01-23
申请人： Jin Liu , Dong Sohn , Liang Hsia
发明人： Jin Liu , Dong Sohn , Liang Hsia
IPC分类号： C30B29/52 , H01L21/20 , H01L29/10 , C30B1/00
CPC分类号： C30B29/52 , H01L21/02381 , H01L21/0245 , H01L21/02463 , H01L21/02502 , H01L21/0251 , H01L21/02532 , H01L21/02543 , H01L21/0262 , H01L29/1054 , Y10S438/933
摘要： A method of forming a relaxed silicon-germanium layer for use as an underlying layer for a subsequent overlying tensile strain silicon layer, has been developed. The method features initial growth of a underlying first silicon-germanium layer on a semiconductor substrate, compositionally graded to feature the largest germanium content at the interface of the first silicon-germanium layer and the semiconductor substrate, with the level of germanium decreasing as the growth of the graded first silicon-germanium layer progresses. This growth sequence allows the largest lattice mismatch and greatest level of threading dislocations to be present at the bottom of the graded silicon-germanium layer, with the magnitude of lattice mismatch and threading dislocations decreasing as the growth of the graded silicon-germanium layer progresses. In situ growth of an overlying silicon-germanium layer featuring uniform or non-graded germanium content, results in a relaxed silicon-germanium layer with a minimum of dislocations propagating from the underlying graded silicon-germanium layer. In situ growth of a silicon layer results in a tensile strain, low defect density layer to be used for MOSFET device applications.
摘要翻译：已经开发了形成用于随后的上覆拉伸应变硅层的下层的松弛硅 - 锗层的方法。该方法的特征在于半导体衬底上的底层第一硅 - 锗层的初始生长，其组成分级以在第一硅 - 锗层和半导体衬底的界面处具有最大的锗含量，锗的含量随着生长的分级第一硅锗层进行。该生长序列允许最大的晶格失配和最高级别的穿透位错存在于渐变硅 - 锗层的底部，随着梯度硅 - 锗层的生长进行，晶格失配和穿透位错的大小减小。具有均匀或非分级锗含量的上覆硅锗层的原位生长导致松弛的硅 - 锗层，其中最小的位错从下面的梯度硅 - 锗层传播。硅层的原位生长导致用于MOSFET器件应用的拉伸应变，低缺陷密度层。

6. 发明申请

US20070134941A1 Structure and method to prevent charge damage from e-beam curing process 有权
标题翻译：防止电子束固化过程中电荷损伤的结构和方法
公开(公告)号：US20070134941A1
公开(公告)日：2007-06-14
申请号：US11297485
申请日：2005-12-08
申请人： Huang Liu , Bei Zhang , Wuping Liu , John Sudijono , Liang Hsia
发明人： Huang Liu , Bei Zhang , Wuping Liu , John Sudijono , Liang Hsia
IPC分类号： H01L21/469
CPC分类号： H01L21/31058 , B05D3/068 , H01J2237/04735 , H01J2237/3156 , H01L21/02112 , H01L21/02274 , H01L21/02351 , H01L21/3105 , H01L21/312 , H01L21/31633 , H01L21/76825 , H01L21/76834
摘要： An example embodiment is a method of curing a film over a semiconductor structure. We provide a semiconductor structure comprised of a substrate and an interconnect structure. We provide a film over the semiconductor structure. We provide an electron source, an anode grid between the electron source and the semiconductor structure. We cure the film by exposing the film to an electron beam from the electron source that passes through the anode grid. We control the electron beam by controlling the bias voltage between the anode grid and the semiconductor structure. Another embodiment is a tool for curing a film.
摘要翻译：示例性实施例是在半导体结构上固化膜的方法。我们提供由衬底和互连结构组成的半导体结构。我们提供半导体结构的电影。我们提供电子源，电子源和半导体结构之间的阳极栅极。我们通过将膜暴露于电子源通过阳极栅格的电子束来固化膜。我们通过控制阳极栅极和半导体结构之间的偏置电压来控制电子束。另一个实施例是用于固化膜的工具。

7. 发明申请

US20060160290A1 Method to fabricate variable work function gates for FUSI devices 有权
标题翻译：为FUSI设备制造可变功能门的方法
公开(公告)号：US20060160290A1
公开(公告)日：2006-07-20
申请号：US11039428
申请日：2005-01-20
申请人： Yung Chong , Dong Sohn , Chew-Hue Ang , Purakh Vermo , Liang Hsia
发明人： Yung Chong , Dong Sohn , Chew-Hue Ang , Purakh Vermo , Liang Hsia
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823835 , H01L21/823842
摘要： An embodiment of fabrication of a variable work function gates in a FUSI device is described. The embodiment uses a work function doping implant to dope the polysilicon to achieve a desired work function. Selective epitaxy growth (SEG) is used to form silicon over the source/drain regions. The doped poly-Si gate is fully silicided to form fully silicided gates that have a desired work function. We provide a substrate having a NMOS region and a PMOS region. We form a gate dielectric layer and a gate layer over said substrate. We perform a (gate Vt) gate layer implant process to implant impurities such as P+, As+, B+, BF2+, N+, Sb+, In+, C+, Si+, Ge+ or Ar+ into the gate layer gate in the NMOS gate regions and said PMOS gate regions. We form a cap layer over said gate layer. We pattern said cap layer, said gate layer and said gate dielectric layer to form a NMOS gate and a PMOS gate. Spacers are formed and S/D regions are formed. A metal is deposited over said substrate surface. We anneal said metal layer to form fully silicided NMOS gate and fully silicided PMOS gate.
摘要翻译：描述了在FUSI设备中制造可变功函数门的实施例。该实施例使用功函数掺杂注入来掺杂多晶硅以实现所需的功函数。选择性外延生长（SEG）用于在源极/漏极区域上形成硅。掺杂的多晶硅栅极被完全硅化以形成具有所需功函数的完全硅化栅极。我们提供具有NMOS区和PMOS区的衬底。我们在所述衬底上形成栅极介电层和栅极层。我们进行（栅极Vt）栅极层注入工艺，将诸如P +，As +，B +，BF 2 +，N +，Sb +，In +，C +，Si +，Ge +或Ar +的杂质注入栅极层 NMOS栅极区域和所述PMOS栅极区域中的栅极。我们在所述栅极层上形成覆盖层。我们对所述盖层，所述栅极层和所述栅极电介质层进行图案化以形成NMOS栅极和PMOS栅极。形成间隔物并形成S / D区域。在所述衬底表面上沉积金属。我们退火所述金属层以形成完全硅化的NMOS栅极和完全硅化的PMOS栅极。

8. 发明申请

US20060128156A1 Self-patterning of photo-active dielectric materials for interconnect isolation 有权
标题翻译：用于互连隔离的光电介质材料的自构图
公开(公告)号：US20060128156A1
公开(公告)日：2006-06-15
申请号：US11345890
申请日：2006-02-02
申请人： Wuping Liu , Bei Zhang , Liang Hsia
发明人： Wuping Liu , Bei Zhang , Liang Hsia
IPC分类号： H01B13/00 , H01L21/311 , B44C1/22 , C03C25/68
CPC分类号： H01L21/76814 , H01L21/4846 , H01L21/76802 , H01L21/76807 , H01L21/76828 , H01L23/5329 , H01L2221/1026 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： In accordance with the objectives of the invention a new method is provided for the creation of an interconnect pattern. The invention provides for a layer of Photo-Active Dielectric (PAD) to be used for the insulation material in which the interconnect pattern is created, this without the use of an overlying exposure mask of photoresist.
摘要翻译：根据本发明的目的，提供了一种用于创建互连图案的新方法。本发明提供了一种用于产生互连图案的绝缘材料的光电介质（PAD）层，不需要使用光致抗蚀剂的上覆曝光掩模。

9. 发明申请

US20060008973A1 Selective oxide trimming to improve metal T-gate transistor 有权
标题翻译：选择性氧化物修整以改善金属T型栅极晶体管
公开(公告)号：US20060008973A1
公开(公告)日：2006-01-12
申请号：US10885855
申请日：2004-07-07
申请人： Timothy Phua , Kheng Tee , Liang Hsia
发明人： Timothy Phua , Kheng Tee , Liang Hsia
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L29/6653 , H01L21/26586 , H01L21/28079 , H01L21/28123 , H01L21/823842 , H01L21/82385 , H01L21/823857 , H01L29/495 , H01L29/66545
摘要： A process to form a FET using a replacement gate. An example feature is that the PMOS sacrificial gate is made narrower than the NMOS sacrificial gate. The PMOS gate is implanted preferably with Ge to increase the amount of poly sacrificial gate that is oxidized to form PMOS spacers. The spacers are used as masks for the LDD Implant. The space between the PLLD regions is preferably larger that the space between the NLDD regions because of the wider PMOS spacers. The PLDD tends to diffuse readily more than NLDD due to the dopant being small and light (i.e. Boron). The wider spacer between the PMOS regions improves device performance by improving the short channel effects for PMOS. In addition, the oxidization of the sacrificial gates allows trimming of sacrificial gates thus extending the limitation of lithography. Another feature of an embodiment is that a portion of the initial pad oxide is removed, thus reducing the amount of undercut created during the channel oxide strip for the dummy gate process. This would improve on the gate overlap capacitance for a T-gate transistor. In a second embodiment, two metal gates with different work functions are formed.
摘要翻译：使用替换栅极形成FET的工艺。一个示例特征是使PMOS牺牲栅极比NMOS牺牲栅极窄。 PMOS栅极优选用Ge注入以增加被氧化形成PMOS间隔物的多晶牺牲栅极的量。间隔件用作LDD植入物的掩模。由于较宽的PMOS间隔物，PLLD区之间的空间优选大于NLDD区之间的空间。由于掺杂剂小且轻（即硼），PLDD容易从NLDD扩散更多。 PMOS区域之间的较宽间隔通过改善PMOS的短沟道效应来提高器件性能。此外，牺牲栅极的氧化允许修剪牺牲栅极，从而延长了光刻的限制。一个实施例的另一个特征是初始衬垫氧化物的一部分被去除，从而减少了在用于虚拟栅极处理的沟道氧化物带期间产生的底切的量。这将提高T栅极晶体管的栅极重叠电容。在第二实施例中，形成具有不同功函数的两个金属栅极。

10. 发明申请

US20050170625A1 Novel method to control dual damascene trench etch profile and trench depth uniformity 有权
标题翻译：控制双镶嵌沟槽蚀刻轮廓和沟槽深度均匀性的新方法
公开(公告)号：US20050170625A1
公开(公告)日：2005-08-04
申请号：US10767292
申请日：2004-01-29
申请人： Hai Cong , Yong Siew , Liang Hsia
发明人： Hai Cong , Yong Siew , Liang Hsia
IPC分类号： H01L21/44 , H01L21/768
CPC分类号： H01L21/76808
摘要： A method of forming trench openings in a dual damascene trench and via etch process by using a two component hard mask layer, termed a bi-layer, over different intermetal dielectrics, IMD, to solve dual damascene patterning problems, such as, fencing and sub-trench formation. Via first patterning in dual damascene processing is one of the major integration schemes for copper backend of line (BEOL) integration. Via first dual damascene scheme usually uses a hard mask layer deposited on top of an inter-metal dielectric (IMD) film stack. The dual damascene trench etch requires uniform trench depth across wafer after etch. In addition, via top corner profiles need to be well maintained without any fencing or faceting. The present method solves these problems by using a two component hard mask layer, termed a bi-layer, deposited directly on top of an inter-metal dielectric (IMD) film stack.
摘要翻译：一种在双镶嵌沟槽和通孔蚀刻工艺中形成沟槽开口的方法，其通过使用称为双层的双组分硬掩模层在不同的金属间电介质IMD之间，以解决双镶嵌图案化问题，例如栅栏和子螺旋形成。通过在双镶嵌处理中的首次图案化是铜后端（BEOL）集成的主要集成方案之一。通过第一双镶嵌方案通常使用沉积在金属间电介质（IMD）膜堆叠顶部上的硬掩模层。双镶嵌沟槽蚀刻需要在蚀刻后跨晶片的均匀沟槽深度。此外，通过顶角型材需要维护良好，没有任何围栏或小面。本方法通过使用直接沉积在金属间电介质（IMD）膜堆叠的顶部上的双组分硬掩模层来解决这些问题。

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