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1. 发明授权

US09122486B2 Bimodal branch predictor encoded in a branch instruction 有权
标题翻译：双分支预测器在分支指令中编码
公开(公告)号：US09122486B2
公开(公告)日：2015-09-01
申请号：US12941105
申请日：2010-11-08
申请人： Suresh K. Venkumahanti , Lucian Codrescu , Stephen R. Shannon , Lin Wang , Phillip M. Jones , Daisy T. Palal , Jiajin Tu
发明人： Suresh K. Venkumahanti , Lucian Codrescu , Stephen R. Shannon , Lin Wang , Phillip M. Jones , Daisy T. Palal , Jiajin Tu
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3844
摘要： Each branch instruction having branch prediction support has branch prediction bits in architecture specified bit positions in the branch instruction. An instruction cache supports modifying the branch instructions with updated branch prediction bits that are dynamically determined when the branch instruction executes.
摘要翻译：具有分支预测支持的每个分支指令在分支指令中的架构指定的位位置具有分支预测位。指令高速缓存支持使用在分支指令执行时动态确定的更新的分支预测位修改分支指令。

2. 发明申请

US20120117327A1 Bimodal Branch Predictor Encoded in a Branch Instruction 有权
标题翻译：在分支指令中编码的双模分支预测器
公开(公告)号：US20120117327A1
公开(公告)日：2012-05-10
申请号：US12941105
申请日：2010-11-08
申请人： Suresh K. Venkumahanti , Lucian Codrescu , Stephen R. Shannon , Lin Wang , Phillip M. Jones , Daisy T. Palal , Jiajin Tu
发明人： Suresh K. Venkumahanti , Lucian Codrescu , Stephen R. Shannon , Lin Wang , Phillip M. Jones , Daisy T. Palal , Jiajin Tu
IPC分类号： G06F12/08
CPC分类号： G06F9/3844
摘要： Each branch instruction having branch prediction support has branch prediction bits in architecture specified bit positions in the branch instruction. An instruction cache supports modifying the branch instructions with updated branch prediction bits that are dynamically determined when the branch instruction executes.
摘要翻译：具有分支预测支持的每个分支指令在分支指令中的架构指定的位位置具有分支预测位。指令高速缓存支持使用在分支指令执行时动态确定的更新的分支预测位修改分支指令。

3. 发明授权

US07685411B2 Multi-mode instruction memory unit 有权
标题翻译：多模式指令存储单元
公开(公告)号：US07685411B2
公开(公告)日：2010-03-23
申请号：US11104115
申请日：2005-04-11
申请人： Muhammad Ahmed , Lucian Codrescu , Erich Plondke , William C. Anderson , Robert Allan Lester , Phillip M. Jones
发明人： Muhammad Ahmed , Lucian Codrescu , Erich Plondke , William C. Anderson , Robert Allan Lester , Phillip M. Jones
IPC分类号： G06F9/00
CPC分类号： G06F9/325 , G06F9/3802 , G06F9/3804 , G06F9/381
摘要： An instruction memory unit comprises a first memory structure operable to store program instructions, and a second memory structure operable to store program instructions fetched from the first memory structure, and to issue stored program instructions for execution. The second memory structure is operable to identify a repeated issuance of a forward program redirect construct, and issue a next program instruction already stored in the second memory structure if a resolution of the forward branching instruction is identical to a last resolution of the same. The second memory structure is further operable to issue a backward program redirect construct, determine whether a target instruction is stored in the second memory structure, issue the target instruction if the target instruction is stored in the second memory structure, and fetch the target instruction from the first memory structure if the target instruction is not stored in the second memory structure.
摘要翻译：指令存储单元包括可操作以存储程序指令的第一存储器结构，以及可操作以存储从第一存储器结构提取的程序指令并且发出用于执行的存储的程序指令的第二存储器结构。如果前向分支指令的分辨率与其最后一个分辨率相同，则第二存储器结构可操作以识别正向程序重定向构造的重复发出，并发出已经存储在第二存储器结构中的下一个程序指令。第二存储器结构还可操作以发出反向程序重定向结构，确定目标指令是否存储在第二存储器结构中，如果目标指令存储在第二存储器结构中，则发出目标指令，并从如果目标指令没有存储在第二存储器结构中的第一存储器结构。

4. 发明授权

US06961800B2 Method for improving processor performance 失效
标题翻译：提高处理器性能的方法
公开(公告)号：US06961800B2
公开(公告)日：2005-11-01
申请号：US09967155
申请日：2001-09-28
申请人： Robert A. Lester , Kenneth T. Chin , Jim Blocker , John E. Larson , Phillip M. Jones , Paul B. Rawlins
发明人： Robert A. Lester , Kenneth T. Chin , Jim Blocker , John E. Larson , Phillip M. Jones , Paul B. Rawlins
IPC分类号： G06F13/00 , G06F13/16 , G06F13/36
CPC分类号： G06F13/1657
摘要： Methods for improving processor performance. Specifically, by reducing some of the latency cycles within a host controller, request processing speed can be improved. One technique for improving processing speed involves initiating a deferred reply transaction before the data is available from a memory controller. A second technique involves anticipating the need to transition from a block next request (BNR) state to a bus priority request (BPRI) state, thereby eliminating the need to wait for a request check to determine if the BPRI state must be implemented.
摘要翻译：提高处理器性能的方法。具体地，通过减少主机控制器内的一些延迟周期，可以提高请求处理速度。用于提高处理速度的一种技术涉及在从存储器控制器获得数据之前发起延迟回复事务。第二种技术涉及预期从块下一个请求（BNR）状态转换到总线优先级请求（BPRI）状态的需要，从而消除了等待请求检查以确定是否必须实现BPRI状态的需要。

5. 发明授权

US06823409B2 Coherency control module for maintaining cache coherency in a multi-processor-bus system 有权
标题翻译：用于在多处理器总线系统中维持高速缓存一致性的一致性控制模块
公开(公告)号：US06823409B2
公开(公告)日：2004-11-23
申请号：US09965894
申请日：2001-09-28
申请人： Phillip M. Jones , Paul B. Rawlins
发明人： Phillip M. Jones , Paul B. Rawlins
IPC分类号： G06F1300
CPC分类号： G06F12/0831 , G06F12/082
摘要： A mechanism for efficiently filtering snoop requests in a multi-processor bus system. Specifically, a snoop filter is provided to filter unnecessary snoops in a multi-bus system.
摘要翻译：一种用于在多处理器总线系统中有效过滤窥探请求的机制。具体来说，提供了一个窥探过滤器来过滤多总线系统中的不必要的窥探。

6. 发明授权

US06505260B2 Computer system with adaptive memory arbitration scheme 失效
标题翻译：具有自适应内存仲裁方案的计算机系统
公开(公告)号：US06505260B2
公开(公告)日：2003-01-07
申请号：US09784690
申请日：2001-02-15
申请人： Kenneth T. Chin , C. Kevin Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , Jeffrey C. Stevens
发明人： Kenneth T. Chin , C. Kevin Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , Jeffrey C. Stevens
IPC分类号： G06F1318
CPC分类号： G06F13/1605
摘要： A computer system includes an adaptive memory arbiter for prioritizing memory access requests, including a self-adjusting, programmable request-priority ranking system. The memory arbiter adapts during every arbitration cycle, reducing the priority of any request which wins memory arbitration. Thus, a memory request initially holding a low priority ranking may gradually advance in priority until that request wins memory arbitration. Such a scheme prevents lower-priority devices from becoming “memory-starved.” Because some types of memory requests (such as refresh requests and memory reads) inherently require faster memory access than other requests (such as memory writes), the adaptive memory arbiter additionally integrates a nonadjustable priority structure into the adaptive ranking system which guarantees faster service to the most urgent requests. Also, the adaptive memory arbitration scheme introduces a flexible method of adjustable priority-weighting which permits selected devices to transact a programmable number of consecutive memory accesses without those devices losing request priority.
摘要翻译：计算机系统包括用于对存储器访问请求进行优先级的自适应存储器仲裁器，包括自调整可编程请求优先级排序系统。存储器仲裁器在每个仲裁周期内进行调整，从而降低获取内存仲裁的任何请求的优先级。因此，初始保持低优先级排序的存储器请求可以逐渐提前优先，直到该请求赢得存储器仲裁。这样的方案可防止低优先级的设备变得“记忆不足”。因为某些类型的存储器请求（例如刷新请求和存储器读取）固有地需要比其他请求（诸如存储器写入）更快的存储器访问，所以自适应存储器仲裁器另外将不可调整的优先级结构集成到自适应排名系统中，从而保证更快的服务最迫切的要求。此外，自适应存储器仲裁方案引入了可调整优先权重的灵活方法，其允许所选择的设备在没有丢失请求优先级的情况下处理可编程数量的连续存储器访问。

7. 发明授权

US06463510B1 Apparatus for identifying memory requests originating on remote I/O devices as noncacheable 有权
标题翻译：用于将源自远程I / O设备的存储器请求识别为不可缓存的装置
公开(公告)号：US06463510B1
公开(公告)日：2002-10-08
申请号：US09751505
申请日：2000-12-29
申请人： Phillip M. Jones , Robert L. Woods
发明人： Phillip M. Jones , Robert L. Woods
IPC分类号： G06F1200
CPC分类号： G06F12/0835 , G06F12/0888
摘要： An apparatus for identifying memory requests originating on remote I/O devices as non-cacheable in a computer system with multiple processors includes a main memory, memory cache, processor, cache coherence directory and cache coherence controller all coupled to a host bridge unit (North bridge). The I/O device transmits requests for data to an I/O bridge unit. The I/O bridge unit forwards the request for data to the host bridge unit and asserts a sideband signal to the host bridge unit if the request is for non-cacheable data. The sideband signal informs the host bridge unit that the memory request is for non-cacheable data and that the cache coherence controller does not need to perform a cache coherence directory lookup. For cacheable data, the cache coherence controller performs a cache coherence directory lookup to maintain the coherence of data stored in a plurality of processor caches in the computer system.
摘要翻译：用于将在远程I / O设备上发起的存储器请求识别为具有多个处理器的计算机系统中不可缓存的设备包括主存储器，存储器高速缓存，处理器，高速缓存一致性目录和高速缓存一致性控制器，所有这些都连接到主机桥单元桥）。 I / O设备向I / O桥单元发送数据请求。如果请求是用于不可缓存的数据，则I / O桥单元将数据请求转发给主桥单元，并且向主桥单元断言边带信号。边带信号通知主机单元存储器请求用于不可缓存数据，并且高速缓存一致性控制器不需要执行高速缓存一致性目录查找。对于可缓存数据，高速缓存一致性控制器执行高速缓存一致性目录查找以保持存储在计算机系统中的多个处理器高速缓存中的数据的一致性。

8. 发明授权

US06272580B1 Apparatus and method for dynamically elevating a lower level bus master to an upper level bus master within a multi-level arbitration system 有权
标题翻译：一种用于在多级仲裁系统内动态地将较低级总线主机升级到上级总线主机的装置和方法
公开(公告)号：US06272580B1
公开(公告)日：2001-08-07
申请号：US09268825
申请日：1999-03-16
申请人： Jeff Stevens , Robert A. Lester , Phillip M. Jones , Jeff W. Wolford , Peter Lee
发明人： Jeff Stevens , Robert A. Lester , Phillip M. Jones , Jeff W. Wolford , Peter Lee
IPC分类号： G06F13362
CPC分类号： G06F13/362
摘要： A computer system, bus interface unit, and method are provided to allocate requests to a shared bus within the computer system. The bus interface unit includes an arbiter which employs a multi-level, round-robin arbitration protocol. Configuration registers are programmed during boot-up of the computer system by assigning a subset of peripheral devices, bus agents, requesters, or bus masters to either a high priority ring or a low priority ring, if two levels of arbitration are used. The status of a low priority device can be elevated to equal priority with a high priority device by assigning the low priority device to a high priority port within the high priority ring if certain circumstances occur. Namely, if data transfers to or from the low priority device are terminated, then the low priority device will be promoted to a high priority device so that it need not wait until after the all high priority device requests have been polled. Instead, the elevated low priority device is placed on the same level of priority as the high priority devices so that its request can be readily serviced and the transaction completed during a data transfer retry operation.
摘要翻译：提供计算机系统，总线接口单元和方法以将计算机系统中的共享总线分配请求。总线接口单元包括采用多级循环仲裁协议的仲裁器。如果使用两级仲裁，配置寄存器在计算机系统引导期间被编程，通过将外设，总线代理，请求者或总线主机的子集分配到高优先级环或低优先级环。如果发生某些情况，则可以通过将低优先级设备分配给高优先级环中的高优先级端口，将低优先级设备的状态提升为与高优先级设备相等的优先级。也就是说，如果到低优先级设备的数据传输结束，则低优先级设备将被提升为高优先级设备，使得它不需要等到所有高优先级设备请求被轮询之后。相反，升高的低优先级设备被放置在与高优先级设备相同的优先级上，使得其请求可以容易地被服务并且在数据传输重试操作期间完成事务。

9. 发明授权

US06233661B1 Computer system with memory controller that hides the next cycle during the current cycle 失效
标题翻译：带有内存控制器的计算机系统，可在当前周期内隐藏下一个周期
公开(公告)号：US06233661B1
公开(公告)日：2001-05-15
申请号：US09069458
申请日：1998-04-28
申请人： Phillip M. Jones , Gary J. Piccirillo
发明人： Phillip M. Jones , Gary J. Piccirillo
IPC分类号： G06F1314
CPC分类号： G06F13/161
摘要： A computer system includes a processor, a memory device, at least one expansion bus, and a bridge device coupling the processor, memory device, and expansion bus together. The bridge device preferably includes a memory controller that is capable of arbitrating among pending memory requests, and in certain situations, starting the next cycle while the current cycle is finishing. This allows executing at least two memory requests concurrently, thus improving bus utilization and retrieving and storing data in memory occurs more efficiently. The memory controller can start the next memory cycle during the current cycle when the next memory cycle will result in a page miss and a bank hit to a bank that is not associated with the most recently used (MRU) page. Further concurrent memory request execution is possible when the next cycle will be a page miss and bank miss.
摘要翻译：计算机系统包括处理器，存储器件，至少一个扩展总线和将处理器，存储器件和扩展总线耦合在一起的桥接器件。桥接器件优选地包括能够在待处理存储器请求之间进行仲裁的存储器控制器，并且在某些情况下，当前循环正在完成时开始下一个循环。这允许同时执行至少两个存储器请求，从而提高总线利用率并且更有效地检索和存储数据在存储器中。存储器控制器可以在当前周期内开始下一个存储器循环，当下一个存储器周期将导致页错过，并且存储体对与最近使用（MRU）页不相关联的存储体进行命中。当下一个周期将是页错误和银行丢失时，进一步的并行存储器请求执行是可能的。

10. 发明授权

US5949436A Accelerated graphics port multiple entry gart cache allocation system and method 失效
标题翻译：加速图形端口多进入gart缓存分配系统和方法
公开(公告)号：US5949436A
公开(公告)日：1999-09-07
申请号：US941861
申请日：1997-09-30
申请人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Jerome J. Johnson , Michael J. Collins
发明人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Jerome J. Johnson , Michael J. Collins
IPC分类号： G06F12/10 , G06T1/60 , G06F15/00 , G06T1/00
CPC分类号： G06T1/60 , G06F12/1027 , G06F12/1081
摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory. The core logic chipset may cache a subset of the most recently used GART table entries to increase AGP performance when performing the address translation. When a GART table entry is not found in the cache, a memory access is required to obtained the needed GART table entry. There are two GART table entries in each quadword returned in toggle mode of the cacheline of memory information returned from the memory read access. At least one quadword (two GART table entries) are stored in the cache each time a memory access is required because of a cache miss.
摘要翻译：具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）由核心逻辑芯片组使用，将AGP图形控制器使用的虚拟内存地址重新映射到驻留在计算机系统内存中的物理内存地址GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际使用不连续的块或物理系统存储器的页面来存储纹理，命令列表等。 GART表由多个条目组成，每个条目包括指向存储器中的图形数据页面的基地址的地址指针。核心逻辑芯片组可以缓存最近使用的GART表项的子集，以在执行地址转换时提高AGP性能。当缓存中没有找到GART表条目时，需要内存访问才能获取所需的GART表条目。在内存读取访问返回的内存信息的缓存行的切换模式下，每个四字中有两个GART表条目。由于缓存未命中，每次需要存储器访问时，至少有一个四字（两个GART表条目）存储在缓存中。

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