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1. 发明授权

US06272580B1 Apparatus and method for dynamically elevating a lower level bus master to an upper level bus master within a multi-level arbitration system 有权
标题翻译：一种用于在多级仲裁系统内动态地将较低级总线主机升级到上级总线主机的装置和方法
公开(公告)号：US06272580B1
公开(公告)日：2001-08-07
申请号：US09268825
申请日：1999-03-16
申请人： Jeff Stevens , Robert A. Lester , Phillip M. Jones , Jeff W. Wolford , Peter Lee
发明人： Jeff Stevens , Robert A. Lester , Phillip M. Jones , Jeff W. Wolford , Peter Lee
IPC分类号： G06F13362
CPC分类号： G06F13/362
摘要： A computer system, bus interface unit, and method are provided to allocate requests to a shared bus within the computer system. The bus interface unit includes an arbiter which employs a multi-level, round-robin arbitration protocol. Configuration registers are programmed during boot-up of the computer system by assigning a subset of peripheral devices, bus agents, requesters, or bus masters to either a high priority ring or a low priority ring, if two levels of arbitration are used. The status of a low priority device can be elevated to equal priority with a high priority device by assigning the low priority device to a high priority port within the high priority ring if certain circumstances occur. Namely, if data transfers to or from the low priority device are terminated, then the low priority device will be promoted to a high priority device so that it need not wait until after the all high priority device requests have been polled. Instead, the elevated low priority device is placed on the same level of priority as the high priority devices so that its request can be readily serviced and the transaction completed during a data transfer retry operation.
摘要翻译：提供计算机系统，总线接口单元和方法以将计算机系统中的共享总线分配请求。总线接口单元包括采用多级循环仲裁协议的仲裁器。如果使用两级仲裁，配置寄存器在计算机系统引导期间被编程，通过将外设，总线代理，请求者或总线主机的子集分配到高优先级环或低优先级环。如果发生某些情况，则可以通过将低优先级设备分配给高优先级环中的高优先级端口，将低优先级设备的状态提升为与高优先级设备相等的优先级。也就是说，如果到低优先级设备的数据传输结束，则低优先级设备将被提升为高优先级设备，使得它不需要等到所有高优先级设备请求被轮询之后。相反，升高的低优先级设备被放置在与高优先级设备相同的优先级上，使得其请求可以容易地被服务并且在数据传输重试操作期间完成事务。

2. 发明授权

US5603050A Direct memory access controller having programmable timing 失效
公开(公告)号：US5603050A
公开(公告)日：1997-02-11
申请号：US398358
申请日：1995-03-03
申请人： Jeff W. Wolford , Robert A. Lester
发明人： Jeff W. Wolford , Robert A. Lester
IPC分类号： G06F13/28 , G06F13/30 , G06F13/362 , G06F13/00
CPC分类号： G06F13/30 , G06F13/28 , G06F13/287 , G06F13/3625
摘要： An improved DMA controller having programmable data transfer timings. Not only is the total cycle time programmable, but the active and inactive period of the cycle are also programmable. An active timing register and an inactive timing register are used in conjunction with a countdown timer to determine the active and inactive periods of the data transfer cycle. The active time period is loaded into the timer during the active phase, with the end of the active phase being indicated by the timer timing out. Next, the inactive time period is loaded into the timer, which similarly times out to indicate the end of the inactive phase of the data transfer cycle.

3. 发明授权

US5596729A First arbiter coupled to a first bus receiving requests from devices coupled to a second bus and controlled by a second arbiter on said second bus 失效
标题翻译：第一仲裁器耦合到第一总线，接收来自耦合到第二总线并由所述第二总线上的第二仲裁器控制的设备的请求
公开(公告)号：US5596729A
公开(公告)日：1997-01-21
申请号：US398366
申请日：1995-03-03
申请人： Robert A. Lester , Jeff W. Wolford
发明人： Robert A. Lester , Jeff W. Wolford
IPC分类号： G06F13/36 , G06F13/00
CPC分类号： G06F13/36
摘要： An improved arbitration scheme including multiple arbiters for arbitrating access to a PCI bus and an ISA bus. The PCI arbiter controls access to the PCI bus by various bus masters, including the CPU/main memory subsystem, various other PCI bus masters, an enhanced DMA or EDMA controller, and an 8237-compatible DMA controller. The PCI arbiter utilizes a modified LRU arbitration scheme. Further, an SD arbiter exists to arbitrate access to the data portion (SD) of the ISA bus. The various devices that may request the SD bus include the EDMA controller, a PCI master in a PCI-to-ISA operation, the DMA controller, an ISA bus master, and the refresh controller. The SD arbiter assigns the highest priority to the PCI bus, followed by the refresh controller, EDMA controller, and DMA controller or ISA bus masters. The DMA controller includes an arbiter for arbitrating between its channels. The DMA arbiter further includes logic to ensure that the DMA controller or ISA bus master relinquishes control of the ISA bus after one arbitration cycle.
摘要翻译：一种改进的仲裁方案，包括用于仲裁访问PCI总线和ISA总线的多仲裁器。 PCI仲裁器控制各种总线主机访问PCI总线，包括CPU /主存储器子系统，各种其他PCI总线主机，增强型DMA或EDMA控制器以及兼容8237的DMA控制器。 PCI仲裁器利用修改的LRU仲裁方案。此外，SD仲裁器存在仲裁访问ISA总线的数据部分（SD）。可以请求SD总线的各种设备包括EDMA控制器，PCI-ISA操作中的PCI主机，DMA控制器，ISA总线主机和刷新控制器。 SD仲裁器将最高优先级分配给PCI总线，其次是刷新控制器，EDMA控制器和DMA控制器或ISA总线主机。 DMA控制器包括用于在其通道之间进行仲裁的仲裁器。 DMA仲裁器还包括确保DMA控制器或ISA总线主机在一个仲裁周期之后放弃对ISA总线的控制的逻辑。

4. 发明授权

US06249847B1 Computer system with synchronous memory arbiter that permits asynchronous memory requests 有权
标题翻译：具有允许异步存储器请求的同步存储器仲裁器的计算机系统
公开(公告)号：US06249847B1
公开(公告)日：2001-06-19
申请号：US09134057
申请日：1998-08-14
申请人： Kenneth T. Chin , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , Michael J. Collins
发明人： Kenneth T. Chin , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , Michael J. Collins
IPC分类号： G06F1378
CPC分类号： G06F13/18
摘要： A computer system that includes a CPU, a memory and a memory controller for controlling access to the memory. The memory controller generally includes arbitration logic for deciding which memory request among one or more pending requests should win arbitration. When a request wins arbitration, the arbitration logic asserts a “won” signal corresponding to that memory request. The memory controller also includes synchronizing logic to synchronize memory requests, corresponding to a first group of requests, that win arbitration to a clock signal and an arbitration enable signal. The synchronizing logic includes an AND gate and a latch for synchronizing the won signals. The memory controller also asynchronously arbitrates a second group of memory requests by asserting a won signal associated with the second group requests that is not synchronized to the clock signal. In this manner, the won signals for the second group of requests can be asserted earlier than the synchronized won signals, thereby permitting the asynchronously arbitrated second group memory requests to be performed earlier than otherwise possible.
摘要翻译：一种包括CPU，存储器和用于控制对存储器的访问的存储器控制器的计算机系统。存储器控制器通常包括仲裁逻辑，用于决定一个或多个待处理请求中哪个存储器请求应该赢得仲裁。当请求赢得仲裁时，仲裁逻辑确定与该存储器请求对应的“赢”信号。存储器控制器还包括同步逻辑，以将与第一组请求相对应的存储器请求同步到仲裁到时钟信号和仲裁使能信号。同步逻辑包括与门和用于使获胜信号同步的锁存器。存储器控制器还通过断言与不与时钟信号同步的第二组请求相关联的获胜信号来异步地仲裁第二组存储器请求。以这种方式，第二组请求的获胜信号可以早于同步的获胜信号被断言，从而允许异步仲裁的第二组存储器请求比其他可能的更早执行。

5. 发明授权

US07120758B2 Technique for improving processor performance 失效
标题翻译：提高处理器性能的技术
公开(公告)号：US07120758B2
公开(公告)日：2006-10-10
申请号：US10365018
申请日：2003-02-12
申请人： Phillip M. Jones , Robert A. Lester , Jens K. Ramsey , William J. Walker , John E. Larson , James Andre , Paul Rawlins
发明人： Phillip M. Jones , Robert A. Lester , Jens K. Ramsey , William J. Walker , John E. Larson , James Andre , Paul Rawlins
IPC分类号： G06F12/00 , G06F3/00
CPC分类号： G06F13/1673
摘要： Method and apparatus for improving processor performance. In some embodiments, processing speed may be improved by reusing data stored in a buffer during an initial request by subsequent requests. Assignment of temporary storage buffers in a controller may be made to allow for the potential for reuse of the data. Further, a hot buffer may be designated to allow for reuse of the data stored in the hot buffer. On subsequent requests, data stored in the hot buffer may be sent to a requesting device without re-retrieving the data from memory.
摘要翻译：提高处理器性能的方法和装置。在一些实施例中，可以通过在初始请求期间通过后续请求重用存储在缓冲器中的数据来改善处理速度。控制器中的临时存储缓冲区的分配可以做出以允许数据重用的潜力。此外，可以指定热缓冲器以允许重新使用存储在热缓冲器中的数据。在随后的请求中，存储在热缓冲器中的数据可以被发送到请求设备而不从存储器重新检索数据。

6. 发明授权

US06216190B1 System and method for optimally deferring or retrying a cycle upon a processor bus that is destined for a peripheral bus 有权
标题翻译：用于最佳延迟或重试一个周期的系统和方法，处理器总线上用于外设总线
公开(公告)号：US06216190B1
公开(公告)日：2001-04-10
申请号：US09164192
申请日：1998-09-30
申请人： Kenneth T. Chin , Clarence K. Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo
发明人： Kenneth T. Chin , Clarence K. Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo
IPC分类号： G06F1342
CPC分类号： G06F13/4239
摘要： A computer is provided having a bus interface unit coupled between a CPU bus, a peripheral bus, and a memory bus. The bus interface unit includes a processor controller linked to the CPU bus for controlling the transfer of cycles from the CPU to the peripheral bus and memory bus. Those cycles can be arranged in order within the CPU bus pipeline. A subset of cycles destined for a peripheral bus can be stalled within a snoop phase associated with the CPU bus. Snoop stall can continue until a memory cycle is encountered upon the CPU bus pipeline within a phase prior to the snoop phase. Once the memory cycle progresses to the snoop phase, snoop stall can be discontinued and the previous, peripheral cycles can then be deferred and/or retried, allowing the memory cycle to be quickly dispatched through all phases of the CPU bus and onto the memory bus. In this fashion, memory cycles can be completed quickly, yet deferrals or retries are minimized to avoid the throughput penalty associated with deferring or retrying cycles back again through each phase of the CPU bus.
摘要翻译：提供一种具有耦合在CPU总线，外围总线和存储器总线之间的总线接口单元的计算机。总线接口单元包括连接到CPU总线的处理器控制器，用于控制从CPU到外围总线和存储器总线的周期传送。这些循环可以顺序排列在CPU总线管道中。在与CPU总线相关联的窥探阶段中，可能会停止发往外围总线的周期的子集。在窥探阶段之前的一个阶段，在CPU总线流水线上，Snoop停止可以继续，直到遇到内存循环。一旦存储器周期进行到窥探阶段，就可以停止侦听停止，然后可以延迟和/或重试先前的周边周期，从而允许通过CPU总线的所有阶段和存储器总线快速调度存储器周期。以这种方式，可以快速完成内存周期，但是延迟或重试最小化，以避免通过CPU总线的每个阶段再次延迟或重试周期相关的吞吐量损失。

7. 发明授权

US06209052B1 System and method for suppressing processor cycles to memory until after a peripheral device write cycle is acknowledged by the memory arbiter 有权
标题翻译：在存储器仲裁器确认外围设备写入周期之后，将处理器周期抑制到存储器的系统和方法
公开(公告)号：US06209052B1
公开(公告)日：2001-03-27
申请号：US09164194
申请日：1998-09-30
申请人： Kenneth T. Chin , Clarence K. Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo
发明人： Kenneth T. Chin , Clarence K. Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo
IPC分类号： G06F1300
CPC分类号： G06F13/1605 , G06F13/4243
摘要： A computer is provided having a bus interface unit coupled between a CPU bus, a peripheral bus (i.e., PCI bus and/or graphics bus), and a memory bus. The bus interface unit includes controllers linked to the respective buses, and a plurality of queues placed within address and data paths between the various controllers. The peripheral bus controller can decode a write cycle to memory, and the processor controller can thereafter request and be granted ownership of the CPU local bus. The address of the write cycle can then be snooped to determine if valid data exists within the CPU cache storage locations. If so, a writeback operation can occur. Ownership of the CPU bus is maintained by the bus interface unit during the snooping operation, as well as during writeback and the request of the memory bus by the peripheral-derived write cycle. It is not until ownership of the memory bus is granted by the memory arbiter that mastership is terminated by the bus interface unit. Accordingly, the bus interface unit keeps CPU-derived cycles off the CPU bus to ensure memory arbiter grants ownership to a write cycle from the peripheral bus. In this fashion, data from the peripheral bus can be stored in system memory before accessing that data by a CPU read cycle. The number of snoop cycles which the bus interface unit can initiate is determined by configuration registers programmed during power on, reset or boot up of computer.
摘要翻译：提供一种计算机，其具有耦合在CPU总线，外围总线（即PCI总线和/或图形总线）之间的总线接口单元和存储器总线。总线接口单元包括链接到相应总线的控制器，以及放置在各种控制器之间的地址和数据路径内的多个队列。外设总线控制器可以将写周期解码为存储器，然后处理器控制器可以请求并授予CPU本地总线的所有权。然后可以窥探写周期的地址，以确定CPU高速缓存存储位置中是否存在有效数据。如果是这样，可以进行回写操作。 CPU总线的所有权在侦听操作期间由总线接口单元维护，以及通过外设来源的写周期在写回和存储器总线的请求期间保持。直到存储器总线的所有权由总线接口单元终止主存的存储器仲裁器才被授予。因此，总线接口单元将CPU派生的周期从CPU总线保持，以确保存储器仲裁器将所有权授予来自外设总线的写周期。以这种方式，通过CPU读取周期访问该数据之前，来自外围总线的数据可以存储在系统存储器中。总线接口单元可以启动的窥探周期数由计算机上电，复位或启动时编程的配置寄存器决定。

8. 发明授权

US06202101B1 System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom 有权
标题翻译：同时请求输入/输出和存储器地址空间的系统和方法，同时保持从其发送和返回的数据的顺序
公开(公告)号：US06202101B1
公开(公告)日：2001-03-13
申请号：US09164189
申请日：1998-09-30
申请人： Kenneth T. Chin , Clarence K. Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo
发明人： Kenneth T. Chin , Clarence K. Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo
IPC分类号： G06F1300
CPC分类号： G06F13/1621
摘要： A computer is provided having a bus interface unit coupled between a processor bus, a peripheral bus, and a memory bus. The bus interface unit includes a processor controller linked to the processor bus for controlling the transfer of cycles from the processor to the peripheral bus and memory bus. Those cycles are initially forwarded as a request, whereby the processor controller includes a memory request queue separate from a peripheral request queue. Requests from the memory and peripheral request queues can be de-queued concurrently to the memory and peripheral buses. This enhances throughput of read and write requests; however, proper ordering of data returned as a result of read requests and data transferred as a result of write requests must be ensured. An in-order queue is also present in the processor controller which records the order in which the requests are dispatched to the peripheral and memory buses from the peripheral and memory request queues. Data ensuing from the request can be re-ordered and presented to the destination based on the current pointer position within the in-order queue. Thus, the in-order queue keeps track of the order in which data is transferred across the processor bus consistent with the order in which the previous requests were transferred.
摘要翻译：提供了一种具有耦合在处理器总线，外围总线和存储器总线之间的总线接口单元的计算机。总线接口单元包括链接到处理器总线的处理器控制器，用于控制从处理器到外围总线和存储器总线的周期传送。这些周期最初作为请求转发，由此处理器控制器包括与外围设备请求队列分开的存储器请求队列。来自存储器和外围设备请求队列的请求可以同时排队到存储器和外围总线。这增强了读写请求的吞吐量; 但是，必须确保作为读请求返回的数据的正确排序和作为写请求结果传送的数据。在处理器控制器中还存在按顺序队列，该处理器控制器从周边和存储器请求队列记录请求被分派到外围设备和存储器总线的顺序。可以根据请求队列中的当前指针位置重新排序并将其显示给目的地。因此，按顺序队列跟踪数据在整个处理器总线上传输的顺序，与先前请求传送的顺序一致。

9. 发明授权

US06961800B2 Method for improving processor performance 失效
标题翻译：提高处理器性能的方法
公开(公告)号：US06961800B2
公开(公告)日：2005-11-01
申请号：US09967155
申请日：2001-09-28
申请人： Robert A. Lester , Kenneth T. Chin , Jim Blocker , John E. Larson , Phillip M. Jones , Paul B. Rawlins
发明人： Robert A. Lester , Kenneth T. Chin , Jim Blocker , John E. Larson , Phillip M. Jones , Paul B. Rawlins
IPC分类号： G06F13/00 , G06F13/16 , G06F13/36
CPC分类号： G06F13/1657
摘要： Methods for improving processor performance. Specifically, by reducing some of the latency cycles within a host controller, request processing speed can be improved. One technique for improving processing speed involves initiating a deferred reply transaction before the data is available from a memory controller. A second technique involves anticipating the need to transition from a block next request (BNR) state to a bus priority request (BPRI) state, thereby eliminating the need to wait for a request check to determine if the BPRI state must be implemented.
摘要翻译：提高处理器性能的方法。具体地，通过减少主机控制器内的一些延迟周期，可以提高请求处理速度。用于提高处理速度的一种技术涉及在从存储器控制器获得数据之前发起延迟回复事务。第二种技术涉及预期从块下一个请求（BNR）状态转换到总线优先级请求（BPRI）状态的需要，从而消除了等待请求检查以确定是否必须实现BPRI状态的需要。

10. 发明授权

US06505260B2 Computer system with adaptive memory arbitration scheme 失效
标题翻译：具有自适应内存仲裁方案的计算机系统
公开(公告)号：US06505260B2
公开(公告)日：2003-01-07
申请号：US09784690
申请日：2001-02-15
申请人： Kenneth T. Chin , C. Kevin Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , Jeffrey C. Stevens
发明人： Kenneth T. Chin , C. Kevin Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , Jeffrey C. Stevens
IPC分类号： G06F1318
CPC分类号： G06F13/1605
摘要： A computer system includes an adaptive memory arbiter for prioritizing memory access requests, including a self-adjusting, programmable request-priority ranking system. The memory arbiter adapts during every arbitration cycle, reducing the priority of any request which wins memory arbitration. Thus, a memory request initially holding a low priority ranking may gradually advance in priority until that request wins memory arbitration. Such a scheme prevents lower-priority devices from becoming “memory-starved.” Because some types of memory requests (such as refresh requests and memory reads) inherently require faster memory access than other requests (such as memory writes), the adaptive memory arbiter additionally integrates a nonadjustable priority structure into the adaptive ranking system which guarantees faster service to the most urgent requests. Also, the adaptive memory arbitration scheme introduces a flexible method of adjustable priority-weighting which permits selected devices to transact a programmable number of consecutive memory accesses without those devices losing request priority.
摘要翻译：计算机系统包括用于对存储器访问请求进行优先级的自适应存储器仲裁器，包括自调整可编程请求优先级排序系统。存储器仲裁器在每个仲裁周期内进行调整，从而降低获取内存仲裁的任何请求的优先级。因此，初始保持低优先级排序的存储器请求可以逐渐提前优先，直到该请求赢得存储器仲裁。这样的方案可防止低优先级的设备变得“记忆不足”。因为某些类型的存储器请求（例如刷新请求和存储器读取）固有地需要比其他请求（诸如存储器写入）更快的存储器访问，所以自适应存储器仲裁器另外将不可调整的优先级结构集成到自适应排名系统中，从而保证更快的服务最迫切的要求。此外，自适应存储器仲裁方案引入了可调整优先权重的灵活方法，其允许所选择的设备在没有丢失请求优先级的情况下处理可编程数量的连续存储器访问。

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