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1. 发明授权

US5854114A Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide 失效
公开(公告)号：US5854114A
公开(公告)日：1998-12-29
申请号：US947888
申请日：1997-10-09
申请人： Xiao-Yu Li , Radu Barsan , Sunil D. Mehta
发明人： Xiao-Yu Li , Radu Barsan , Sunil D. Mehta
IPC分类号： H01L21/762 , H01L21/8239 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L21/336
CPC分类号： H01L27/11517 , H01L21/76229 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11526
摘要： A shallow trench isolation structure and a method for forming the same for use with non-volatile memory devices is provided so as to maintain sufficient data retention thereof. An epitaxial layer is formed on a top surface of a semiconductor substrate. A barrier oxide layer is formed on a top surface of the epitaxial layer. A nitride layer is deposited on a top surface of the barrier oxide layer. Trenches are formed through the epitaxial layer and the barrier oxide layer to a depth greater than 4000 .ANG. below the surface of the epitaxial layer so as to create isolation regions in order to electrically isolate active regions in the epitaxial layer. A liner oxide is formed on sidewalls and bottom of the trenches to a thickness between 750 .ANG. to 1500 .ANG.. As a result, leakage current in the sidewalls are prevented due to less thinning of the liner oxide layer by subsequent fabrication process steps.

2. 发明授权

US5830795A Simplified masking process for programmable logic device manufacture 失效
标题翻译：用于可编程逻辑器件制造的简化掩蔽过程
公开(公告)号：US5830795A
公开(公告)日：1998-11-03
申请号：US664190
申请日：1996-06-10
申请人： Sunil D. Mehta , Radu Barsan
发明人： Sunil D. Mehta , Radu Barsan
IPC分类号： H01L21/8238 , H01L21/8247 , H01L27/092 , H01L21/8234
CPC分类号： H01L27/11521 , H01L21/823807 , H01L27/0922 , H01L27/11558
摘要： A process for forming CMOS transistors on a semiconductor substrate, wherein the plurality of transistors includes high-voltage N-channel and high-voltage P-channel transistors, and low-voltage N-channel and low-voltage P-channel transistors, wherein a tunnel oxide of a first thickness is required and a gate oxide of a second thickness is required is provided. The process comprises the steps of: forming a thick gate oxide on the surface of the substrate; forming a low voltage n-channel transistor mask, the mask including a plurality of windows exposing first portions of the thick gate oxide; implanting an n-type dopant into the substrate through said windows and through the thick gate oxide layer to form an n-dopant implant region; etching a first portion of the thick gate oxide exposing the surface of the substrate overlying the n-dopant implant region; stripping the low voltage n-channel mask; forming a low voltage p-channel transistor mask, the mask including a plurality of windows exposing the second portions of the thick gate oxide; implanting a p-type dopant into the substrate through said windows and through the thick gate oxide layer; etching a second portion of the thick gate oxide layer thereby exposing a first and second portions of the substrate surface; and simultaneously forming a tunnel oxide on the first exposed portion of the substrate and gate oxide on the second exposed portion of the substrate.
摘要翻译：一种用于在半导体衬底上形成CMOS晶体管的工艺，其中所述多个晶体管包括高压N沟道和高压P沟道晶体管，以及低电压N沟道和低电压P沟道晶体管，其中a 需要第一厚度的隧道氧化物，并且需要第二厚度的栅极氧化物。该方法包括以下步骤：在衬底的表面上形成厚栅极氧化物; 形成低电压n沟道晶体管掩模，所述掩模包括暴露所述厚栅极氧化物的第一部分的多个窗口; 通过所述窗口和通过厚栅氧化层将n型掺杂剂注入到衬底中以形成n掺杂剂注入区域; 蚀刻暴露覆盖在n-掺杂剂注入区域上的衬底的表面的厚栅极氧化物的第一部分; 剥离低电压n沟道掩模; 形成低电压p沟道晶体管掩模，所述掩模包括暴露所述厚栅极氧化物的第二部分的多个窗口; 通过所述窗口和通过厚栅极氧化物层将p型掺杂剂注入衬底; 蚀刻厚栅极氧化物层的第二部分，从而暴露衬底表面的第一和第二部分; 并且同时在衬底的第一暴露部分和衬底的第二暴露部分上的栅极氧化物上形成隧道氧化物。

3. 发明授权

US06071784A Annealing of silicon oxynitride and silicon nitride films to eliminate high temperature charge loss 失效
标题翻译：氮氧化硅和氮化硅膜的退火以消除高温电荷损失
公开(公告)号：US06071784A
公开(公告)日：2000-06-06
申请号：US921003
申请日：1997-08-29
申请人： Sunil D. Mehta , Radu Barsan
发明人： Sunil D. Mehta , Radu Barsan
IPC分类号： H01L21/768 , H01L21/336
CPC分类号： H01L21/76801 , H01L21/76828 , H01L21/76829 , H01L21/76834 , H01L21/76895
摘要： This invention includes a semiconductor device having a gate formed on a semiconductor substrate with a low hydrogen content etch stop or barrier layer formed over the gate, and methods for manufacturing a semiconductor device with an etch stop or barrier layer with low free hydrogen content. The semiconductor device may have a hydrogen getter layer formed between the gate and the etch stop or barrier layer. The etch stop or barrier layer is a high temperature PECVD nitride film, a high temperature PECVD oxynitride film or a high temperature LPCVD nitride film. The hydrogen getter layer is P-doped film having a thickness between about 500 .ANG. and about 2000 .ANG. and is a PSG, BPSG, PTEOS deposited oxide film, or a BPTEOS deposited oxide film. The low free hydrogen content of the etch stop layer or barrier layer is achieved by a high temperature annealing step, performed at a higher temperature than the deposition temperature of the etch stop or barrier layer. Specific uses of the etch stop or barrier layers include manufacture of electrical contacts and local interconnects.
摘要翻译：本发明包括半导体器件，其具有形成在半导体衬底上的栅极，该栅极形成在栅极上形成的低氢含量蚀刻阻挡层或阻挡层，以及用于制造具有低自由氢含量的蚀刻停止层或阻挡层的半导体器件的方法。半导体器件可以具有形成在栅极和蚀刻停止层或阻挡层之间的吸氢剂层。蚀刻停止层或阻挡层是高温PECVD氮化物膜，高温PECVD氮氧化物膜或高温LPCVD氮化物膜。吸氢剂层是厚度在约500至约2000之间的P掺杂膜，是PSG，BPSG，PTEOS沉积氧化物膜或BPTEOS沉积氧化物膜。通过高温退火步骤实现蚀刻停止层或阻挡层的低自由氢含量，其在比蚀刻停止层或阻挡层的沉积温度更高的温度下进行。蚀刻停止层或阻挡层的具体用途包括制造电触点和局部互连。

4. 发明授权

US6064105A Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide 有权
标题翻译：使用较厚的衬垫氧化物进行浅沟槽隔离的EEPROM单元的数据保留
公开(公告)号：US6064105A
公开(公告)日：2000-05-16
申请号：US134174
申请日：1998-08-14
申请人： Xiao-Yu Li , Radu Barsan , Sunil D. Mehta
发明人： Xiao-Yu Li , Radu Barsan , Sunil D. Mehta
IPC分类号： H01L21/762 , H01L21/8239 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L21/8244
CPC分类号： H01L27/11517 , H01L21/76229 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11526
摘要： A shallow trench isolation structure and a method for forming the same for use with non-volatile memory devices is provided so as to maintain sufficient data retention thereof. An epitaxial layer is formed on a top surface of a semiconductor substrate. A barrier oxide layer is formed on a top surface of the epitaxial layer. A nitride layer is deposited on a top surface of the barrier oxide layer. Trenches are formed through the epitaxial layer and the barrier oxide layer to a depth greater than 4000 .ANG. below the surface of the epitaxial layer so as to create isolation regions in order to electrically isolate active regions in the epitaxial layer. A liner oxide is formed on sidewalls and bottom of the trenches to a thickness between 750 .ANG. to 1500 .ANG.. As a result, leakage current in the sidewalls are prevented due to less thinning of the liner oxide layer by subsequent fabrication process steps.
摘要翻译：提供浅沟槽隔离结构及其与非易失性存储器件一起使用的形成方法，以便保持足够的数据保留。在半导体衬底的顶表面上形成外延层。在外延层的顶表面上形成阻挡氧化层。氮化物层沉积在阻挡氧化物层的顶表面上。沟槽通过外延层和阻挡氧化物层形成在外延层表面下方大于4000的深度，以便产生隔离区，以便电隔离外延层中的有源区。衬垫氧化物形成在沟槽的侧壁和底部上，厚度在750至1500之间。结果，由于随后的制造工艺步骤，衬垫氧化物层的薄度变小，可以防止侧壁中的漏电流。

5. 发明授权

US07078286B1 Process for fabricating a semiconductor device having electrically isolated low voltage and high voltage regions 有权
标题翻译：用于制造具有电隔离的低电压和高电压区域的半导体器件的工艺
公开(公告)号：US07078286B1
公开(公告)日：2006-07-18
申请号：US10928563
申请日：2004-08-27
申请人： Sunil D. Mehta
发明人： Sunil D. Mehta
IPC分类号： H01L21/8238 , H01L21/76
CPC分类号： H01L27/11521 , H01L21/76232 , H01L27/115 , H01L27/11558
摘要： A process for fabricating a semiconductor device having electrically isolated low voltage and high voltage substrate regions includes low voltage and high voltage trench isolation structures in which a deep portion of the high voltage isolation trench provides electrical isolation in the high voltage regions. The high voltage isolation trench structures include a shallow portion that can be simultaneously formed with the low voltage trench isolation structures. The deep portion of the high voltage isolation trench has a bottom surface and shares a continuous wall surface with the shallow portion that extends from the bottom surface to the principal surface of the substrate. A process for fabricating the device includes the formation of sidewall spacers to define a minimum isolation width between adjacent high voltage nodes.
摘要翻译：一种用于制造具有电隔离的低电压和高电压衬底区域的半导体器件的工艺包括低电压和高电压沟槽隔离结构，其中高压隔离沟槽的深部分在高电压区域中提供电隔离。高电压隔离沟槽结构包括可与低电压沟槽隔离结构同时形成的浅部分。高电压隔离沟槽的深部具有底表面并且具有从底部表面延伸到基底主表面的浅部分的连续壁表面。用于制造该器件的工艺包括形成侧壁间隔物以限定相邻高压节点之间的最小隔离宽度。

6. 发明授权

US06545313B1 EEPROM tunnel window for program injection via P+ contacted inversion 失效
标题翻译： EEPROM隧道窗口通过P +接触反转进行程序注入
公开(公告)号：US06545313B1
公开(公告)日：2003-04-08
申请号：US10211125
申请日：2002-08-02
申请人： Chun Jiang , Robert Tu , Sunil D. Mehta
发明人： Chun Jiang , Robert Tu , Sunil D. Mehta
IPC分类号： H01L29788
CPC分类号： H01L21/28273
摘要： An improved method for fabricating a tunnel oxide window for use in an EEPROM memory cell is provided so as to produce better programming endurance. A P+ implant is provided at the tunnel window edge. During the programming operation, the P+ contacted inversion layer is used instead of the program junction. As a result, there is eliminated the voltage drop in the program junction region so as to improve the efficiency of programming.
摘要翻译：提供了一种用于制造用于EEPROM存储单元的隧道氧化物窗口的改进方法，以便产生更好的编程耐久性。在隧道窗边缘提供P +植入物。在编程操作期间，使用P +接触反转层代替程序结。结果，消除了程序结区域中的电压降，从而提高编程效率。

7. 发明授权

US06472308B1 Borderless vias on bottom metal 失效
公开(公告)号：US06472308B1
公开(公告)日：2002-10-29
申请号：US09949276
申请日：2001-09-07
申请人： Sunil D. Mehta
发明人： Sunil D. Mehta
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L21/76819 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An improved manufacturing process and an improved device made by the process for forming via interconnects between metal layers in a multilevel metallization structure substantially eliminates trench formation during via overetch and exploding vias during via fill. An insulating multilayer structure comprising a conformal oxide, a spin-on layer, and an etch stop layer for the via etch locally planarizes the region adjacent to metal lines before the ILD is deposited and vias are patterned and etched. Using this process, metal borders around vias can be reduced or eliminated, thereby increasing circuit packing density.

8. 发明授权

US06214666B1 Method of forming a non-volatile memory device 失效
标题翻译：形成非易失性存储器件的方法
公开(公告)号：US06214666B1
公开(公告)日：2001-04-10
申请号：US09216051
申请日：1998-12-18
申请人： Sunil D. Mehta
发明人： Sunil D. Mehta
IPC分类号： H01L218247
CPC分类号： H01L29/66825 , G11C16/0441 , H01L29/7886 , Y10S438/983
摘要： A method for manufacturing a non-volatile EEPROM memory cell, and a memory cell structure provided by the method. The method comprises the steps of: forming a gate stack on the surface of a substrate; forming a first and a second active regions in the substrate so that the first and second active regions extend to a depth below the surface of the substrate and have a first impurity type and an impurity concentration; and implanting a pocket region of an opposite conductivity type to that of the first or second active region into the surface of the substrate adjacent to the first active region. The step of implanting a pocket region may performed by implanting substantially at an angle non-normal to the surface of the substrate.
摘要翻译：一种用于制造非易失性EEPROM存储单元的方法，以及通过该方法提供的存储单元结构。该方法包括以下步骤：在衬底的表面上形成栅叠层; 在所述衬底中形成第一和第二有源区，使得所述第一和第二有源区延伸到所述衬底的表面下方的深度并且具有第一杂质类型和杂质浓度; 以及将与所述第一或第二有源区的相反导电类型的口袋区域注入到与所述第一有源区相邻的所述衬底的表面中。注入口袋区域的步骤可以通过基本上以不垂直于基底表面的角度注入来进行。

9. 发明授权

US06208559B1 Method of operating EEPROM memory cells having transistors with thin gate oxide and reduced disturb 有权
标题翻译：操作具有具有薄栅极氧化物和减少干扰的晶体管的EEPROM存储单元的方法
公开(公告)号：US06208559B1
公开(公告)日：2001-03-27
申请号：US09441220
申请日：1999-11-15
申请人： Robert H. Tu , Sunil D. Mehta
发明人： Robert H. Tu , Sunil D. Mehta
IPC分类号： G11C1604
CPC分类号： G11C16/3427 , G11C16/0433 , G11C16/10 , H01L27/115
摘要： An improved process of programming and erasing an EEPROM memory cell in an array of identical cells uses a reduced voltage on the write transistor of the cell to be programmed or erased and at the same time applies smaller voltages across the relatively thin oxides of the write transistors of the other cells in the array so as to reduce oxide leakage and damage in those cells but without disturbing the information stored in those cells. The result is the ability to scale down the size of the EEPROM memory cell allowing enhanced economies and permitting faster program, erase and reading speeds.
摘要翻译：编程和擦除相同单元阵列中的EEPROM存储单元的改进过程使用待编程或擦除的单元写入晶体管上的降低的电压，同时在写入晶体管的相对薄的氧化物上施加较小的电压的阵列中的其他电池，以便减少这些电池中的氧化物泄漏和损坏，但是不会干扰存储在这些电池中的信息。结果是能够缩小EEPROM存储单元的尺寸，从而增强经济性，并允许更快的编程，擦除和读取速度。

10. 发明授权

US06172392B2 Boron doped silicon capacitor plate 失效
标题翻译：硼掺杂硅电容器板
公开(公告)号：US06172392B2
公开(公告)日：2001-01-09
申请号：US09280887
申请日：1999-03-29
申请人： Christopher O. Schmidt , Sunil D. Mehta , Xiao-Yu Li
发明人： Christopher O. Schmidt , Sunil D. Mehta , Xiao-Yu Li
IPC分类号： H01L29788
CPC分类号： H01L27/11558 , H01L27/115 , H01L27/11521
摘要： A nonvolatile memory device utilizing a program junction region of a p-type impurity and oxide grown thereon. In one aspect, the device comprises a programming structure and a program junction separated from said programming structure by a field oxide region. A program junction oxide layer overlies said program junction region. A floating gate is provided over the oxide which covers said programming structure, said program junction oxide layer, and in some embodiments the gate oxide of a sense transistor.
摘要翻译：一种利用p型杂质的程序结区域和在其上生长的氧化物的非易失性存储器件。一方面，该装置包括编程结构和通过场氧化物区与所述编程结构分离的程序结。程序结氧化物层覆盖所述程序结区域。在覆盖所述编程结构，所述程序结氧化物层的氧化物上提供浮置栅极，并且在一些实施例中，提供感测晶体管的栅极氧化物。

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