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1. 发明授权

US06208559B1 Method of operating EEPROM memory cells having transistors with thin gate oxide and reduced disturb 有权
标题翻译：操作具有具有薄栅极氧化物和减少干扰的晶体管的EEPROM存储单元的方法
公开(公告)号：US06208559B1
公开(公告)日：2001-03-27
申请号：US09441220
申请日：1999-11-15
申请人： Robert H. Tu , Sunil D. Mehta
发明人： Robert H. Tu , Sunil D. Mehta
IPC分类号： G11C1604
CPC分类号： G11C16/3427 , G11C16/0433 , G11C16/10 , H01L27/115
摘要： An improved process of programming and erasing an EEPROM memory cell in an array of identical cells uses a reduced voltage on the write transistor of the cell to be programmed or erased and at the same time applies smaller voltages across the relatively thin oxides of the write transistors of the other cells in the array so as to reduce oxide leakage and damage in those cells but without disturbing the information stored in those cells. The result is the ability to scale down the size of the EEPROM memory cell allowing enhanced economies and permitting faster program, erase and reading speeds.
摘要翻译：编程和擦除相同单元阵列中的EEPROM存储单元的改进过程使用待编程或擦除的单元写入晶体管上的降低的电压，同时在写入晶体管的相对薄的氧化物上施加较小的电压的阵列中的其他电池，以便减少这些电池中的氧化物泄漏和损坏，但是不会干扰存储在这些电池中的信息。结果是能够缩小EEPROM存储单元的尺寸，从而增强经济性，并允许更快的编程，擦除和读取速度。

2. 发明授权

US06309942B1 STI punch-through defects and stress reduction by high temperature oxide reflow process 有权
标题翻译： STI穿透缺陷和通过高温氧化物回流工艺的应力降低
公开(公告)号：US06309942B1
公开(公告)日：2001-10-30
申请号：US09245161
申请日：1999-02-04
申请人： Ting Y. Tsui , Robert H. Tu , Xiao-Yu Li , Sunil D. Mehta
发明人： Ting Y. Tsui , Robert H. Tu , Xiao-Yu Li , Sunil D. Mehta
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： A method of manufacturing a semiconductor device with reduced shallow trench isolation defects and stress is disclosed. The disclosed method begins by providing a silicon substrate including a capping layer. A plurality of isolation trenches are then etched through the capping layer and into the silicon substrate to form a plurality of isolation regions in the silicon substrate. The isolation trenches are then filled with an oxide layer. The oxide layer and the capping layer are then polished back using techniques known in the art. After polishing, the semiconductor device is annealed between a temperature range of about 1150° C. to about 1200° C.
摘要翻译：公开了一种制造具有减小的浅沟槽隔离缺陷和应力的半导体器件的方法。所公开的方法开始于提供包括封盖层的硅衬底。然后通过覆盖层蚀刻多个隔离沟槽并进入硅衬底，以在硅衬底中形成多个隔离区域。然后用氧化物层填充隔离沟槽。然后使用本领域已知的技术将氧化物层和覆盖层进行抛光。在抛光之后，半导体器件在约1150℃至约1200℃的温度范围内退火

3. 发明授权

US06291327B1 Optimization of S/D annealing to minimize S/D shorts in memory array 失效
标题翻译：优化S / D退火以最小化存储器阵列中的S / D短路
公开(公告)号：US06291327B1
公开(公告)日：2001-09-18
申请号：US09192094
申请日：1998-11-13
申请人： Xiao-Yu Li , Sunil D. Mehta , Christopher O. Schmidt , Robert H. Tu
发明人： Xiao-Yu Li , Sunil D. Mehta , Christopher O. Schmidt , Robert H. Tu
IPC分类号： H01L21336
CPC分类号： H01L21/76237 , H01L21/823418 , H01L21/823462 , H01L27/1052
摘要： A method for eliminating source/drain shorting generated during the highly-doped source/drain implant steps in a standard STI process is provided. This is achieved by reducing the RTA temperature to be less than 1000° C. so as to minimize enhanced doping diffusion. Further, the energy level for the highly-doped source/drain implant steps is increased so to compensate for poly depletion in the gate electrodes.
摘要翻译：提供了一种用于消除在标准STI工艺中的高掺杂源极/漏极注入步骤期间产生的源极/漏极短路的方法。这是通过将RTA温度降低至小于1000℃来实现的，以便使增强的掺杂扩散最小化。此外，高掺杂源极/漏极注入步骤的能级增加，以补偿栅电极中的多晶硅耗尽。

4. 发明授权

US06221733B1 Reduction of mechanical stress in shallow trench isolation process 有权
标题翻译：浅沟槽隔离过程中机械应力的降低
公开(公告)号：US06221733B1
公开(公告)日：2001-04-24
申请号：US09192096
申请日：1998-11-13
申请人： Xiao-Yu Li , Sunil D. Mehta , Robert H. Tu
发明人： Xiao-Yu Li , Sunil D. Mehta , Robert H. Tu
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , Y10S148/05
摘要： A method of minimizing mechanical stress generated during the trench-forming/trench-filling process steps in a standard shallow trench isolation (STI) process is provided. This is achieved by forming trenches with a more sloped and smoother profile, and/or limiting the trench depth to be less than 0.4 &mgr;m, and/or reducing or increasing the trench densification temperature, and/or performing the densification step after the chemical-mechanical polishing step. In addition, a furnace TEOS oxide film is used as the trench-filling material.
摘要翻译：提供了一种使标准浅沟槽隔离（STI）工艺中的沟槽形成/沟槽填充工艺步骤期间产生的机械应力最小化的方法。这是通过形成具有更倾斜和更平滑轮廓的沟槽和/或限制沟槽深度小于0.4μm，和/或减小或增加沟槽致密化温度，和/或在化学处理之后执行致密化步骤来实现的，机械抛光步骤。此外，使用炉TEOS氧化物膜作为沟槽填充材料。

5. 发明授权

US07078286B1 Process for fabricating a semiconductor device having electrically isolated low voltage and high voltage regions 有权
标题翻译：用于制造具有电隔离的低电压和高电压区域的半导体器件的工艺
公开(公告)号：US07078286B1
公开(公告)日：2006-07-18
申请号：US10928563
申请日：2004-08-27
申请人： Sunil D. Mehta
发明人： Sunil D. Mehta
IPC分类号： H01L21/8238 , H01L21/76
CPC分类号： H01L27/11521 , H01L21/76232 , H01L27/115 , H01L27/11558
摘要： A process for fabricating a semiconductor device having electrically isolated low voltage and high voltage substrate regions includes low voltage and high voltage trench isolation structures in which a deep portion of the high voltage isolation trench provides electrical isolation in the high voltage regions. The high voltage isolation trench structures include a shallow portion that can be simultaneously formed with the low voltage trench isolation structures. The deep portion of the high voltage isolation trench has a bottom surface and shares a continuous wall surface with the shallow portion that extends from the bottom surface to the principal surface of the substrate. A process for fabricating the device includes the formation of sidewall spacers to define a minimum isolation width between adjacent high voltage nodes.
摘要翻译：一种用于制造具有电隔离的低电压和高电压衬底区域的半导体器件的工艺包括低电压和高电压沟槽隔离结构，其中高压隔离沟槽的深部分在高电压区域中提供电隔离。高电压隔离沟槽结构包括可与低电压沟槽隔离结构同时形成的浅部分。高电压隔离沟槽的深部具有底表面并且具有从底部表面延伸到基底主表面的浅部分的连续壁表面。用于制造该器件的工艺包括形成侧壁间隔物以限定相邻高压节点之间的最小隔离宽度。

6. 发明授权

US06545313B1 EEPROM tunnel window for program injection via P+ contacted inversion 失效
标题翻译： EEPROM隧道窗口通过P +接触反转进行程序注入
公开(公告)号：US06545313B1
公开(公告)日：2003-04-08
申请号：US10211125
申请日：2002-08-02
申请人： Chun Jiang , Robert Tu , Sunil D. Mehta
发明人： Chun Jiang , Robert Tu , Sunil D. Mehta
IPC分类号： H01L29788
CPC分类号： H01L21/28273
摘要： An improved method for fabricating a tunnel oxide window for use in an EEPROM memory cell is provided so as to produce better programming endurance. A P+ implant is provided at the tunnel window edge. During the programming operation, the P+ contacted inversion layer is used instead of the program junction. As a result, there is eliminated the voltage drop in the program junction region so as to improve the efficiency of programming.
摘要翻译：提供了一种用于制造用于EEPROM存储单元的隧道氧化物窗口的改进方法，以便产生更好的编程耐久性。在隧道窗边缘提供P +植入物。在编程操作期间，使用P +接触反转层代替程序结。结果，消除了程序结区域中的电压降，从而提高编程效率。

7. 发明授权

US06472308B1 Borderless vias on bottom metal 失效
公开(公告)号：US06472308B1
公开(公告)日：2002-10-29
申请号：US09949276
申请日：2001-09-07
申请人： Sunil D. Mehta
发明人： Sunil D. Mehta
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L21/76819 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An improved manufacturing process and an improved device made by the process for forming via interconnects between metal layers in a multilevel metallization structure substantially eliminates trench formation during via overetch and exploding vias during via fill. An insulating multilayer structure comprising a conformal oxide, a spin-on layer, and an etch stop layer for the via etch locally planarizes the region adjacent to metal lines before the ILD is deposited and vias are patterned and etched. Using this process, metal borders around vias can be reduced or eliminated, thereby increasing circuit packing density.

8. 发明授权

US06214666B1 Method of forming a non-volatile memory device 失效
标题翻译：形成非易失性存储器件的方法
公开(公告)号：US06214666B1
公开(公告)日：2001-04-10
申请号：US09216051
申请日：1998-12-18
申请人： Sunil D. Mehta
发明人： Sunil D. Mehta
IPC分类号： H01L218247
CPC分类号： H01L29/66825 , G11C16/0441 , H01L29/7886 , Y10S438/983
摘要： A method for manufacturing a non-volatile EEPROM memory cell, and a memory cell structure provided by the method. The method comprises the steps of: forming a gate stack on the surface of a substrate; forming a first and a second active regions in the substrate so that the first and second active regions extend to a depth below the surface of the substrate and have a first impurity type and an impurity concentration; and implanting a pocket region of an opposite conductivity type to that of the first or second active region into the surface of the substrate adjacent to the first active region. The step of implanting a pocket region may performed by implanting substantially at an angle non-normal to the surface of the substrate.
摘要翻译：一种用于制造非易失性EEPROM存储单元的方法，以及通过该方法提供的存储单元结构。该方法包括以下步骤：在衬底的表面上形成栅叠层; 在所述衬底中形成第一和第二有源区，使得所述第一和第二有源区延伸到所述衬底的表面下方的深度并且具有第一杂质类型和杂质浓度; 以及将与所述第一或第二有源区的相反导电类型的口袋区域注入到与所述第一有源区相邻的所述衬底的表面中。注入口袋区域的步骤可以通过基本上以不垂直于基底表面的角度注入来进行。

9. 发明授权

US06172392B2 Boron doped silicon capacitor plate 失效
标题翻译：硼掺杂硅电容器板
公开(公告)号：US06172392B2
公开(公告)日：2001-01-09
申请号：US09280887
申请日：1999-03-29
申请人： Christopher O. Schmidt , Sunil D. Mehta , Xiao-Yu Li
发明人： Christopher O. Schmidt , Sunil D. Mehta , Xiao-Yu Li
IPC分类号： H01L29788
CPC分类号： H01L27/11558 , H01L27/115 , H01L27/11521
摘要： A nonvolatile memory device utilizing a program junction region of a p-type impurity and oxide grown thereon. In one aspect, the device comprises a programming structure and a program junction separated from said programming structure by a field oxide region. A program junction oxide layer overlies said program junction region. A floating gate is provided over the oxide which covers said programming structure, said program junction oxide layer, and in some embodiments the gate oxide of a sense transistor.
摘要翻译：一种利用p型杂质的程序结区域和在其上生长的氧化物的非易失性存储器件。一方面，该装置包括编程结构和通过场氧化物区与所述编程结构分离的程序结。程序结氧化物层覆盖所述程序结区域。在覆盖所述编程结构，所述程序结氧化物层的氧化物上提供浮置栅极，并且在一些实施例中，提供感测晶体管的栅极氧化物。

10. 发明授权

US6087275A Reduction of n-channel parasitic transistor leakage by using low power/low pressure phosphosilicate glass 失效
标题翻译：通过使用低功率/低压磷硅玻璃减少n沟道寄生晶体管泄漏
公开(公告)号：US6087275A
公开(公告)日：2000-07-11
申请号：US843150
申请日：1997-04-26
申请人： Minh Van Ngo , Sunil D. Mehta , Nicholas R. MacCrae
发明人： Minh Van Ngo , Sunil D. Mehta , Nicholas R. MacCrae
IPC分类号： H01L21/316 , H01L21/762 , H01L21/768 , H01L21/8234 , H01L21/31
CPC分类号： H01L21/02129 , H01L21/02164 , H01L21/022 , H01L21/02274 , H01L21/31625 , H01L21/76202 , H01L21/76895 , H01L21/823481
摘要： A method of manufacturing a semiconductor device with increasing threshold voltage for parasitic transistor by forming a low power-low pressure phosphosilicate glass layer on the active regions and the field oxide regions.
摘要翻译：一种通过在有源区域和场氧化物区域上形成低功率 - 低压磷硅玻璃层来制造用于寄生晶体管的阈值电压增加的半导体器件的方法。

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