专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5854114A Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide 失效
公开(公告)号：US5854114A
公开(公告)日：1998-12-29
申请号：US947888
申请日：1997-10-09
申请人： Xiao-Yu Li , Radu Barsan , Sunil D. Mehta
发明人： Xiao-Yu Li , Radu Barsan , Sunil D. Mehta
IPC分类号： H01L21/762 , H01L21/8239 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L21/336
CPC分类号： H01L27/11517 , H01L21/76229 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11526
摘要： A shallow trench isolation structure and a method for forming the same for use with non-volatile memory devices is provided so as to maintain sufficient data retention thereof. An epitaxial layer is formed on a top surface of a semiconductor substrate. A barrier oxide layer is formed on a top surface of the epitaxial layer. A nitride layer is deposited on a top surface of the barrier oxide layer. Trenches are formed through the epitaxial layer and the barrier oxide layer to a depth greater than 4000 .ANG. below the surface of the epitaxial layer so as to create isolation regions in order to electrically isolate active regions in the epitaxial layer. A liner oxide is formed on sidewalls and bottom of the trenches to a thickness between 750 .ANG. to 1500 .ANG.. As a result, leakage current in the sidewalls are prevented due to less thinning of the liner oxide layer by subsequent fabrication process steps.

2. 发明授权

US6064105A Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide 有权
标题翻译：使用较厚的衬垫氧化物进行浅沟槽隔离的EEPROM单元的数据保留
公开(公告)号：US6064105A
公开(公告)日：2000-05-16
申请号：US134174
申请日：1998-08-14
申请人： Xiao-Yu Li , Radu Barsan , Sunil D. Mehta
发明人： Xiao-Yu Li , Radu Barsan , Sunil D. Mehta
IPC分类号： H01L21/762 , H01L21/8239 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L21/8244
CPC分类号： H01L27/11517 , H01L21/76229 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11526
摘要： A shallow trench isolation structure and a method for forming the same for use with non-volatile memory devices is provided so as to maintain sufficient data retention thereof. An epitaxial layer is formed on a top surface of a semiconductor substrate. A barrier oxide layer is formed on a top surface of the epitaxial layer. A nitride layer is deposited on a top surface of the barrier oxide layer. Trenches are formed through the epitaxial layer and the barrier oxide layer to a depth greater than 4000 .ANG. below the surface of the epitaxial layer so as to create isolation regions in order to electrically isolate active regions in the epitaxial layer. A liner oxide is formed on sidewalls and bottom of the trenches to a thickness between 750 .ANG. to 1500 .ANG.. As a result, leakage current in the sidewalls are prevented due to less thinning of the liner oxide layer by subsequent fabrication process steps.
摘要翻译：提供浅沟槽隔离结构及其与非易失性存储器件一起使用的形成方法，以便保持足够的数据保留。在半导体衬底的顶表面上形成外延层。在外延层的顶表面上形成阻挡氧化层。氮化物层沉积在阻挡氧化物层的顶表面上。沟槽通过外延层和阻挡氧化物层形成在外延层表面下方大于4000的深度，以便产生隔离区，以便电隔离外延层中的有源区。衬垫氧化物形成在沟槽的侧壁和底部上，厚度在750至1500之间。结果，由于随后的制造工艺步骤，衬垫氧化物层的薄度变小，可以防止侧壁中的漏电流。

3. 发明授权

US5830795A Simplified masking process for programmable logic device manufacture 失效
标题翻译：用于可编程逻辑器件制造的简化掩蔽过程
公开(公告)号：US5830795A
公开(公告)日：1998-11-03
申请号：US664190
申请日：1996-06-10
申请人： Sunil D. Mehta , Radu Barsan
发明人： Sunil D. Mehta , Radu Barsan
IPC分类号： H01L21/8238 , H01L21/8247 , H01L27/092 , H01L21/8234
CPC分类号： H01L27/11521 , H01L21/823807 , H01L27/0922 , H01L27/11558
摘要： A process for forming CMOS transistors on a semiconductor substrate, wherein the plurality of transistors includes high-voltage N-channel and high-voltage P-channel transistors, and low-voltage N-channel and low-voltage P-channel transistors, wherein a tunnel oxide of a first thickness is required and a gate oxide of a second thickness is required is provided. The process comprises the steps of: forming a thick gate oxide on the surface of the substrate; forming a low voltage n-channel transistor mask, the mask including a plurality of windows exposing first portions of the thick gate oxide; implanting an n-type dopant into the substrate through said windows and through the thick gate oxide layer to form an n-dopant implant region; etching a first portion of the thick gate oxide exposing the surface of the substrate overlying the n-dopant implant region; stripping the low voltage n-channel mask; forming a low voltage p-channel transistor mask, the mask including a plurality of windows exposing the second portions of the thick gate oxide; implanting a p-type dopant into the substrate through said windows and through the thick gate oxide layer; etching a second portion of the thick gate oxide layer thereby exposing a first and second portions of the substrate surface; and simultaneously forming a tunnel oxide on the first exposed portion of the substrate and gate oxide on the second exposed portion of the substrate.
摘要翻译：一种用于在半导体衬底上形成CMOS晶体管的工艺，其中所述多个晶体管包括高压N沟道和高压P沟道晶体管，以及低电压N沟道和低电压P沟道晶体管，其中a 需要第一厚度的隧道氧化物，并且需要第二厚度的栅极氧化物。该方法包括以下步骤：在衬底的表面上形成厚栅极氧化物; 形成低电压n沟道晶体管掩模，所述掩模包括暴露所述厚栅极氧化物的第一部分的多个窗口; 通过所述窗口和通过厚栅氧化层将n型掺杂剂注入到衬底中以形成n掺杂剂注入区域; 蚀刻暴露覆盖在n-掺杂剂注入区域上的衬底的表面的厚栅极氧化物的第一部分; 剥离低电压n沟道掩模; 形成低电压p沟道晶体管掩模，所述掩模包括暴露所述厚栅极氧化物的第二部分的多个窗口; 通过所述窗口和通过厚栅极氧化物层将p型掺杂剂注入衬底; 蚀刻厚栅极氧化物层的第二部分，从而暴露衬底表面的第一和第二部分; 并且同时在衬底的第一暴露部分和衬底的第二暴露部分上的栅极氧化物上形成隧道氧化物。

4. 发明授权

US06071784A Annealing of silicon oxynitride and silicon nitride films to eliminate high temperature charge loss 失效
标题翻译：氮氧化硅和氮化硅膜的退火以消除高温电荷损失
公开(公告)号：US06071784A
公开(公告)日：2000-06-06
申请号：US921003
申请日：1997-08-29
申请人： Sunil D. Mehta , Radu Barsan
发明人： Sunil D. Mehta , Radu Barsan
IPC分类号： H01L21/768 , H01L21/336
CPC分类号： H01L21/76801 , H01L21/76828 , H01L21/76829 , H01L21/76834 , H01L21/76895
摘要： This invention includes a semiconductor device having a gate formed on a semiconductor substrate with a low hydrogen content etch stop or barrier layer formed over the gate, and methods for manufacturing a semiconductor device with an etch stop or barrier layer with low free hydrogen content. The semiconductor device may have a hydrogen getter layer formed between the gate and the etch stop or barrier layer. The etch stop or barrier layer is a high temperature PECVD nitride film, a high temperature PECVD oxynitride film or a high temperature LPCVD nitride film. The hydrogen getter layer is P-doped film having a thickness between about 500 .ANG. and about 2000 .ANG. and is a PSG, BPSG, PTEOS deposited oxide film, or a BPTEOS deposited oxide film. The low free hydrogen content of the etch stop layer or barrier layer is achieved by a high temperature annealing step, performed at a higher temperature than the deposition temperature of the etch stop or barrier layer. Specific uses of the etch stop or barrier layers include manufacture of electrical contacts and local interconnects.
摘要翻译：本发明包括半导体器件，其具有形成在半导体衬底上的栅极，该栅极形成在栅极上形成的低氢含量蚀刻阻挡层或阻挡层，以及用于制造具有低自由氢含量的蚀刻停止层或阻挡层的半导体器件的方法。半导体器件可以具有形成在栅极和蚀刻停止层或阻挡层之间的吸氢剂层。蚀刻停止层或阻挡层是高温PECVD氮化物膜，高温PECVD氮氧化物膜或高温LPCVD氮化物膜。吸氢剂层是厚度在约500至约2000之间的P掺杂膜，是PSG，BPSG，PTEOS沉积氧化物膜或BPTEOS沉积氧化物膜。通过高温退火步骤实现蚀刻停止层或阻挡层的低自由氢含量，其在比蚀刻停止层或阻挡层的沉积温度更高的温度下进行。蚀刻停止层或阻挡层的具体用途包括制造电触点和局部互连。

5. 发明授权

US06172392B2 Boron doped silicon capacitor plate 失效
标题翻译：硼掺杂硅电容器板
公开(公告)号：US06172392B2
公开(公告)日：2001-01-09
申请号：US09280887
申请日：1999-03-29
申请人： Christopher O. Schmidt , Sunil D. Mehta , Xiao-Yu Li
发明人： Christopher O. Schmidt , Sunil D. Mehta , Xiao-Yu Li
IPC分类号： H01L29788
CPC分类号： H01L27/11558 , H01L27/115 , H01L27/11521
摘要： A nonvolatile memory device utilizing a program junction region of a p-type impurity and oxide grown thereon. In one aspect, the device comprises a programming structure and a program junction separated from said programming structure by a field oxide region. A program junction oxide layer overlies said program junction region. A floating gate is provided over the oxide which covers said programming structure, said program junction oxide layer, and in some embodiments the gate oxide of a sense transistor.
摘要翻译：一种利用p型杂质的程序结区域和在其上生长的氧化物的非易失性存储器件。一方面，该装置包括编程结构和通过场氧化物区与所述编程结构分离的程序结。程序结氧化物层覆盖所述程序结区域。在覆盖所述编程结构，所述程序结氧化物层的氧化物上提供浮置栅极，并且在一些实施例中，提供感测晶体管的栅极氧化物。

6. 发明授权

US6075293A Semiconductor device having a multi-layer metal interconnect structure 有权
标题翻译：具有多层金属互连结构的半导体器件
公开(公告)号：US6075293A
公开(公告)日：2000-06-13
申请号：US263412
申请日：1999-03-05
申请人： Xiao-Yu Li , Sunil D. Mehta , Van H. Pham , Amit P. Marathe
发明人： Xiao-Yu Li , Sunil D. Mehta , Van H. Pham , Amit P. Marathe
IPC分类号： H01L23/532 , H01L23/48
CPC分类号： H01L23/53223 , H01L2924/0002
摘要： A multi-level metal interconnect structure in a semiconductor device includes a plurality of overlying metal layers separated by ILD layers and electrically connected by filled vias in the ILD layers. Each metal layer includes a relatively thick antireflective layer for improved electromigration resistance. Each metal layer also includes a metal lining layer and a metal interconnect layer overlying the metal lining layer. Enhanced electromigration resistance is obtained by forming the antireflective layer to a thickness of no less than the thickness of the metal lining layer. In a preferred embodiment of the invention, the antireflective layer has a thickness of about 1000 angstroms.
摘要翻译：半导体器件中的多级金属互连结构包括由ILD层分离并由ILD层中的填充通孔电连接的多个上覆金属层。每个金属层包括相对较厚的抗反射层，用于改善电迁移阻力。每个金属层还包括覆盖金属衬里层的金属衬里层和金属互连层。通过将抗反射层形成为不小于金属衬里层的厚度的厚度来获得增强的电迁移电阻。在本发明的优选实施例中，抗反射层的厚度为约1000埃。

7. 发明授权

US06309942B1 STI punch-through defects and stress reduction by high temperature oxide reflow process 有权
标题翻译： STI穿透缺陷和通过高温氧化物回流工艺的应力降低
公开(公告)号：US06309942B1
公开(公告)日：2001-10-30
申请号：US09245161
申请日：1999-02-04
申请人： Ting Y. Tsui , Robert H. Tu , Xiao-Yu Li , Sunil D. Mehta
发明人： Ting Y. Tsui , Robert H. Tu , Xiao-Yu Li , Sunil D. Mehta
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： A method of manufacturing a semiconductor device with reduced shallow trench isolation defects and stress is disclosed. The disclosed method begins by providing a silicon substrate including a capping layer. A plurality of isolation trenches are then etched through the capping layer and into the silicon substrate to form a plurality of isolation regions in the silicon substrate. The isolation trenches are then filled with an oxide layer. The oxide layer and the capping layer are then polished back using techniques known in the art. After polishing, the semiconductor device is annealed between a temperature range of about 1150° C. to about 1200° C.
摘要翻译：公开了一种制造具有减小的浅沟槽隔离缺陷和应力的半导体器件的方法。所公开的方法开始于提供包括封盖层的硅衬底。然后通过覆盖层蚀刻多个隔离沟槽并进入硅衬底，以在硅衬底中形成多个隔离区域。然后用氧化物层填充隔离沟槽。然后使用本领域已知的技术将氧化物层和覆盖层进行抛光。在抛光之后，半导体器件在约1150℃至约1200℃的温度范围内退火

8. 发明授权

US06261944B1 Method for forming a semiconductor device having high reliability passivation overlying a multi-level interconnect 有权
标题翻译：用于形成具有高可靠性钝化的半导体器件的方法，覆盖多层互连
公开(公告)号：US06261944B1
公开(公告)日：2001-07-17
申请号：US09200395
申请日：1998-11-24
申请人： Sunil D. Mehta , Xiao-Yu Li
发明人： Sunil D. Mehta , Xiao-Yu Li
IPC分类号： H01L214763
CPC分类号： H01L21/316 , H01L21/76819 , H01L21/76825 , H01L23/3192 , H01L24/48 , H01L2224/05599 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/85399 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099 , H01L2924/00012
摘要： A semiconductor device having a high reliability passivation includes a planarization layer overlying a multi-level interconnect layer. The passivation layer has a planar surface upon which additional passivation layers are formed. Openings in the overlying passivation layers and the planarization layer expose bonding pads in the multi-level interconnect layer. In a process for fabricating the device, the planarization layer is preferably formed by dispensing a siloxane spin-on-glass (SOG) material onto the surface of the multi-level interconnect layer. The SOG is subsequently planarized to form a substantially planar surface.
摘要翻译：具有高可靠性钝化的半导体器件包括覆盖多层互连层的平坦化层。钝化层具有平坦表面，在其上形成附加的钝化层。上覆钝化层和平坦化层中的开口暴露多层互连层中的焊盘。在制造该器件的过程中，平坦化层优选通过将硅氧烷旋涂玻璃（SOG）材料分配到多层互连层的表面上而形成。 SOG随后被平坦化以形成基本平坦的表面。

9. 发明授权

US06207989B1 Non-volatile memory device having a high-reliability composite insulation layer 失效
标题翻译：具有高可靠性复合绝缘层的非易失性存储器件
公开(公告)号：US06207989B1
公开(公告)日：2001-03-27
申请号：US09268897
申请日：1999-03-16
申请人： Xiao-Yu Li , Sunil D. Mehta
发明人： Xiao-Yu Li , Sunil D. Mehta
IPC分类号： H01L2976
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11558
摘要： A non-volatile memory device includes a floating-gate electrode overlying a tunnel oxide layer. A portion of the floating-gate electrode forms the control gate electrode for a sense transistor that is used to determine the presence of charge on the floating-gate electrode. A composite insulation layer overlies the floating-gate electrode. The composite insulation layer includes a dielectric layer, a doped insulating layer overlying the dielectric layer, and a planarization layer overlying the doped insulating layer. The thicknesses of the dielectric layer and the doped insulating layer are precisely determined, such that the doped insulating layer getters mobile ions, such as hydrogen ions, away from the floating-gate electrode, while not capacitively coupling with the floating-gate electrode. In a preferred embodiment of the invention, the dielectric layer has a thickness of about 450 to about 550 Å, and the doped insulating layer has a thickness of about 2900 to about 3100 Å, and the planarization layer has a thickness of about 6000 to 8000 Å.
摘要翻译：非易失性存储器件包括覆盖隧道氧化物层的浮栅电极。浮栅电极的一部分形成用于确定浮栅电极上电荷存在的读出晶体管的控制栅电极。复合绝缘层覆盖浮栅电极。复合绝缘层包括电介质层，覆盖电介质层的掺杂绝缘层和覆盖掺杂绝缘层的平坦化层。电介质层和掺杂绝缘层的厚度被精确地确定，使得掺杂的绝缘层在不与浮栅电极电容耦合的同时将诸如氢离子的移动离子吸引到浮栅电极。在本发明的优选实施例中，电介质层的厚度为约450至约550，掺杂绝缘层的厚度为约2900至约3100，平坦化层的厚度为约6000至8000 一个。

10. 发明授权

US6040019A Method of selectively annealing damaged doped regions 失效
标题翻译：选择性退火损伤掺杂区域的方法
公开(公告)号：US6040019A
公开(公告)日：2000-03-21
申请号：US799230
申请日：1997-02-14
申请人： Emi Ishida , Xiao-Yu Li , Sunil D. Mehta
发明人： Emi Ishida , Xiao-Yu Li , Sunil D. Mehta
IPC分类号： H01L21/265 , H01L21/268 , H01L21/8247 , C23C14/00 , B05D3/06 , H01L21/263
CPC分类号： H01L27/11521 , H01L21/26506 , H01L21/26513 , H01L21/268 , H01L27/11558
摘要： A method of forming a region of impurity in a semiconductor substrate with minimal damage. The method includes the steps of: forming a reaction-inhibiting impurity region in the semiconductor substrate to a depth below the semiconductor substrate; and applying laser energy to the semiconductor substrate at a sufficient magnitude to liquify the semiconductor substrate in the region.
摘要翻译：一种以最小的损伤在半导体衬底中形成杂质区域的方法。该方法包括以下步骤：在半导体衬底的深度下方形成反应抑制杂质区; 以及将激光能量以足够大的量施加到所述半导体衬底以在所述区域中液化所述半导体衬底。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式