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1. 发明申请

US20110031627A1 Reducing Crosstalk In The Design Of Module Nets 有权
标题翻译：在模块网的设计中减少串扰
公开(公告)号：US20110031627A1
公开(公告)日：2011-02-10
申请号：US12537767
申请日：2009-08-07
申请人： Dulce M. Altabella Cabrera , Sungjun Chun , Anand Haridass , Tingdong Zhou
发明人： Dulce M. Altabella Cabrera , Sungjun Chun , Anand Haridass , Tingdong Zhou
IPC分类号： G06F17/50 , H01L23/52
CPC分类号： H01L23/5386 , G06F17/5077 , G06F2217/82 , H01L23/5222 , H01L23/552 , H01L25/0655 , H01L2224/16227 , H01L2224/16235 , H01L2924/15192
摘要： A method, a system and a computer program product for reducing coupling noise in low loss on-module wires used for connecting module components in electrical circuits/devices. During the design stage, an Enhanced Crosstalk Reduction (ECR) utility identifies interconnect wires as driven/aggressor traces or receiver traces. The ECR utility substantially avoids forward crosstalk in a victim trace by specially arranging driver traces adjacent to the receiver victim trace in order to provide a lower level and saturated level of backward crosstalk. In particular, the ECR utility provided a configuration of wire/trace layers based on one or more of: (a) the crosstalk impact of a trace when positioned in a particular location; (b) the crosstalk impact of the trace upon remaining components based on placement in the particular location; and (c) system component specifications. In addition, the ECR utility reduces crosstalk by providing a configuration of receiver wires and transmitter wires without the use of isolation layers.
摘要翻译：一种用于减少用于连接电路/设备中的模块部件的低损耗模块电线中的耦合噪声的方法，系统和计算机程序产品。在设计阶段，增强型串扰降低（ECR）实用程序将互连导线识别为驱动/侵入轨迹或接收器迹线。 ECR实用程序通过专门布置与接收器受害者跟踪相邻的驱动器迹线，基本上避免了受害者跟踪中的前向串扰，以便提供较低级别和饱和的后向串扰水平。特别地，ECR实用程序基于以下中的一个或多个提供了线/迹线层的配置：（a）当定位在特定位置时迹线的串扰影响; （b）基于在特定位置的放置，迹线对剩余部件的串扰影响; 和（c）系统组件规格。此外，ECR实用程序通过提供接收器线和发射器线的配置来减少串扰，而不使用隔离层。

2. 发明授权

US08407644B2 Reducing crosstalk in the design of module nets 有权
标题翻译：减少模块网设计中的串扰
公开(公告)号：US08407644B2
公开(公告)日：2013-03-26
申请号：US12537767
申请日：2009-08-07
申请人： Dulce M. Altabella Cabrera , Sungjun Chun , Anand Haridass , Tingdong Zhou
发明人： Dulce M. Altabella Cabrera , Sungjun Chun , Anand Haridass , Tingdong Zhou
IPC分类号： G06F17/50
CPC分类号： H01L23/5386 , G06F17/5077 , G06F2217/82 , H01L23/5222 , H01L23/552 , H01L25/0655 , H01L2224/16227 , H01L2224/16235 , H01L2924/15192
摘要： A method, a system and a computer program product for reducing coupling noise in low loss on-module wires used for connecting module components in electrical circuits/devices. During the design stage, an Enhanced Crosstalk Reduction (ECR) utility identifies interconnect wires as driven/aggressor traces or receiver traces. The ECR utility substantially avoids forward crosstalk in a victim trace by specially arranging driver traces adjacent to the receiver victim trace in order to provide a lower level and saturated level of backward crosstalk. In particular, the ECR utility provided a configuration of wire/trace layers based on one or more of: (a) the crosstalk impact of a trace when positioned in a particular location; (b) the crosstalk impact of the trace upon remaining components based on placement in the particular location; and (c) system component specifications. In addition, the ECR utility reduces crosstalk by providing a configuration of receiver wires and transmitter wires without the use of isolation layers.
摘要翻译：一种用于减少用于连接电路/设备中的模块部件的低损耗模块电线中的耦合噪声的方法，系统和计算机程序产品。在设计阶段，增强型串扰降低（ECR）实用程序将互连导线识别为驱动/侵入轨迹或接收器迹线。 ECR实用程序通过专门布置与接收器受害者跟踪相邻的驱动器迹线，基本上避免了受害者跟踪中的前向串扰，以便提供较低级别和饱和的后向串扰水平。特别地，ECR实用程序基于以下中的一个或多个提供了线/迹线层的配置：（a）当定位在特定位置时迹线的串扰影响; （b）基于在特定位置的放置，迹线对剩余部件的串扰影响; 和（c）系统组件规格。此外，ECR实用程序通过提供接收器线和发射器线的配置来减少串扰，而不使用隔离层。

3. 发明申请

US20120081859A1 ELECTRONIC MODULE POWER SUPPLY 失效
标题翻译：电子模块电源
公开(公告)号：US20120081859A1
公开(公告)日：2012-04-05
申请号：US12895623
申请日：2010-09-30
申请人： Michael A. Christo , Julio A. Maldonado , Roger D. Weekly , Tingdong Zhou
发明人： Michael A. Christo , Julio A. Maldonado , Roger D. Weekly , Tingdong Zhou
IPC分类号： H05K1/14
CPC分类号： H05K1/112 , H05K1/0263 , H05K1/0296 , H05K1/115 , H05K3/3436 , H05K2201/0355 , H05K2201/1028 , Y10T29/49128 , Y10T29/49155
摘要： Power may be supplied to an electronic module according to various techniques. In one general implementation, for example, a system for supping power to an electronic module may include a printed circuit board, the electronic module, and a conductive foil. The board may include a number of contact locations on a first side, with at least one of the contact locations electrically coupled to a via to a second side of the board. The electronic module may be electrically coupled to the contact locations on the first side of the board and receive electrical power through the at least one contact location electrically coupled to a via. The foil may be adapted to convey electrical power for the electronic module and electrically coupled on the second side of circuit board to at least the via electrically coupled to a contact location that receives electrical power for the electronic module.
摘要翻译：可以根据各种技术向电子模块供电。在一般的实施方案中，例如，用于对电子模块的电力的系统可以包括印刷电路板，电子模块和导电箔。板可以包括在第一侧上的多个接触位置，其中至少一个接触位置电耦合到通孔到板的第二侧。电子模块可以电耦合到板的第一侧上的接触位置，并且通过电耦合到通孔的至少一个接触位置接收电力。箔可以适于传送用于电子模块的电力并且电耦合到电路板的第二侧上至少通过电气耦合到接收用于电子模块的电力的接触位置的通孔。

4. 发明申请

US20090193383A1 Auto-Router Performing Simultaneous Placement of Signal and Return Paths 有权
标题翻译：自动路由器执行信号和返回路径的同时放置
公开(公告)号：US20090193383A1
公开(公告)日：2009-07-30
申请号：US12021363
申请日：2008-01-29
申请人： Michael A. Christo , Julio A. Maldonado , Roger D. Weekly , Tingdong Zhou
发明人： Michael A. Christo , Julio A. Maldonado , Roger D. Weekly , Tingdong Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , H05K1/0237 , H05K3/0005 , H05K2201/09236 , H05K2201/09672
摘要： An auto routing method and system provides optimized circuit routing while maintaining proper reference return paths for critical signals. Critical signal paths are auto-routed simultaneously with corresponding reference return paths, and the reference return paths can be merged into reference planes if they are adjacent to regions connected to the same reference net. The reference return paths may be in a plane adjacent to the signal path plane in the same channel, or the reference returns may be routed in adjacent channels in the same plane as the signal path. A check may be performed on endpoints of each critical signal path to determine whether a reference return via is present within a proximity tolerance of the signal path endpoints, and a reference return via placed if not.
摘要翻译：自动路由方法和系统提供优化的电路路由，同时为关键信号保留适当的参考返回路径。临界信号路径与对应的参考返回路径同时自动路由，并且如果参考返回路径与连接到相同参考网络的区域相邻，则它们可以合并到参考平面中。参考返回路径可以在与相同信道中的信号路径平面相邻的平面中，或者参考返回可以在与信号路径相同的平面中的相邻信道中路由。可以在每个关键信号路径的端点上执行检查，以确定参考返回通道是否存在于信号路径端点的接近容限内，如果不是则通过放置参考返回。

5. 发明授权

US07533360B1 Flow based package pin assignment 失效
标题翻译：基于流量的封装引脚分配
公开(公告)号：US07533360B1
公开(公告)日：2009-05-12
申请号：US12177648
申请日：2008-07-22
申请人： Haoxing Ren , Hua Xiang , Tingdong Zhou
发明人： Haoxing Ren , Hua Xiang , Tingdong Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5072 , G06F2217/40
摘要： The present invention provides a method of performing BSM assignments for each routing layer typically having one BSM group (e.g. memory bus) per layer. Further, the present invention provides for routable BSM assignments. Further, the present invention provides a method for handling pair constraints providing for differential pairs to be placed close to each other. Further, the method of the present invention provides for simultaneous routing and pin assignments while honoring pair constraint concerns and optimizing wire length.
摘要翻译：本发明提供了一种通常每层具有一个BSM组（例如存储器总线）的每个路由层执行BSM分配的方法。此外，本发明提供可路由的BSM分配。此外，本发明提供了一种用于处理提供用于彼此靠近放置的差分对的对约束的方法。此外，本发明的方法提供同时布线和引脚分配，同时保证对约束关系并优化线长度。

6. 发明授权

US08339803B2 High-speed ceramic modules with hybrid referencing scheme for improved performance and reduced cost 有权
标题翻译：具有混合参考方案的高速陶瓷模块，可提高性能并降低成本
公开(公告)号：US08339803B2
公开(公告)日：2012-12-25
申请号：US12630993
申请日：2009-12-04
申请人： Wiren Dale Becker , Jinwoo Choi , Tingdong Zhou
发明人： Wiren Dale Becker , Jinwoo Choi , Tingdong Zhou
IPC分类号： H05K7/00
CPC分类号： H01L21/76838 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/66 , H01L2924/0002 , H01L2924/09701 , H01L2924/19051 , H01L2924/3011 , H05K1/0253 , H05K3/4629 , H05K2201/09309 , H05K2201/09681 , H05K2201/09727 , H05K2201/10674 , H01L2924/00
摘要： A multi-layered ceramic package comprises: a signal layer with identified chip/device area(s)/site(s) that require a supply of power; and a voltage power (Vdd) layer and a ground (Gnd) layer disposed on opposite sides directly above or below (adjacent to) the signal layer and providing a first reference mesh plane and a second reference mesh plane configured utilizing a hybrid mesh scheme. The hybrid mesh scheme comprises different mesh configurations from among: a full dense mesh in a first area directly above or below the identified chip/device area(s); a half dense mesh in a second area that is above or below the edge(s) of the chip/device area; and a wider mesh pitch in all other areas, and the Vdd traces are aligned to run parallel and adjacent to signal lines in those other areas. Wider traces are provided within the mesh areas that run parallel and adjacent to signal lines.
摘要翻译：多层陶瓷封装包括：具有识别的芯片/设备区域/需要供电电源的位置的信号层; 以及设置在信号层的正上方或下方（相邻）相对侧的电压功率（Vdd）层和接地（Gnd）层，并且提供使用混合网格方案配置的第一参考网格平面和第二参考网格平面。混合网格方案包括以下不同的网格配置：在识别的芯片/设备区域之上或之下的第一区域中的全密度网格; 在芯片/设备区域的边缘的上方或下方的第二区域中的半密度网格; 并且在所有其它区域中具有更宽的网格间距，并且Vdd迹线对准以在其他区域中与信号线平行并相邻地延伸。在与信号线平行且相邻的网格区域内提供更宽的轨迹。

7. 发明申请

US20080295041A1 System and Method for Power Domain Optimization 有权
标题翻译：电力域优化的系统和方法
公开(公告)号：US20080295041A1
公开(公告)日：2008-11-27
申请号：US11753644
申请日：2007-05-25
申请人： Tingdong Zhou , Michael A. Christo , Julio A. Maldonado , Roger D. Weekly
发明人： Tingdong Zhou , Michael A. Christo , Julio A. Maldonado , Roger D. Weekly
IPC分类号： G06F17/50
CPC分类号： H05K1/0262 , G06F17/5068 , G06F2217/78 , H05K3/0005 , H05K2201/093 , H05K2201/09336 , H05K2201/09345 , H05K2201/09663
摘要： A method for electronic circuit power plane design includes analyzing direct current (DC) properties of a power plane of an electronic circuit. The method includes analyzing power net inductance (PNI) properties of the power plane and identifying victim areas of the power plane having predetermined current density properties based on the DC properties and the PNI properties of the power plane. The method further includes replacing the identified victim areas with ground (GND) shapes to form a modified power plane.
摘要翻译：一种用于电子电路电源平面设计的方法包括分析电子电路的电源平面的直流（DC）特性。该方法包括基于电力平面的DC特性和PNI特性来分析功率平面的功率网络电感（PNI）特性和识别具有预定电流密度特性的功率平面的受害区域。该方法还包括用地（GND）形状替换所识别的受害区域，以形成修改后的电力平面。

8. 发明申请

US20110132650A1 High-Speed Ceramic Modules with Hybrid Referencing Scheme for Improved Performance and Reduced Cost 有权
标题翻译：具有混合参考方案的高速陶瓷模块，用于提高性能和降低成本
公开(公告)号：US20110132650A1
公开(公告)日：2011-06-09
申请号：US12630993
申请日：2009-12-04
申请人： Wiren D. Becker , Jinwoo Choi , Tingdong Zhou
发明人： Wiren D. Becker , Jinwoo Choi , Tingdong Zhou
IPC分类号： H01R12/06 , G06F17/50 , H05K3/10
CPC分类号： H01L21/76838 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/66 , H01L2924/0002 , H01L2924/09701 , H01L2924/19051 , H01L2924/3011 , H05K1/0253 , H05K3/4629 , H05K2201/09309 , H05K2201/09681 , H05K2201/09727 , H05K2201/10674 , H01L2924/00
摘要： A multi-layered ceramic package comprises: a signal layer with identified chip/device area(s)/site(s) that require a supply of power; and a voltage power (Vdd) layer and a ground (Gnd) layer disposed on opposite sides directly above or below (adjacent to) the signal layer and providing a first reference mesh plane and a second reference mesh plane configured utilizing a hybrid mesh scheme. The hybrid mesh scheme comprises different mesh configurations from among: a full dense mesh in a first area directly above or below the identified chip/device area(s); a half dense mesh in a second area that is above or below the edge(s) of the chip/device area; and a wider mesh pitch in all other areas, and the Vdd traces are aligned to run parallel and adjacent to signal lines in those other areas. Wider traces are provided within the mesh areas that run parallel and adjacent to signal lines.
摘要翻译：多层陶瓷封装包括：具有识别的芯片/设备区域/需要供电电源的位置的信号层; 以及设置在信号层的正上方或下方（相邻）相对侧的电压功率（Vdd）层和接地（Gnd）层，并且提供使用混合网格方案配置的第一参考网格平面和第二参考网格平面。混合网格方案包括以下不同的网格配置：在识别的芯片/设备区域之上或之下的第一区域中的全密度网格; 在芯片/设备区域的边缘的上方或下方的第二区域中的半密度网格; 并且在所有其它区域中具有更宽的网格间距，并且Vdd迹线对准以在其他区域中与信号线平行并相邻地延伸。在与信号线平行且相邻的网格区域内提供更宽的轨迹。

9. 发明授权

US07844925B2 System and method for power domain optimization 有权
标题翻译：电力域优化的系统和方法
公开(公告)号：US07844925B2
公开(公告)日：2010-11-30
申请号：US11753644
申请日：2007-05-25
申请人： Tingdong Zhou , Michael A. Christo , Julio A. Maldonado , Roger D. Weekly
发明人： Tingdong Zhou , Michael A. Christo , Julio A. Maldonado , Roger D. Weekly
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： H05K1/0262 , G06F17/5068 , G06F2217/78 , H05K3/0005 , H05K2201/093 , H05K2201/09336 , H05K2201/09345 , H05K2201/09663
摘要： A method for electronic circuit power plane design includes analyzing direct current (DC) properties of a power plane of an electronic circuit. The method includes analyzing power net inductance (PNI) properties of the power plane and identifying victim areas of the power plane having predetermined current density properties based on the DC properties and the PNI properties of the power plane. The method further includes replacing the identified victim areas with ground (GND) shapes to form a modified power plane.
摘要翻译：一种用于电子电路电源平面设计的方法包括分析电子电路的电源平面的直流（DC）特性。该方法包括基于电力平面的DC特性和PNI特性来分析功率平面的功率网络电感（PNI）特性和识别具有预定电流密度特性的功率平面的受害区域。该方法还包括用地（GND）形状替换所识别的受害区域，以形成修改后的电力平面。

10. 发明授权

US08683413B2 Method for making high-speed ceramic modules with hybrid referencing scheme for improved performance and reduced cost 有权
标题翻译：制造具有混合参考方案的高速陶瓷模块以提高性能并降低成本的方法
公开(公告)号：US08683413B2
公开(公告)日：2014-03-25
申请号：US13621242
申请日：2012-09-15
申请人： Wiren Dale Becker , Jinwoo Choi , Tingdong Zhou
发明人： Wiren Dale Becker , Jinwoo Choi , Tingdong Zhou
IPC分类号： G06F17/50 , G06F9/455 , H01L21/00
CPC分类号： H01L21/76838 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/66 , H01L2924/0002 , H01L2924/09701 , H01L2924/19051 , H01L2924/3011 , H05K1/0253 , H05K3/4629 , H05K2201/09309 , H05K2201/09681 , H05K2201/09727 , H05K2201/10674 , H01L2924/00
摘要： A multi-layered ceramic package comprises: a signal layer with identified chip/device area(s) that require a supply of power; and a voltage power (Vdd) layer and a ground (Gnd) layer disposed on opposite sides directly above or below and adjacent to the signal layer and providing a first reference mesh plane and a second reference mesh plane configured utilizing a hybrid mesh scheme. The hybrid mesh scheme comprises: a full dense mesh in a first area directly above or below the identified chip/device area(s); a half dense mesh in a second area that is above or below the edge(s) of the chip/device area; and a wider mesh pitch in all other areas The Vdd traces are aligned to run parallel and adjacent to signal lines in those other areas. Wider traces are provided within the mesh areas that run parallel and adjacent to signal lines.
摘要翻译：多层陶瓷封装包括：具有需要供电的识别芯片/器件区域的信号层; 以及设置在信号层正上方或下方并相邻的相对侧上的电压功率（Vdd）层和接地（Gnd）层，并提供使用混合网格方案配置的第一参考网格平面和第二参考网格平面。混合网格方案包括：在识别的芯片/设备区域的正上方或下方的第一区域中的全密度网格; 在芯片/设备区域的边缘的上方或下方的第二区域中的半密度网格; 和所有其他区域中的较宽的网格间距Vdd迹线对齐以与其他区域的信号线平行并相邻。在与信号线平行且相邻的网格区域内提供更宽的轨迹。

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