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1. 发明授权

US08270240B2 Current leakage reduction 有权
标题翻译：电流泄漏减少
公开(公告)号：US08270240B2
公开(公告)日：2012-09-18
申请号：US12784025
申请日：2010-05-20
申请人： Sung-Chieh Lin , Kuoyuan (Peter) Hsu , Jiann-Tseng Huang , We-Li Liao
发明人： Sung-Chieh Lin , Kuoyuan (Peter) Hsu , Jiann-Tseng Huang , We-Li Liao
IPC分类号： G11C29/00
CPC分类号： G11C8/12 , G11C17/18
摘要： An OTP memory array includes a bit line coupled to a plurality of memory banks. Each memory bank includes a plurality of memory cells, a footer, and a bias device, and is associated with a current mirror. When a memory cell is activated (e.g., for reading) the memory bank including the activated memory cell is referred to as an activated memory bank and other banks are referred to as deactivated memory banks. A current tracking device serves to compensate for bit line leakage current in deactivated memory cells in the activated memory bank. Further, footers and bias devices in deactivated memory banks and associated current mirrors are configured to reduce/eliminate bit line current leakage through deactivated memory cells in deactivated memory banks.
摘要翻译： OTP存储器阵列包括耦合到多个存储体的位线。每个存储体包括多个存储单元，一个页脚和一个偏置装置，并与一个电流镜相关联。当存储器单元被激活（例如，用于读取）时，包括激活的存储器单元的存储体被称为激活的存储体，并且其它存储体被称为禁用存储体。电流跟踪装置用于补偿激活的存储体中的去激活的存储器单元中的位线泄漏电流。此外，禁用存储器组和相关联的电流镜中的脚和偏置器件被配置为通过去激活的存储体中的去激活的存储器单元来减少/消除位线电流泄漏。

2. 发明申请

US20110026354A1 CURRENT LEAKAGE REDUCTION 有权
标题翻译：电流泄漏减少
公开(公告)号：US20110026354A1
公开(公告)日：2011-02-03
申请号：US12784025
申请日：2010-05-20
申请人： Sung-Chieh Lin , Kuoyuan (Peter) Hsu , Jiann-Tseng Huang , We-Li Liao
发明人： Sung-Chieh Lin , Kuoyuan (Peter) Hsu , Jiann-Tseng Huang , We-Li Liao
IPC分类号： G11C5/14 , G11C8/00 , G11C17/00
CPC分类号： G11C8/12 , G11C17/18
摘要： An OTP memory array includes a bit line coupled to a plurality of memory banks. Each memory bank includes a plurality of memory cells, a footer, and a bias device, and is associated with a current mirror. When a memory cell is activated (e.g., for reading) the memory bank including the activated memory cell is referred to as an activated memory bank and other banks are referred to as deactivated memory banks. A current tracking device serves to compensate for bit line leakage current in deactivated memory cells in the activated memory bank. Further, footers and bias devices in deactivated memory banks and associated current mirrors are configured to reduce/eliminate bit line current leakage through deactivated memory cells in deactivated memory banks.
摘要翻译： OTP存储器阵列包括耦合到多个存储体的位线。每个存储体包括多个存储单元，一个页脚和一个偏置装置，并与一个电流镜相关联。当存储器单元被激活（例如，用于读取）时，包括激活的存储器单元的存储体被称为激活的存储体，并且其他存储体被称为去激活存储体。电流跟踪装置用于补偿激活的存储体中的去激活的存储器单元中的位线泄漏电流。此外，禁用存储器组和相关联的电流镜中的脚和偏置器件被配置为通过去激活的存储体中的去激活的存储器单元来减少/消除位线电流泄漏。

3. 发明授权

US08400860B2 Electrical fuse memory 有权
标题翻译：电熔丝记忆体
公开(公告)号：US08400860B2
公开(公告)日：2013-03-19
申请号：US12839542
申请日：2010-07-20
申请人： Sung-Chieh Lin , David Yen , Wei-Li Liao , Jiann-Tseng Huang , Kuoyuan (Peter) Hsu
发明人： Sung-Chieh Lin , David Yen , Wei-Li Liao , Jiann-Tseng Huang , Kuoyuan (Peter) Hsu
IPC分类号： G11C17/16
CPC分类号： G11C17/16
摘要： Some embodiments regard a memory array that has a plurality of rows and columns. A column includes a program control device, a plurality of eFuse memory cells in the column, a sense amplifier, and a bit line coupling the program control device, the plurality of memory cells in the column, and the sense amplifier. A row includes a plurality of eFuse memory cells in the row, a word line coupling the plurality of eFuse memory cells in the row, and a footer configured as a current path for the plurality of eFuse memory cells in the row.
摘要翻译：一些实施例涉及具有多个行和列的存储器阵列。列包括程序控制装置，列中的多个eFuse存储器单元，读出放大器和耦合程序控制装置，列中的多个存储单元和读出放大器的位线。行包括行中的多个eFuse存储器单元，耦合行中的多个eFuse存储器单元的字线和被配置为行中的多个eFuse存储器单元的当前路径的页脚。

4. 发明授权

US08767498B2 Circuit and method for generating a read signal 有权
标题翻译：用于产生读取信号的电路和方法
公开(公告)号：US08767498B2
公开(公告)日：2014-07-01
申请号：US13285357
申请日：2011-10-31
申请人： Jiann-Tseng Huang , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
发明人： Jiann-Tseng Huang , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
IPC分类号： G11C17/14
CPC分类号： G11C17/16 , G11C17/18
摘要： A circuit includes a fuse circuit and a control circuit. The fuse circuit has an electrical fuse. The control circuit is configured to receive an input signal having an input pulse, and, based on a feedback signal from the fuse circuit, generates a read pulse smaller than the input pulse for use in reading the data stored in the electrical fuse.
摘要翻译：电路包括熔丝电路和控制电路。保险丝电路具有电熔丝。控制电路被配置为接收具有输入脉冲的输入信号，并且基于来自熔丝电路的反馈信号，产生比用于读取存储在电熔丝中的数据的输入脉冲更小的读取脉冲。

5. 发明授权

US08824234B2 Electrical fuse memory 有权
标题翻译：电熔丝记忆体
公开(公告)号：US08824234B2
公开(公告)日：2014-09-02
申请号：US13771674
申请日：2013-02-20
申请人： Sung-Chieh Lin , David Yen , Wei-Li Liao , Jiann-Tseng Huang , Kuoyuan (Peter) Hsu
发明人： Sung-Chieh Lin , David Yen , Wei-Li Liao , Jiann-Tseng Huang , Kuoyuan (Peter) Hsu
IPC分类号： G11C17/16
CPC分类号： G11C17/16
摘要： A method of reading an eFuse in a column of eFuse memory cells includes electrically disconnecting a first end of the eFuse from a first electrical path. A second electrical path between a second end of the eFuse and a node is activated to bypass a third electrical path, where the third electrical path includes a diode device between the second end of the eFuse and the node. A footer coupled with the node is turned on.
摘要翻译：读取eFuse存储单元列中的eFuse的方法包括将eFuse的第一端与第一电路断开。 eFuse的第二端和节点之间的第二电路被激活以绕过第三电路，其中第三电路包括在eFuse的第二端和节点之间的二极管器件。与节点耦合的页脚被打开。

6. 发明授权

US08614927B2 Current leakage reduction 有权
标题翻译：电流泄漏减少
公开(公告)号：US08614927B2
公开(公告)日：2013-12-24
申请号：US13595551
申请日：2012-08-27
申请人： Sung-Chieh Lin , Kuoyuan (Peter) Hsu , Jiann-Tseng Huang , Wei-Li Liao
发明人： Sung-Chieh Lin , Kuoyuan (Peter) Hsu , Jiann-Tseng Huang , Wei-Li Liao
IPC分类号： G11C7/00
CPC分类号： G11C8/12 , G11C17/18
摘要： This description relates to a circuit including a bit line. The circuit further includes at least one memory bank. The at least one memory bank includes at least one memory cell, a first device configured to provide a current path between the bit line and the at least one memory cell when the at least one memory cell is activated, and a second device configured to reduce current leakage between the bit line and the at least one memory cell when the at least one memory cell is deactivated. The circuit further includes a tracking device configured to receive a mirror current substantially equal to a current along the current path, the tracking device configured to have a resistance substantially equal to a cumulative resistance of all memory cells of the at least one memory cell.
摘要翻译：本说明书涉及包括位线的电路。电路还包括至少一个存储体。所述至少一个存储体包括至少一个存储单元，配置为当所述至少一个存储单元被激活时在所述位线和所述至少一个存储器单元之间提供电流路径的第一设备，以及被配置为减少当所述至少一个存储器单元被停用时，所述位线与所述至少一个存储器单元之间的电流泄漏。电路还包括跟踪装置，其被配置为接收基本上等于沿着电流路径的电流的反射镜电流，跟踪装置被配置为具有基本上等于至少一个存储器单元的所有存储器单元的累积电阻的电阻。

7. 发明申请

US20120051162A1 METHOD AND APPARATUS FOR BIT CELL REPAIR 有权
标题翻译：用于位单元修复的方法和装置
公开(公告)号：US20120051162A1
公开(公告)日：2012-03-01
申请号：US12871417
申请日：2010-08-30
申请人： Sung-Chieh Lin , Jiann-Tseng Huang , Wei-Li Liao , Kuoyuan Hsu
发明人： Sung-Chieh Lin , Jiann-Tseng Huang , Wei-Li Liao , Kuoyuan Hsu
IPC分类号： G11C29/04
CPC分类号： G11C29/04 , G11C29/44
摘要： A method includes reading data from a subset of a plurality of memory bit cells of a non-volatile memory. The data identifies an address of at least one individual failed bit cell. The method further includes loading the data directly into a register, receiving an address of data to be accessed, determining if the received address is the address of any individual failed bit cell; and accessing the data of the register if the received address is the address of any individual failed bit cell.
摘要翻译：一种方法包括从非易失性存储器的多个存储位单元的子集读取数据。数据标识至少一个单独故障位单元的地址。该方法还包括将数据直接加载到寄存器中，接收要访问的数据的地址，确定接收的地址是否是任何单个故障位单元的地址; 并且如果接收到的地址是任何单个故障位单元的地址，则访问寄存器的数据。

8. 发明授权

US08194490B2 Electrical fuse memory arrays 有权
标题翻译：电熔丝存储器阵列
公开(公告)号：US08194490B2
公开(公告)日：2012-06-05
申请号：US12877646
申请日：2010-09-08
申请人： Po-Hung Chen , Chin-Huang Wang , Yen-Chieh Huang , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
发明人： Po-Hung Chen , Chin-Huang Wang , Yen-Chieh Huang , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
IPC分类号： G11C17/18
CPC分类号： G11C17/165
摘要： Some embodiments regard a memory array that has a plurality of eFuse memory cells arranged in rows and columns, a plurality of bit lines, and a plurality of word lines. A column includes a bit line selector, a bit line coupled to the bit line selector, and a plurality of eFuse memory cells. An eFuse memory cell of the column includes a PMOS transistor and an eFuse. A drain of the PMOS transistor is coupled to a first end of the eFuse. A gate of the PMOS transistor is coupled to a word line. A source of the PMOS transistor is coupled to the bit line of the column.
摘要翻译：一些实施例涉及具有以行和列，多个位线和多个字线布置的多个eFuse存储器单元的存储器阵列。列包括位线选择器，耦合到位线选择器的位线和多个eFuse存储器单元。该列的eFuse存储单元包括PMOS晶体管和eFuse。 PMOS晶体管的漏极耦合到eFuse的第一端。 PMOS晶体管的栅极耦合到字线。 PMOS晶体管的源极耦合到列的位线。

9. 发明申请

US20090243705A1 High Voltage Tolerative Driver Circuit 审中-公开
标题翻译：高电压容差驱动电路
公开(公告)号：US20090243705A1
公开(公告)日：2009-10-01
申请号：US12057585
申请日：2008-03-28
申请人： Jiann-Tseng Huang , Sung-Chieh Lin
发明人： Jiann-Tseng Huang , Sung-Chieh Lin
IPC分类号： G11C5/14
CPC分类号： H03K19/00315
摘要： A high voltage tolerative inverter circuit is disclosed, which comprises a PMOS transistor with a source and drain being connected to a first high voltage power supply (VDDQ) and an output terminal, respectively, a gate of the PMOS transistor being controlled by a first signal having a voltage swing between the VDDQ and a low voltage power supply (VSS), and a NMOS transistor with a source and drain being connected to the VSS and the output terminal, a gate of the NMOS transistor being controlled by a second signal having a voltage swing between a second high voltage power supply (VDD) and the VSS, wherein the VDD is lower than the VDDQ, and the voltage swings between the VDDQ and the VSS by the first signal and between the VDD and the VSS by the second signal are always in the same direction.
摘要翻译：公开了一种高耐压逆变器电路，其包括PMOS晶体管，其源极和漏极分别连接到第一高电压电源（VDDQ）和输出端子，PMOS晶体管的栅极由第一信号在VDDQ和低电压电源（VSS）之间具有电压摆幅，以及具有源极和漏极连接到VSS和输出端子的NMOS晶体管，NMOS晶体管的栅极由具有第二高压电源（VDD）和VSS之间的电压摆幅，其中VDD低于VDDQ，VDDQ和VSS之间的电压按照第一信号在VDD和VSS之间摆动第二信号总是在同一个方向。

10. 发明授权

US07394637B2 Sense amplifier with leakage compensation for electrical fuses 有权
标题翻译：带有漏电补偿功能的感应放大器
公开(公告)号：US07394637B2
公开(公告)日：2008-07-01
申请号：US11304174
申请日：2005-12-15
申请人： Sung-Chieh Lin , Hung-Jen Liao , Fu-Lung Hsueh , Jiann-Tseng Huang
发明人： Sung-Chieh Lin , Hung-Jen Liao , Fu-Lung Hsueh , Jiann-Tseng Huang
IPC分类号： H02H5/04
CPC分类号： G11C17/18
摘要： A sense amplifier for detecting a logic state of a selected electrical fuse cell among a number of unselected electrical fuse cells includes a bias module coupled to a power supply for generating a first current, and a tracking module coupled to the bias module for generating a second current. A current supplier is coupled to the bias module and the tracking module for generating a third current substantially equal to a sum of the first and second currents scaled by a predetermined factor, the third current being diverted into a first sub-current flowing through the selected electrical fuse cell and a second sub-current leaking through the unselected electrical fuse cells. The tracking module is so configured that the second current scaled by the predetermined factor is substantially equal to the second sub-current, thereby avoiding the first sub-current to be reduced by the second sub-current.
摘要翻译：用于检测多个未选择的电熔丝单元中的所选择的电熔丝单元的逻辑状态的读出放大器包括耦合到电源的用于产生第一电流的偏置模块，以及耦合到偏置模块的跟踪模块，用于产生第二当前。当前供应商耦合到偏置模块和跟踪模块，用于产生基本上等于由预定因子缩放的第一和第二电流之和的第三电流，第三电流被转移到流过所选择的第一电流的第一子电流电熔丝单元和第二子电流通过未选择的电熔丝单元泄漏。跟踪模块被配置为使得按预定因子缩放的第二电流基本上等于第二子电流，从而避免第一子电流被第二子电流减小。

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