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1. 发明授权

US09041069B2 Distributed metal routing 有权
标题翻译：分布式金属布线
公开(公告)号：US09041069B2
公开(公告)日：2015-05-26
申请号：US13007235
申请日：2011-01-14
申请人： You-Cheng Xiao , Yen-Huei Chen , Jung-Hsuan Chen , Shao-Yu Chou , Li-Chun Tien , Hung-Jen Liao
发明人： You-Cheng Xiao , Yen-Huei Chen , Jung-Hsuan Chen , Shao-Yu Chou , Li-Chun Tien , Hung-Jen Liao
IPC分类号： H01L23/52 , H01L23/485 , H01L23/528 , H01L23/482 , H01L23/522
CPC分类号： H01L21/76879 , H01L21/768 , H01L21/76832 , H01L23/4824 , H01L23/485 , H01L23/522 , H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.
摘要翻译：公开了一种用于分布式金属布线的系统和方法。一个实施例包括具有覆盖在metal_0层上的metal_1层的metal_0层。金属层1包括分开的平行线，具有不同信号的线分布在metal_1层上。这样的布局减小了metal_0层内的寄生电阻，因为它减小了电流行进的距离。此外，metal_1中的分布式布局允许连接到metal_2层，而不需要通孔的锤头连接。

2. 发明授权

US08792292B2 Providing row redundancy to solve vertical twin bit failures 有权
标题翻译：提供行冗余来解决垂直双位故障
公开(公告)号：US08792292B2
公开(公告)日：2014-07-29
申请号：US13046625
申请日：2011-03-11
申请人： Hong-Chen Cheng , Jung-Ping Yang , Chung-Ji Lu , Derek C. Tao , Cheng Hung Lee , Hung-Jen Liao
发明人： Hong-Chen Cheng , Jung-Ping Yang , Chung-Ji Lu , Derek C. Tao , Cheng Hung Lee , Hung-Jen Liao
IPC分类号： G11C29/00
CPC分类号： G11C29/846
摘要： A circuit includes a failure address register configured to store a first row address, a row address modifier coupled to the failure address register, wherein the row address modifier is configured to modify the first row address received from the failure address register to generate a second row address. A first comparator is configured to receive and compare the first row address and a third row address. A second comparator is configured to receive and compare the second row address and the third row address. The first and the second row addresses are failed row addresses in a memory.
摘要翻译：电路包括被配置为存储第一行地址的故障地址寄存器，耦合到故障地址寄存器的行地址修改器，其中行地址修改器被配置为修改从故障地址寄存器接收的第一行地址以生成第二行地址。第一比较器被配置为接收和比较第一行地址和第三行地址。第二比较器被配置为接收和比较第二行地址和第三行地址。第一行地址和第二行地址是存储器中的失败行地址。

3. 发明申请

US20130263066A1 Pre-Colored Methodology of Multiple Patterning 有权
标题翻译：多种图案预色彩方法
公开(公告)号：US20130263066A1
公开(公告)日：2013-10-03
申请号：US13607946
申请日：2012-09-10
申请人： Yen-Huei Chen , Hung-Jen Liao , Jonathan Tsung-Yung Chang
发明人： Yen-Huei Chen , Hung-Jen Liao , Jonathan Tsung-Yung Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Some embodiments relate to a method of pre-coloring word lines and control lines within an SRAM integrated chip design to avoid timing delays that result from processing variations introduced through multiple patterning lithography processes. The method is performed by generating a graphical IC layout file having an SRAM circuit with a plurality of word lines and Y-control lines. The word lines and Y-control lines are assigned a color during decomposition. The word lines and Y-control lines are further pre-colored in a manner that deliberately assigns the pre-colored data to a same mask. Therefore, during mask building, data associated with pre-colored word and Y-control lines is sent to a same mask, regardless of the colors that are assigned to the data. By assigning word and Y-control lines to a same mask through pre-coloring, processing variations between the word and Y-control lines are minimized, thereby mitigating timing variations in an SRAM circuit.
摘要翻译：一些实施例涉及在SRAM集成芯片设计中预先着色字线和控制线的方法，以避免由通过多次图案化光刻工艺引入的处理变化而产生的定时延迟。该方法通过生成具有多个字线和Y控制线的SRAM电路的图形IC布局文件来执行。在分解过程中，字线和Y控制线被分配一个颜色。字线和Y控制线进一步预先着色，以故意将预色数据分配给相同的掩码。因此，在面具构建期间，与预色彩字和Y控制线相关联的数据被发送到相同的掩码，而不管分配给数据的颜色如何。通过预分色将字和Y控制线分配给相同的掩码，字和Y控制线之间的处理变化被最小化，从而减轻SRAM电路中的定时变化。

4. 发明申请

US20130188433A1 MEMORY CIRCUIT AND METHOD OF WRITING DATUM TO MEMORY CIRCUIT 有权
标题翻译：存储器电路和将数据写入存储器电路的方法
公开(公告)号：US20130188433A1
公开(公告)日：2013-07-25
申请号：US13354884
申请日：2012-01-20
申请人： Chih-Yu LIN , Wei Min CHAN , Yen-Huei CHEN , Hung-Jen LIAO , Jonathan Tsung-Yung CHANG
发明人： Chih-Yu LIN , Wei Min CHAN , Yen-Huei CHEN , Hung-Jen LIAO , Jonathan Tsung-Yung CHANG
IPC分类号： G11C7/00
CPC分类号： G11C11/419
摘要： A circuit includes a first node, a second node, a memory cell, a first data line, a second data line, and a write driver. The memory cell is coupled to the first node and the second node and powered by a first voltage at the first node and a second voltage at the second node. The first data line and the second data line are coupled to the memory cell. The write driver has a third node carrying a third voltage less than the first voltage during a write operation. The write deriver is coupled to the first data line and the second data line and configured to, during a write operation, selectively coupling one of the first data line and the second data line to the third node and coupling the other one of the first data line and the second data line to the first node.
摘要翻译：电路包括第一节点，第二节点，存储器单元，第一数据线，第二数据线和写驱动器。存储器单元耦合到第一节点和第二节点，并由第一节点处的第一电压和第二节点处的第二电压供电。第一数据线和第二数据线耦合到存储器单元。写入驱动器具有在写入操作期间承载小于第一电压的第三电压的第三节点。写引导器耦合到第一数据线和第二数据线，并且被配置为在写操作期间，选择性地将第一数据线和第二数据线之一耦合到第三节点，并将第一数据中的另一个耦合线和第二条数据线到第一个节点。

5. 发明授权

US08488395B2 Keepers, integrated circuits, and systems thereof 有权
标题翻译：保管人，集成电路及其系统
公开(公告)号：US08488395B2
公开(公告)日：2013-07-16
申请号：US12754733
申请日：2010-04-06
申请人： Cheng Hung Lee , Ching-Wei Wu , Bin Sheng , Hung-Jen Liao
发明人： Cheng Hung Lee , Ching-Wei Wu , Bin Sheng , Hung-Jen Liao
IPC分类号： G11C7/00
CPC分类号： H01L27/1104 , G11C11/419
摘要： A keeper of an integrated circuit includes a first transistor having a first gate being coupled with an output end of an inverter. A second transistor is coupled with the first transistor in series. The second transistor has a second gate being coupled with an input end of the inverter.
摘要翻译：集成电路的保持器包括具有与反相器的输出端耦合的第一栅极的第一晶体管。第二晶体管与第一晶体管串联耦合。第二晶体管具有与反相器的输入端耦合的第二栅极。

6. 发明授权

US08427888B2 Word-line driver using level shifter at local control circuit 有权
标题翻译：在本地控制电路上使用电平转换器的字线驱动器
公开(公告)号：US08427888B2
公开(公告)日：2013-04-23
申请号：US12702594
申请日：2010-02-09
申请人： Chung-Ji Lu , Lee-Cheng Hung , Hung-Jen Liao , Hsu-Shun Chen , Hong-Chen Cheng , Chung-Yi Wu , Uppu Sharath Chandra
发明人： Chung-Ji Lu , Lee-Cheng Hung , Hung-Jen Liao , Hsu-Shun Chen , Hong-Chen Cheng , Chung-Yi Wu , Uppu Sharath Chandra
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C8/10
摘要： A representative circuit device includes a local control circuit having a level shifter, wherein in response to receipt of a first address signal the level shifter shifts the first address signal from a first voltage level to a second voltage level, providing a level shifted first address signal; and a word-line driver having at least one input for receiving a plurality of address signals, wherein the at least one input includes a first input that is coupled to the local control circuit to receive the level shifted first address signal, and an output that is electrically coupled to a word line of a memory cell array.
摘要翻译：代表性电路装置包括具有电平移位器的本地控制电路，其中响应于接收到第一地址信号，电平移位器将第一地址信号从第一电压电平移位到第二电压电平，提供电平移位的第一地址信号 ; 以及具有用于接收多个地址信号的至少一个输入的字线驱动器，其中所述至少一个输入包括耦合到所述本地控制电路以接收所述电平移位的第一地址信号的第一输入，以及输出，电耦合到存储单元阵列的字线。

7. 发明申请

US20130094307A1 BIT LINE VOLTAGE BIAS FOR LOW POWER MEMORY DESIGN 有权
标题翻译：用于低功率存储器设计的位线电压偏置
公开(公告)号：US20130094307A1
公开(公告)日：2013-04-18
申请号：US13271353
申请日：2011-10-12
申请人： Hong-Chen CHENG , Jung-Ping Yang , Chiting Cheng , Cheng-Hung Lee , Sang H. Dong , Hung-Jen Liao
发明人： Hong-Chen CHENG , Jung-Ping Yang , Chiting Cheng , Cheng-Hung Lee , Sang H. Dong , Hung-Jen Liao
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C11/419
摘要： In a digital memory with an array of bit cells coupled to word lines and bit lines, each bit cell having cross coupled inverters isolated from bit lines by passing gate transistors until addressed, some or all of the bit cells are switchable between a sleep mode and a standby mode in response to a control signal. A bit line bias circuit controls the voltage at which the bit lines are caused to float when in the sleep mode. A pull-up transistor for each bit line BL or BLB in a complementary pair has a conductive channel coupled to a positive supply voltage and a gate coupled to the other bit line in the pair, BLB or BL, respectively. A connecting transistor also can be coupled between the bit lines of the complementary pair, bringing the floating bit lines to the supply voltage less a difference voltage ΔV.
摘要翻译：在具有耦合到字线和位线的位单元阵列的数字存储器中，每个位单元具有通过将栅极晶体管直接寻址而与位线隔离的交叉耦合的反相器，部分或全部位单元可在睡眠模式和响应于控制信号的待机模式。位线偏置电路控制在处于睡眠模式时使位线浮动的电压。用于互补对中的每个位线BL或BLB的上拉晶体管具有耦合到正电源电压的导电沟道和耦合到该对BLB或BL中的另一位线的栅极。连接晶体管也可以耦合在互补对的位线之间，使浮置位线降低到差值ΔVV的电源电压。

8. 发明授权

US08395950B2 Memory device having a clock skew generator 有权
标题翻译：具有时钟偏移发生器的存储器件
公开(公告)号：US08395950B2
公开(公告)日：2013-03-12
申请号：US12968582
申请日：2010-12-15
申请人： Tzu-Kuei Lin , Hung-Jen Liao , Shao-Yu Chou , Ching-Wei Wu
发明人： Tzu-Kuei Lin , Hung-Jen Liao , Shao-Yu Chou , Ching-Wei Wu
IPC分类号： G11C7/00
CPC分类号： G11C7/222
摘要： A memory device is provided with memory components and a clock skew generator, supporting at least two read and write operations that can occur coincidentally in read-read, read-write and write-write modes of operation of the memory device. The clock skew generator produces at least two stable and balanced clock channels carrying the at least two clock signals and varies relative timing of the clock signal edges so as to displace the edges in time, in those modes of operation wherein simultaneous edges would lead to detrimental loading.
摘要翻译：存储器件具有存储器组件和时钟偏斜发生器，支持在存储器件的读取，读写和写入 - 写入操作模式中可能巧合地发生的至少两个读和写操作。时钟偏移发生器产生至少两个稳定和平衡的时钟通道，其承载至少两个时钟信号，并且改变时钟信号边沿的相对定时，从而在这些操作模式中随时移动边缘，其中同时的边缘将导致有害的加载。

9. 发明授权

US08363454B2 SRAM bit cell 有权
标题翻译： SRAM位单元
公开(公告)号：US08363454B2
公开(公告)日：2013-01-29
申请号：US13015773
申请日：2011-01-28
申请人： Ping Wang , Hung-Jen Liao , Yen-Huei Chen , Jihi-Yu Lin , Shao-Yu Chou
发明人： Ping Wang , Hung-Jen Liao , Yen-Huei Chen , Jihi-Yu Lin , Shao-Yu Chou
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A semiconductor memory bit cell includes an inverter latch including a pair of cross-coupled inverters. A first transistor has a gate coupled to a first control line and a source coupled to the inverter latch, and a second transistor has a gate coupled to a second control line and a drain coupled to the drain of the first transistor at a first node. A third transistor has a source coupled to the first node and a gate coupled to a word line, and a fourth transistor has a gate coupled to a source of the second transistor and to the inverter latch. A fifth transistor has a gate coupled to the word line and a drain coupled to a read bit line.
摘要翻译：半导体存储器位单元包括具有一对交叉耦合的反相器的反相器锁存器。第一晶体管具有耦合到第一控制线的栅极和耦合到反相器锁存器的源极，并且第二晶体管具有耦合到第二控制线的栅极和在第一节点耦合到第一晶体管的漏极的漏极。第三晶体管具有耦合到第一节点的源极和耦合到字线的栅极，并且第四晶体管具有耦合到第二晶体管的源极和反相器锁存器的栅极。第五晶体管具有耦合到字线的栅极和耦合到读位线的漏极。

10. 发明申请

US20120258592A1 Layouts of POLY Cut Openings Overlapping Active Regions 有权
标题翻译： POLY切割开关重叠活动区域的布局
公开(公告)号：US20120258592A1
公开(公告)日：2012-10-11
申请号：US13081115
申请日：2011-04-06
申请人： Jung-Hsuan Chen , Yen-Huei Chen , Li-Chun Tien , Hung-Jen Liao
发明人： Jung-Hsuan Chen , Yen-Huei Chen , Li-Chun Tien , Hung-Jen Liao
IPC分类号： H01L21/28
CPC分类号： H01L21/32139 , H01L21/76816
摘要： A method of forming integrated circuits includes forming a mask layer over a gate electrode line, wherein the gate electrode line is over a well region of a semiconductor substrate; forming an opening in the mask layer, wherein a portion of the gate electrode line and a well pickup region of the well region are exposed through the opening; and removing the portion of the gate electrode line through the opening.
摘要翻译：形成集成电路的方法包括在栅电极线上形成掩模层，其中栅电极线在半导体衬底的阱区之上; 在所述掩模层中形成开口，其中所述栅电极线的一部分和所述阱区的阱拾取区域通过所述开口露出; 并且通过所述开口去除所述栅电极线的所述部分。

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