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1. 发明授权

US08400860B2 Electrical fuse memory 有权
标题翻译：电熔丝记忆体
公开(公告)号：US08400860B2
公开(公告)日：2013-03-19
申请号：US12839542
申请日：2010-07-20
申请人： Sung-Chieh Lin , David Yen , Wei-Li Liao , Jiann-Tseng Huang , Kuoyuan (Peter) Hsu
发明人： Sung-Chieh Lin , David Yen , Wei-Li Liao , Jiann-Tseng Huang , Kuoyuan (Peter) Hsu
IPC分类号： G11C17/16
CPC分类号： G11C17/16
摘要： Some embodiments regard a memory array that has a plurality of rows and columns. A column includes a program control device, a plurality of eFuse memory cells in the column, a sense amplifier, and a bit line coupling the program control device, the plurality of memory cells in the column, and the sense amplifier. A row includes a plurality of eFuse memory cells in the row, a word line coupling the plurality of eFuse memory cells in the row, and a footer configured as a current path for the plurality of eFuse memory cells in the row.
摘要翻译：一些实施例涉及具有多个行和列的存储器阵列。列包括程序控制装置，列中的多个eFuse存储器单元，读出放大器和耦合程序控制装置，列中的多个存储单元和读出放大器的位线。行包括行中的多个eFuse存储器单元，耦合行中的多个eFuse存储器单元的字线和被配置为行中的多个eFuse存储器单元的当前路径的页脚。

2. 发明授权

US08767498B2 Circuit and method for generating a read signal 有权
标题翻译：用于产生读取信号的电路和方法
公开(公告)号：US08767498B2
公开(公告)日：2014-07-01
申请号：US13285357
申请日：2011-10-31
申请人： Jiann-Tseng Huang , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
发明人： Jiann-Tseng Huang , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
IPC分类号： G11C17/14
CPC分类号： G11C17/16 , G11C17/18
摘要： A circuit includes a fuse circuit and a control circuit. The fuse circuit has an electrical fuse. The control circuit is configured to receive an input signal having an input pulse, and, based on a feedback signal from the fuse circuit, generates a read pulse smaller than the input pulse for use in reading the data stored in the electrical fuse.
摘要翻译：电路包括熔丝电路和控制电路。保险丝电路具有电熔丝。控制电路被配置为接收具有输入脉冲的输入信号，并且基于来自熔丝电路的反馈信号，产生比用于读取存储在电熔丝中的数据的输入脉冲更小的读取脉冲。

3. 发明授权

US08824234B2 Electrical fuse memory 有权
标题翻译：电熔丝记忆体
公开(公告)号：US08824234B2
公开(公告)日：2014-09-02
申请号：US13771674
申请日：2013-02-20
申请人： Sung-Chieh Lin , David Yen , Wei-Li Liao , Jiann-Tseng Huang , Kuoyuan (Peter) Hsu
发明人： Sung-Chieh Lin , David Yen , Wei-Li Liao , Jiann-Tseng Huang , Kuoyuan (Peter) Hsu
IPC分类号： G11C17/16
CPC分类号： G11C17/16
摘要： A method of reading an eFuse in a column of eFuse memory cells includes electrically disconnecting a first end of the eFuse from a first electrical path. A second electrical path between a second end of the eFuse and a node is activated to bypass a third electrical path, where the third electrical path includes a diode device between the second end of the eFuse and the node. A footer coupled with the node is turned on.
摘要翻译：读取eFuse存储单元列中的eFuse的方法包括将eFuse的第一端与第一电路断开。 eFuse的第二端和节点之间的第二电路被激活以绕过第三电路，其中第三电路包括在eFuse的第二端和节点之间的二极管器件。与节点耦合的页脚被打开。

4. 发明授权

US08614927B2 Current leakage reduction 有权
标题翻译：电流泄漏减少
公开(公告)号：US08614927B2
公开(公告)日：2013-12-24
申请号：US13595551
申请日：2012-08-27
申请人： Sung-Chieh Lin , Kuoyuan (Peter) Hsu , Jiann-Tseng Huang , Wei-Li Liao
发明人： Sung-Chieh Lin , Kuoyuan (Peter) Hsu , Jiann-Tseng Huang , Wei-Li Liao
IPC分类号： G11C7/00
CPC分类号： G11C8/12 , G11C17/18
摘要： This description relates to a circuit including a bit line. The circuit further includes at least one memory bank. The at least one memory bank includes at least one memory cell, a first device configured to provide a current path between the bit line and the at least one memory cell when the at least one memory cell is activated, and a second device configured to reduce current leakage between the bit line and the at least one memory cell when the at least one memory cell is deactivated. The circuit further includes a tracking device configured to receive a mirror current substantially equal to a current along the current path, the tracking device configured to have a resistance substantially equal to a cumulative resistance of all memory cells of the at least one memory cell.
摘要翻译：本说明书涉及包括位线的电路。电路还包括至少一个存储体。所述至少一个存储体包括至少一个存储单元，配置为当所述至少一个存储单元被激活时在所述位线和所述至少一个存储器单元之间提供电流路径的第一设备，以及被配置为减少当所述至少一个存储器单元被停用时，所述位线与所述至少一个存储器单元之间的电流泄漏。电路还包括跟踪装置，其被配置为接收基本上等于沿着电流路径的电流的反射镜电流，跟踪装置被配置为具有基本上等于至少一个存储器单元的所有存储器单元的累积电阻的电阻。

5. 发明授权

US08270240B2 Current leakage reduction 有权
标题翻译：电流泄漏减少
公开(公告)号：US08270240B2
公开(公告)日：2012-09-18
申请号：US12784025
申请日：2010-05-20
申请人： Sung-Chieh Lin , Kuoyuan (Peter) Hsu , Jiann-Tseng Huang , We-Li Liao
发明人： Sung-Chieh Lin , Kuoyuan (Peter) Hsu , Jiann-Tseng Huang , We-Li Liao
IPC分类号： G11C29/00
CPC分类号： G11C8/12 , G11C17/18
摘要： An OTP memory array includes a bit line coupled to a plurality of memory banks. Each memory bank includes a plurality of memory cells, a footer, and a bias device, and is associated with a current mirror. When a memory cell is activated (e.g., for reading) the memory bank including the activated memory cell is referred to as an activated memory bank and other banks are referred to as deactivated memory banks. A current tracking device serves to compensate for bit line leakage current in deactivated memory cells in the activated memory bank. Further, footers and bias devices in deactivated memory banks and associated current mirrors are configured to reduce/eliminate bit line current leakage through deactivated memory cells in deactivated memory banks.
摘要翻译： OTP存储器阵列包括耦合到多个存储体的位线。每个存储体包括多个存储单元，一个页脚和一个偏置装置，并与一个电流镜相关联。当存储器单元被激活（例如，用于读取）时，包括激活的存储器单元的存储体被称为激活的存储体，并且其它存储体被称为禁用存储体。电流跟踪装置用于补偿激活的存储体中的去激活的存储器单元中的位线泄漏电流。此外，禁用存储器组和相关联的电流镜中的脚和偏置器件被配置为通过去激活的存储体中的去激活的存储器单元来减少/消除位线电流泄漏。

6. 发明申请

US20110026354A1 CURRENT LEAKAGE REDUCTION 有权
标题翻译：电流泄漏减少
公开(公告)号：US20110026354A1
公开(公告)日：2011-02-03
申请号：US12784025
申请日：2010-05-20
申请人： Sung-Chieh Lin , Kuoyuan (Peter) Hsu , Jiann-Tseng Huang , We-Li Liao
发明人： Sung-Chieh Lin , Kuoyuan (Peter) Hsu , Jiann-Tseng Huang , We-Li Liao
IPC分类号： G11C5/14 , G11C8/00 , G11C17/00
CPC分类号： G11C8/12 , G11C17/18
摘要： An OTP memory array includes a bit line coupled to a plurality of memory banks. Each memory bank includes a plurality of memory cells, a footer, and a bias device, and is associated with a current mirror. When a memory cell is activated (e.g., for reading) the memory bank including the activated memory cell is referred to as an activated memory bank and other banks are referred to as deactivated memory banks. A current tracking device serves to compensate for bit line leakage current in deactivated memory cells in the activated memory bank. Further, footers and bias devices in deactivated memory banks and associated current mirrors are configured to reduce/eliminate bit line current leakage through deactivated memory cells in deactivated memory banks.
摘要翻译： OTP存储器阵列包括耦合到多个存储体的位线。每个存储体包括多个存储单元，一个页脚和一个偏置装置，并与一个电流镜相关联。当存储器单元被激活（例如，用于读取）时，包括激活的存储器单元的存储体被称为激活的存储体，并且其他存储体被称为去激活存储体。电流跟踪装置用于补偿激活的存储体中的去激活的存储器单元中的位线泄漏电流。此外，禁用存储器组和相关联的电流镜中的脚和偏置器件被配置为通过去激活的存储体中的去激活的存储器单元来减少/消除位线电流泄漏。

7. 发明授权

US08194490B2 Electrical fuse memory arrays 有权
标题翻译：电熔丝存储器阵列
公开(公告)号：US08194490B2
公开(公告)日：2012-06-05
申请号：US12877646
申请日：2010-09-08
申请人： Po-Hung Chen , Chin-Huang Wang , Yen-Chieh Huang , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
发明人： Po-Hung Chen , Chin-Huang Wang , Yen-Chieh Huang , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
IPC分类号： G11C17/18
CPC分类号： G11C17/165
摘要： Some embodiments regard a memory array that has a plurality of eFuse memory cells arranged in rows and columns, a plurality of bit lines, and a plurality of word lines. A column includes a bit line selector, a bit line coupled to the bit line selector, and a plurality of eFuse memory cells. An eFuse memory cell of the column includes a PMOS transistor and an eFuse. A drain of the PMOS transistor is coupled to a first end of the eFuse. A gate of the PMOS transistor is coupled to a word line. A source of the PMOS transistor is coupled to the bit line of the column.
摘要翻译：一些实施例涉及具有以行和列，多个位线和多个字线布置的多个eFuse存储器单元的存储器阵列。列包括位线选择器，耦合到位线选择器的位线和多个eFuse存储器单元。该列的eFuse存储单元包括PMOS晶体管和eFuse。 PMOS晶体管的漏极耦合到eFuse的第一端。 PMOS晶体管的栅极耦合到字线。 PMOS晶体管的源极耦合到列的位线。

8. 发明授权

US08946825B2 Integrated circuit structure to resolve deep-well plasma charging problem and method of forming the same 有权
标题翻译：集成电路结构解决深井等离子体充电问题及其形成方法
公开(公告)号：US08946825B2
公开(公告)日：2015-02-03
申请号：US13433194
申请日：2012-03-28
申请人： David Yen , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
发明人： David Yen , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
IPC分类号： H01L23/62
CPC分类号： H01L27/0928 , H01L21/263 , H01L21/823871 , H01L21/823878 , H01L21/823892 , H01L27/0629 , H01L29/6609
摘要： During various processing operations, ions from process plasma may be transfer to a deep n-well (DNW) formed under devices structures. A reverse-biased diode may be connected to the signal line to protect a gate dielectric formed outside the DNW and is connected to the drain of the transistor formed inside the DNW.
摘要翻译：在各种处理操作期间，来自工艺等离子体的离子可以转移到在器件结构下形成的深n阱（DNW）。反向偏置二极管可以连接到信号线以保护形成在DNW外部的栅极电介质，并且连接到形成在DNW内部的晶体管的漏极。

9. 发明授权

US08692580B2 Sense amplifier 有权
标题翻译：感应放大器
公开(公告)号：US08692580B2
公开(公告)日：2014-04-08
申请号：US13407548
申请日：2012-02-28
申请人： Chen-Ming Hung , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
发明人： Chen-Ming Hung , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
IPC分类号： H03K3/00
CPC分类号： G01R27/08 , G11C7/062 , G11C17/18 , G11C2207/063 , H03F3/45179 , H03F2200/555 , H03F2203/45394 , H03F2203/45674
摘要： An amplifying circuit comprises a bias circuit, a reference circuit, a first circuit, and an amplifying sub-circuit. The bias circuit is configured to provide a bias current. The reference circuit is configured to provide a first differential input based on a reference resistive device and a reference current derived from the bias current. The first circuit is configured to provide a second differential input based on a first current and a first resistance. The amplifying sub-circuit is configured to receive the first differential input and the second differential input and to generate a sense amplifying output indicative of a resistance relationship between the first resistance and a resistance of the reference resistive device.
摘要翻译：放大电路包括偏置电路，参考电路，第一电路和放大子电路。偏置电路被配置为提供偏置电流。参考电路被配置为提供基于参考电阻器件的第一差分输入和从偏置电流导出的参考电流。第一电路被配置为基于第一电流和第一电阻提供第二差分输入。放大子电路被配置为接收第一差分输入和第二差分输入，并且产生指示第一电阻和参考电阻器件的电阻之间的电阻关系的读出放大输出。

10. 发明授权

US09135099B2 Memory error correction 有权
标题翻译：内存纠错
公开(公告)号：US09135099B2
公开(公告)日：2015-09-15
申请号：US13434588
申请日：2012-03-29
申请人： Yun-Han Chen , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
发明人： Yun-Han Chen , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
IPC分类号： G11C29/00 , G06F11/07 , G06F11/10 , H03M13/19 , H03M13/00
CPC分类号： G06F11/073 , G06F11/0793 , G06F11/1008 , H03M13/19 , H03M13/6561
摘要： A method includes, by a first circuit, converting a plurality of bits in a first format to a second format. The plurality of bits in the second format is used, by a second circuit, to program a plurality of memory cells corresponding to the plurality of bits. The first format is a parallel format. The second format is a serial format. The first circuit and the second circuit are electrically coupled together in a chip. In some embodiments, the plurality of bits includes address information, cell data information, and program information of a memory cell that has an error. In some embodiments, the plurality of bits includes word data information of a word and error code and correction information corresponding to the word data information of the word.
摘要翻译：一种方法包括通过第一电路将第一格式的多个比特转换成第二格式。通过第二电路使用第二格式的多个比特来对与多个比特相对应的多个存储单元进行编程。第一种格式是并行格式。第二种格式是串行格式。第一电路和第二电路在芯片中电耦合在一起。在一些实施例中，多个位包括地址信息，单元数据信息和具有错误的存储器单元的程序信息。在一些实施例中，多个比特包括单词的字数据信息和与单词的单词数据信息对应的错误代码和校正信息。

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