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1. 发明授权

US08824234B2 Electrical fuse memory 有权
标题翻译：电熔丝记忆体
公开(公告)号：US08824234B2
公开(公告)日：2014-09-02
申请号：US13771674
申请日：2013-02-20
申请人： Sung-Chieh Lin , David Yen , Wei-Li Liao , Jiann-Tseng Huang , Kuoyuan (Peter) Hsu
发明人： Sung-Chieh Lin , David Yen , Wei-Li Liao , Jiann-Tseng Huang , Kuoyuan (Peter) Hsu
IPC分类号： G11C17/16
CPC分类号： G11C17/16
摘要： A method of reading an eFuse in a column of eFuse memory cells includes electrically disconnecting a first end of the eFuse from a first electrical path. A second electrical path between a second end of the eFuse and a node is activated to bypass a third electrical path, where the third electrical path includes a diode device between the second end of the eFuse and the node. A footer coupled with the node is turned on.
摘要翻译：读取eFuse存储单元列中的eFuse的方法包括将eFuse的第一端与第一电路断开。 eFuse的第二端和节点之间的第二电路被激活以绕过第三电路，其中第三电路包括在eFuse的第二端和节点之间的二极管器件。与节点耦合的页脚被打开。

2. 发明申请

US20100329055A1 MEASURING ELECTRICAL RESISTANCE 有权
标题翻译：测量电阻
公开(公告)号：US20100329055A1
公开(公告)日：2010-12-30
申请号：US12824652
申请日：2010-06-28
申请人： Kuoyuan HSU , Po-Hung CHEN , Jiann-Tseng HUANG , Subramani KENGERI
发明人： Kuoyuan HSU , Po-Hung CHEN , Jiann-Tseng HUANG , Subramani KENGERI
IPC分类号： G11C29/00 , G11C17/16
CPC分类号： G11C13/00 , G11C5/147 , G11C7/00 , G11C7/062 , G11C7/22 , G11C13/0004 , G11C13/004 , G11C16/26 , G11C17/16 , G11C17/165 , G11C17/18 , G11C2013/0045
摘要： A circuit having a first circuit configured to receive an input voltage and generate a first voltage that generates a first current flowing through a resistive device and a second voltage that generates a second current; a node electrically coupled to the resistive device and having a third voltage that generates a third current; and a second circuit configured to generate a fourth voltage having a logic state indicating a logic state of the resistive device.
摘要翻译：一种具有第一电路的电路，其被配置为接收输入电压并产生产生流过电阻器件的第一电流的第一电压和产生第二电流的第二电压; 电耦合到所述电阻装置并具有产生第三电流的第三电压的节点; 以及第二电路，被配置为产生具有指示电阻装置的逻辑状态的逻辑状态的第四电压。

3. 发明申请

US20130107603A1 CIRCUIT AND METHOD FOR GENERATING A READ SIGNAL 有权
标题翻译：用于产生读取信号的电路和方法
公开(公告)号：US20130107603A1
公开(公告)日：2013-05-02
申请号：US13285357
申请日：2011-10-31
申请人： Jiann-Tseng HUANG , Sung-Chieh LIN , Kuoyuan (Peter) HSU
发明人： Jiann-Tseng HUANG , Sung-Chieh LIN , Kuoyuan (Peter) HSU
IPC分类号： G11C17/16
CPC分类号： G11C17/16 , G11C17/18
摘要： A circuit includes a fuse circuit and a control circuit. The fuse circuit has an electrical fuse. The control circuit is configured to receive an input signal having an input pulse, and, based on a feedback signal from the fuse circuit, generates a read pulse smaller than the input pulse for use in reading the data stored in the electrical fuse.
摘要翻译：电路包括熔丝电路和控制电路。保险丝电路具有电熔丝。控制电路被配置为接收具有输入脉冲的输入信号，并且基于来自熔丝电路的反馈信号，产生比用于读取存储在电熔丝中的数据的输入脉冲更小的读取脉冲。

4. 发明授权

US08400860B2 Electrical fuse memory 有权
标题翻译：电熔丝记忆体
公开(公告)号：US08400860B2
公开(公告)日：2013-03-19
申请号：US12839542
申请日：2010-07-20
申请人： Sung-Chieh Lin , David Yen , Wei-Li Liao , Jiann-Tseng Huang , Kuoyuan (Peter) Hsu
发明人： Sung-Chieh Lin , David Yen , Wei-Li Liao , Jiann-Tseng Huang , Kuoyuan (Peter) Hsu
IPC分类号： G11C17/16
CPC分类号： G11C17/16
摘要： Some embodiments regard a memory array that has a plurality of rows and columns. A column includes a program control device, a plurality of eFuse memory cells in the column, a sense amplifier, and a bit line coupling the program control device, the plurality of memory cells in the column, and the sense amplifier. A row includes a plurality of eFuse memory cells in the row, a word line coupling the plurality of eFuse memory cells in the row, and a footer configured as a current path for the plurality of eFuse memory cells in the row.
摘要翻译：一些实施例涉及具有多个行和列的存储器阵列。列包括程序控制装置，列中的多个eFuse存储器单元，读出放大器和耦合程序控制装置，列中的多个存储单元和读出放大器的位线。行包括行中的多个eFuse存储器单元，耦合行中的多个eFuse存储器单元的字线和被配置为行中的多个eFuse存储器单元的当前路径的页脚。

5. 发明申请

US20120081165A1 HIGH VOLTAGE TOLERATIVE DRIVER 审中-公开
标题翻译：高电压驱动器
公开(公告)号：US20120081165A1
公开(公告)日：2012-04-05
申请号：US12894210
申请日：2010-09-30
申请人： Jiann-Tseng HUANG , Sung-Chieh LIN , Kuoyuan HSU , Po-Hung CHEN
发明人： Jiann-Tseng HUANG , Sung-Chieh LIN , Kuoyuan HSU , Po-Hung CHEN
IPC分类号： H03L5/00 , H01H37/76 , H01L25/00
CPC分类号： H03K19/00315 , H03K19/018528
摘要： A high voltage tolerative inverter circuit includes a first PMOS transistor with a source connected to VDDQ and drain connected to a first node; a second PMOS transistor with a source connected to the first node and a drain connected to an output; a first NMOS transistor with a source connected to VSS and a drain connected to a second node; a second NMOS transistor with a source connected to the second node and a drain connected to the output. A gate of the first PMOS transistor is controlled by a first signal having a voltage swing between VDDQ and VSS. A gate of the first NMOS transistor and the second PMOS transistor are controlled by a second signal having a voltage swing between VDD and VSS. VDD is lower than VDDQ. A gate of the second NMOS transistor is biased with a first voltage greater than VSS.
摘要翻译：高耐压逆变器电路包括：第一PMOS晶体管，其源极连接到VDDQ，漏极连接到第一节点; 第二PMOS晶体管，源极连接到第一节点，漏极连接到输出端; 第一NMOS晶体管，源极连接到VSS，漏极连接到第二节点; 第二NMOS晶体管，源极连接到第二节点，漏极连接到输出。第一PMOS晶体管的栅极由具有VDDQ和VSS之间的电压摆幅的第一信号控制。第一NMOS晶体管和第二PMOS晶体管的栅极由具有在VDD和VSS之间的电压摆幅的第二信号控制。 VDD低于VDDQ。第二NMOS晶体管的栅极以大于VSS的第一电压偏置。

6. 发明申请

US20120051162A1 METHOD AND APPARATUS FOR BIT CELL REPAIR 有权
标题翻译：用于位单元修复的方法和装置
公开(公告)号：US20120051162A1
公开(公告)日：2012-03-01
申请号：US12871417
申请日：2010-08-30
申请人： Sung-Chieh Lin , Jiann-Tseng Huang , Wei-Li Liao , Kuoyuan Hsu
发明人： Sung-Chieh Lin , Jiann-Tseng Huang , Wei-Li Liao , Kuoyuan Hsu
IPC分类号： G11C29/04
CPC分类号： G11C29/04 , G11C29/44
摘要： A method includes reading data from a subset of a plurality of memory bit cells of a non-volatile memory. The data identifies an address of at least one individual failed bit cell. The method further includes loading the data directly into a register, receiving an address of data to be accessed, determining if the received address is the address of any individual failed bit cell; and accessing the data of the register if the received address is the address of any individual failed bit cell.
摘要翻译：一种方法包括从非易失性存储器的多个存储位单元的子集读取数据。数据标识至少一个单独故障位单元的地址。该方法还包括将数据直接加载到寄存器中，接收要访问的数据的地址，确定接收的地址是否是任何单个故障位单元的地址; 并且如果接收到的地址是任何单个故障位单元的地址，则访问寄存器的数据。

7. 发明授权

US07616416B2 System to protect electrical fuses 有权
标题翻译：保护电气保险丝的系统
公开(公告)号：US07616416B2
公开(公告)日：2009-11-10
申请号：US11839966
申请日：2007-08-16
申请人： Shine Chung , Jiann-Tseng Huang , Shao-Chang Huang
发明人： Shine Chung , Jiann-Tseng Huang , Shao-Chang Huang
IPC分类号： H02H9/00 , H01H85/00
CPC分类号： G11C17/16 , G11C17/18
摘要： A method and system is disclosed for protecting electrical fuse circuitry. A electrical fuse circuit with electrostatic discharge (ESD) protection has at least one electrical fuse, a programming device coupled in series with the electrical fuse having at least a transistor for receiving a control signal for controlling a programming current flowing through the electrical fuse, a voltage source coupled to the fuse and the programming device for providing the programming current, and a protection module coupled to a gate of the transistor at its first end for reducing charges accumulated at the gate of the transistor due to electric static charges arriving at the voltage source, thereby preventing the programming device from accidentally programming the fuse.
摘要翻译：公开了一种用于保护电熔丝电路的方法和系统。具有静电放电（ESD）保护的电熔丝电路具有至少一个电熔丝，与至少一晶体管串联耦合的编程装置，用于接收用于控制流经电熔丝的编程电流的控制信号，电压源耦合到熔丝和用于提供编程电流的编程装置，以及保护模块，其在其第一端耦合到晶体管的栅极，以减少由于到达电压的电静电而在晶体管的栅极处累积的电荷源，从而防止编程设备意外编程保险丝。

8. 发明授权

US08427857B2 Electrical fuse programming time control scheme 有权
标题翻译：电熔丝编程时间控制方案
公开(公告)号：US08427857B2
公开(公告)日：2013-04-23
申请号：US12774851
申请日：2010-05-06
申请人： Po-Hung Chen , Sung-Chieh Lin , Kuoyuan Hsu , Jiann-Tseng Huang
发明人： Po-Hung Chen , Sung-Chieh Lin , Kuoyuan Hsu , Jiann-Tseng Huang
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/18
摘要： A circuit includes a fuse and a sensing and control circuit. The fuse is coupled between a MOS transistor and a current source node. The sensing and control circuit is configured to receive a programming pulse and output a modified programming signal to the gate of the MOS transistor for programming the fuse. The modified programming signal has a pulse width based on a magnitude of a current through the first fuse.
摘要翻译：电路包括熔丝和感测和控制电路。熔丝耦合在MOS晶体管和电流源节点之间。感测和控制电路被配置为接收编程脉冲并将修改的编程信号输出到MOS晶体管的栅极，以编程保险丝。改进的编程信号具有基于通过第一保险丝的电流的幅度的脉冲宽度。

9. 发明申请

US20120020177A1 ELECTRICAL FUSE MEMORY 有权
标题翻译：电子保险丝存储器
公开(公告)号：US20120020177A1
公开(公告)日：2012-01-26
申请号：US12839542
申请日：2010-07-20
申请人： Sung-Chieh LIN , David YEN , Wei-Li LIAO , Jiann-Tseng HUANG , Kuoyuan (Peter) HSU
发明人： Sung-Chieh LIN , David YEN , Wei-Li LIAO , Jiann-Tseng HUANG , Kuoyuan (Peter) HSU
IPC分类号： G11C17/16
CPC分类号： G11C17/16
摘要： Some embodiments regard a memory array that has a plurality of rows and columns. A column includes a program control device, a plurality of eFuse memory cells in the column, a sense amplifier, and a bit line coupling the program control device, the plurality of memory cells in the column, and the sense amplifier. A row includes a plurality of eFuse memory cells in the row, a word line coupling the plurality of eFuse memory cells in the row, and a footer configured as a current path for the plurality of eFuse memory cells in the row.
摘要翻译：一些实施例涉及具有多个行和列的存储器阵列。列包括程序控制装置，列中的多个eFuse存储器单元，读出放大器和耦合程序控制装置，列中的多个存储单元和读出放大器的位线。行包括行中的多个eFuse存储器单元，耦合行中的多个eFuse存储器单元的字线和被配置为行中的多个eFuse存储器单元的当前路径的页脚。

10. 发明申请

US20070279816A1 SYSTEM TO PROTECT ELECTRICAL FUSES 有权
标题翻译：保护电熔丝的系统
公开(公告)号：US20070279816A1
公开(公告)日：2007-12-06
申请号：US11839966
申请日：2007-08-16
申请人： Shine Chung , Jiann-Tseng Huang , Shao-Chang Huang
发明人： Shine Chung , Jiann-Tseng Huang , Shao-Chang Huang
IPC分类号： H02H9/04 , H03K19/003
CPC分类号： G11C17/16 , G11C17/18
摘要： A method and system is disclosed for protecting electrical fuse circuitry. A electrical fuse circuit with electrostatic discharge (ESD) protection has at least one electrical fuse, a programming device coupled in series with the electrical fuse having at least a transistor for receiving a control signal for controlling a programming current flowing through the electrical fuse, a voltage source coupled to the fuse and the programming device for providing the programming current, and a protection module coupled to a gate of the transistor at its first end for reducing charges accumulated at the gate of the transistor due to electric static charges arriving at the voltage source, thereby preventing the programming device from accidentally programming the fuse.
摘要翻译：公开了一种用于保护电熔丝电路的方法和系统。具有静电放电（ESD）保护的电熔丝电路具有至少一个电熔丝，与至少一晶体管串联耦合的编程装置，用于接收用于控制流经电熔丝的编程电流的控制信号，电压源耦合到熔丝和用于提供编程电流的编程装置，以及保护模块，其在其第一端耦合到晶体管的栅极，以减少由于到达电压的电静电而在晶体管的栅极处累积的电荷源，从而防止编程设备意外编程保险丝。

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