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1. 发明授权

US08194490B2 Electrical fuse memory arrays 有权
标题翻译：电熔丝存储器阵列
公开(公告)号：US08194490B2
公开(公告)日：2012-06-05
申请号：US12877646
申请日：2010-09-08
申请人： Po-Hung Chen , Chin-Huang Wang , Yen-Chieh Huang , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
发明人： Po-Hung Chen , Chin-Huang Wang , Yen-Chieh Huang , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
IPC分类号： G11C17/18
CPC分类号： G11C17/165
摘要： Some embodiments regard a memory array that has a plurality of eFuse memory cells arranged in rows and columns, a plurality of bit lines, and a plurality of word lines. A column includes a bit line selector, a bit line coupled to the bit line selector, and a plurality of eFuse memory cells. An eFuse memory cell of the column includes a PMOS transistor and an eFuse. A drain of the PMOS transistor is coupled to a first end of the eFuse. A gate of the PMOS transistor is coupled to a word line. A source of the PMOS transistor is coupled to the bit line of the column.
摘要翻译：一些实施例涉及具有以行和列，多个位线和多个字线布置的多个eFuse存储器单元的存储器阵列。列包括位线选择器，耦合到位线选择器的位线和多个eFuse存储器单元。该列的eFuse存储单元包括PMOS晶体管和eFuse。 PMOS晶体管的漏极耦合到eFuse的第一端。 PMOS晶体管的栅极耦合到字线。 PMOS晶体管的源极耦合到列的位线。

2. 发明授权

US08466732B2 Voltage level shifter 有权
标题翻译：电压电平转换器
公开(公告)号：US08466732B2
公开(公告)日：2013-06-18
申请号：US12900650
申请日：2010-10-08
申请人： Po-Hung Chen , Kuoyuan (Peter) Hsu , David Yen , Sung-Chieh Lin
发明人： Po-Hung Chen , Kuoyuan (Peter) Hsu , David Yen , Sung-Chieh Lin
IPC分类号： H03L5/00
CPC分类号： H03K3/356165
摘要： An input of a first inverter is configured to serve as an input node. An output of the first inverter is coupled to an input of a second inverter. An output of the second inverter is configured to serve as an output node. An input of a third inverter is coupled to an input of the first inverter. A gate of a first NMOS transistor is coupled to an output of the third inverter. A drain of the first NMOS transistor is coupled to the second inverter. A source of the first NMOS transistor is configured to serve as a level input node. When the input node is configured to receive a low logic level, the output node is configured to receive a voltage level provided by a voltage level at the level input node.
摘要翻译：第一反相器的输入被配置为用作输入节点。第一反相器的输出耦合到第二反相器的输入端。第二反相器的输出被配置为用作输出节点。第三反相器的输入耦合到第一反相器的输入端。第一NMOS晶体管的栅极耦合到第三反相器的输出端。第一NMOS晶体管的漏极耦合到第二反相器。第一NMOS晶体管的源极被配置为用作电平输入节点。当输入节点被配置为接收低逻辑电平时，输出节点被配置为接收由电平输入节点处的电压电平提供的电压电平。

3. 发明授权

US08400860B2 Electrical fuse memory 有权
标题翻译：电熔丝记忆体
公开(公告)号：US08400860B2
公开(公告)日：2013-03-19
申请号：US12839542
申请日：2010-07-20
申请人： Sung-Chieh Lin , David Yen , Wei-Li Liao , Jiann-Tseng Huang , Kuoyuan (Peter) Hsu
发明人： Sung-Chieh Lin , David Yen , Wei-Li Liao , Jiann-Tseng Huang , Kuoyuan (Peter) Hsu
IPC分类号： G11C17/16
CPC分类号： G11C17/16
摘要： Some embodiments regard a memory array that has a plurality of rows and columns. A column includes a program control device, a plurality of eFuse memory cells in the column, a sense amplifier, and a bit line coupling the program control device, the plurality of memory cells in the column, and the sense amplifier. A row includes a plurality of eFuse memory cells in the row, a word line coupling the plurality of eFuse memory cells in the row, and a footer configured as a current path for the plurality of eFuse memory cells in the row.
摘要翻译：一些实施例涉及具有多个行和列的存储器阵列。列包括程序控制装置，列中的多个eFuse存储器单元，读出放大器和耦合程序控制装置，列中的多个存储单元和读出放大器的位线。行包括行中的多个eFuse存储器单元，耦合行中的多个eFuse存储器单元的字线和被配置为行中的多个eFuse存储器单元的当前路径的页脚。

4. 发明授权

US08946825B2 Integrated circuit structure to resolve deep-well plasma charging problem and method of forming the same 有权
标题翻译：集成电路结构解决深井等离子体充电问题及其形成方法
公开(公告)号：US08946825B2
公开(公告)日：2015-02-03
申请号：US13433194
申请日：2012-03-28
申请人： David Yen , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
发明人： David Yen , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
IPC分类号： H01L23/62
CPC分类号： H01L27/0928 , H01L21/263 , H01L21/823871 , H01L21/823878 , H01L21/823892 , H01L27/0629 , H01L29/6609
摘要： During various processing operations, ions from process plasma may be transfer to a deep n-well (DNW) formed under devices structures. A reverse-biased diode may be connected to the signal line to protect a gate dielectric formed outside the DNW and is connected to the drain of the transistor formed inside the DNW.
摘要翻译：在各种处理操作期间，来自工艺等离子体的离子可以转移到在器件结构下形成的深n阱（DNW）。反向偏置二极管可以连接到信号线以保护形成在DNW外部的栅极电介质，并且连接到形成在DNW内部的晶体管的漏极。

5. 发明授权

US08767498B2 Circuit and method for generating a read signal 有权
标题翻译：用于产生读取信号的电路和方法
公开(公告)号：US08767498B2
公开(公告)日：2014-07-01
申请号：US13285357
申请日：2011-10-31
申请人： Jiann-Tseng Huang , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
发明人： Jiann-Tseng Huang , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
IPC分类号： G11C17/14
CPC分类号： G11C17/16 , G11C17/18
摘要： A circuit includes a fuse circuit and a control circuit. The fuse circuit has an electrical fuse. The control circuit is configured to receive an input signal having an input pulse, and, based on a feedback signal from the fuse circuit, generates a read pulse smaller than the input pulse for use in reading the data stored in the electrical fuse.
摘要翻译：电路包括熔丝电路和控制电路。保险丝电路具有电熔丝。控制电路被配置为接收具有输入脉冲的输入信号，并且基于来自熔丝电路的反馈信号，产生比用于读取存储在电熔丝中的数据的输入脉冲更小的读取脉冲。

6. 发明授权

US08692580B2 Sense amplifier 有权
标题翻译：感应放大器
公开(公告)号：US08692580B2
公开(公告)日：2014-04-08
申请号：US13407548
申请日：2012-02-28
申请人： Chen-Ming Hung , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
发明人： Chen-Ming Hung , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
IPC分类号： H03K3/00
CPC分类号： G01R27/08 , G11C7/062 , G11C17/18 , G11C2207/063 , H03F3/45179 , H03F2200/555 , H03F2203/45394 , H03F2203/45674
摘要： An amplifying circuit comprises a bias circuit, a reference circuit, a first circuit, and an amplifying sub-circuit. The bias circuit is configured to provide a bias current. The reference circuit is configured to provide a first differential input based on a reference resistive device and a reference current derived from the bias current. The first circuit is configured to provide a second differential input based on a first current and a first resistance. The amplifying sub-circuit is configured to receive the first differential input and the second differential input and to generate a sense amplifying output indicative of a resistance relationship between the first resistance and a resistance of the reference resistive device.
摘要翻译：放大电路包括偏置电路，参考电路，第一电路和放大子电路。偏置电路被配置为提供偏置电流。参考电路被配置为提供基于参考电阻器件的第一差分输入和从偏置电流导出的参考电流。第一电路被配置为基于第一电流和第一电阻提供第二差分输入。放大子电路被配置为接收第一差分输入和第二差分输入，并且产生指示第一电阻和参考电阻器件的电阻之间的电阻关系的读出放大输出。

7. 发明授权

US08824234B2 Electrical fuse memory 有权
标题翻译：电熔丝记忆体
公开(公告)号：US08824234B2
公开(公告)日：2014-09-02
申请号：US13771674
申请日：2013-02-20
申请人： Sung-Chieh Lin , David Yen , Wei-Li Liao , Jiann-Tseng Huang , Kuoyuan (Peter) Hsu
发明人： Sung-Chieh Lin , David Yen , Wei-Li Liao , Jiann-Tseng Huang , Kuoyuan (Peter) Hsu
IPC分类号： G11C17/16
CPC分类号： G11C17/16
摘要： A method of reading an eFuse in a column of eFuse memory cells includes electrically disconnecting a first end of the eFuse from a first electrical path. A second electrical path between a second end of the eFuse and a node is activated to bypass a third electrical path, where the third electrical path includes a diode device between the second end of the eFuse and the node. A footer coupled with the node is turned on.
摘要翻译：读取eFuse存储单元列中的eFuse的方法包括将eFuse的第一端与第一电路断开。 eFuse的第二端和节点之间的第二电路被激活以绕过第三电路，其中第三电路包括在eFuse的第二端和节点之间的二极管器件。与节点耦合的页脚被打开。

8. 发明授权

US08787109B2 Word line driver having a control switch 有权
标题翻译：具有控制开关的字线驱动器
公开(公告)号：US08787109B2
公开(公告)日：2014-07-22
申请号：US13466518
申请日：2012-05-08
申请人： Wei-Li Liao , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
发明人： Wei-Li Liao , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
IPC分类号： G11C8/00 , G11C5/14 , G11C16/06
CPC分类号： G11C8/08
摘要： A word line driver including a control switch configured to receive a control signal, where the control switch is between a first node configured to receive an operating voltage signal and a second node configured to determine an output of the word line driver. The word line driver further includes a cross-coupled amplifier electrically connected to the second node. The word line driver further includes at least one inverter electrically connected to the cross-coupled amplifier. A semiconductor device including the word line driver and a memory array including at least one electronic fuse.
摘要翻译：一种字线驱动器，包括被配置为接收控制信号的控制开关，其中所述控制开关位于被配置为接收工作电压信号的第一节点和被配置为确定所述字线驱动器的输出的第二节点之间。字线驱动器还包括电连接到第二节点的交叉耦合放大器。字线驱动器还包括电连接到交叉耦合放大器的至少一个反相器。包括字线驱动器和包括至少一个电子熔丝的存储器阵列的半导体器件。

9. 发明授权

US08625324B2 Non-salicide polysilicon fuse 有权
标题翻译：非硅化物多晶硅保险丝
公开(公告)号：US08625324B2
公开(公告)日：2014-01-07
申请号：US13107441
申请日：2011-05-13
申请人： Sung-Chieh Lin , David Yen , Chi-Hsu Chiu , Kuoyuan (Peter) Hsu
发明人： Sung-Chieh Lin , David Yen , Chi-Hsu Chiu , Kuoyuan (Peter) Hsu
IPC分类号： G11C17/00 , H01L23/52
CPC分类号： H01L23/5256 , G11C17/10 , G11C17/16 , H01L2924/0002 , H01L2924/00
摘要： The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a non-salicided polysilicon fuse. The non-salicided polysilicon fuse and a programming transistor form a one-time programmable (OTP) memory cell, which can be programmed with a low programming voltage.
摘要翻译：本文公开的方法和结构的实施例提供了形成和编程非水化多晶硅熔丝的机制。非水银多晶硅熔丝和编程晶体管形成一个可编程的编程电压低的一次可编程（OTP）存储单元。

10. 发明授权

US08542549B2 Electrical fuse bit cell 有权
标题翻译：电熔丝位元
公开(公告)号：US08542549B2
公开(公告)日：2013-09-24
申请号：US13205009
申请日：2011-08-08
申请人： Sung-Chieh Lin , Wei-Li Liao , Kuoyuan (Peter) Hsu
发明人： Sung-Chieh Lin , Wei-Li Liao , Kuoyuan (Peter) Hsu
IPC分类号： G11C17/18
CPC分类号： G11C17/16 , G11C17/18
摘要： An electrical fuse (eFuse) bit cell includes a program transistor, a read transistor, and an eFuse. The program transistor has a first program terminal, a second program terminal, and a third program terminal. The read transistor has a first read terminal, a second read terminal, and a third read terminal. The eFuse has a first end and a second end. The first end, the first program terminal, and the second read terminal are coupled together. The read transistor is configured to be off and the program transistor is configured to be on when the eFuse bit cell is in a program mode. The program transistor is configured to be off and the read transistor is configured to be on when the eFuse bit cell is in a read mode.
摘要翻译：电熔丝（eFuse）位单元包括程序晶体管，读晶体管和eFuse。程序晶体管具有第一程序终端，第二程序终端和第三程序终端。读取晶体管具有第一读取端子，第二读取端子和第三读取端子。 eFuse具有第一端和第二端。第一端，第一程序终端和第二读终端耦合在一起。读晶体管被配置为截止，并且当eFuse位单元处于编程模式时，程序晶体管被配置为导通。程序晶体管被配置为截止，并且当eFuse位单元处于读取模式时，读取晶体管被配置为导通。

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